105 #define MBUS_CONF(port, bwlimit, qos, acs, bwl0, bwl1, bwl2)	\  macro
120 	MBUS_CONF(   CPU,  true, HIGHEST, 0,  512,  256,  128);  in mctl_set_master_priority_h3()
121 	MBUS_CONF(   GPU,  true,    HIGH, 0, 1536, 1024,  256);  in mctl_set_master_priority_h3()
122 	MBUS_CONF(UNUSED,  true, HIGHEST, 0,  512,  256,   96);  in mctl_set_master_priority_h3()
123 	MBUS_CONF(   DMA,  true, HIGHEST, 0,  256,  128,   32);  in mctl_set_master_priority_h3()
124 	MBUS_CONF(    VE,  true,    HIGH, 0, 1792, 1600,  256);  in mctl_set_master_priority_h3()
125 	MBUS_CONF(   CSI,  true, HIGHEST, 0,  256,  128,   32);  in mctl_set_master_priority_h3()
126 	MBUS_CONF(  NAND,  true,    HIGH, 0,  256,  128,   64);  in mctl_set_master_priority_h3()
127 	MBUS_CONF(    SS,  true, HIGHEST, 0,  256,  128,   64);  in mctl_set_master_priority_h3()
128 	MBUS_CONF(    TS,  true, HIGHEST, 0,  256,  128,   64);  in mctl_set_master_priority_h3()
129 	MBUS_CONF(    DI,  true,    HIGH, 0, 1024,  256,   64);  in mctl_set_master_priority_h3()
130 	MBUS_CONF(    DE,  true, HIGHEST, 3, 8192, 6120, 1024);  in mctl_set_master_priority_h3()
131 	MBUS_CONF(DE_CFD,  true,    HIGH, 0, 1024,  288,   64);  in mctl_set_master_priority_h3()
145 	MBUS_CONF(   CPU,  true, HIGHEST, 0,  160,  100,   80);  in mctl_set_master_priority_a64()
146 	MBUS_CONF(   GPU, false,    HIGH, 0, 1536, 1400,  256);  in mctl_set_master_priority_a64()
147 	MBUS_CONF(UNUSED,  true, HIGHEST, 0,  512,  256,   96);  in mctl_set_master_priority_a64()
148 	MBUS_CONF(   DMA,  true,    HIGH, 0,  256,   80,  100);  in mctl_set_master_priority_a64()
149 	MBUS_CONF(    VE,  true,    HIGH, 0, 1792, 1600,  256);  in mctl_set_master_priority_a64()
150 	MBUS_CONF(   CSI,  true,    HIGH, 0,  256,  128,    0);  in mctl_set_master_priority_a64()
151 	MBUS_CONF(  NAND,  true,    HIGH, 0,  256,  128,   64);  in mctl_set_master_priority_a64()
152 	MBUS_CONF(    SS,  true, HIGHEST, 0,  256,  128,   64);  in mctl_set_master_priority_a64()
153 	MBUS_CONF(    TS,  true, HIGHEST, 0,  256,  128,   64);  in mctl_set_master_priority_a64()
154 	MBUS_CONF(    DI,  true,    HIGH, 0, 1024,  256,   64);  in mctl_set_master_priority_a64()
155 	MBUS_CONF(    DE,  true,    HIGH, 2, 8192, 6144, 2048);  in mctl_set_master_priority_a64()
156 	MBUS_CONF(DE_CFD,  true,    HIGH, 0, 1280,  144,   64);  in mctl_set_master_priority_a64()
175 	MBUS_CONF(   CPU, true, HIGHEST, 0,  300,  260,  150);  in mctl_set_master_priority_h5()
176 	MBUS_CONF(   GPU, true, HIGHEST, 0,  600,  400,  200);  in mctl_set_master_priority_h5()
177 	MBUS_CONF(UNUSED, true, HIGHEST, 0,  512,  256,   96);  in mctl_set_master_priority_h5()
178 	MBUS_CONF(   DMA, true, HIGHEST, 0,  256,  128,   32);  in mctl_set_master_priority_h5()
179 	MBUS_CONF(    VE, true, HIGHEST, 0, 1900, 1500, 1000);  in mctl_set_master_priority_h5()
180 	MBUS_CONF(   CSI, true, HIGHEST, 0,  150,  120,  100);  in mctl_set_master_priority_h5()
181 	MBUS_CONF(  NAND, true,    HIGH, 0,  256,  128,   64);  in mctl_set_master_priority_h5()
182 	MBUS_CONF(    SS, true, HIGHEST, 0,  256,  128,   64);  in mctl_set_master_priority_h5()
183 	MBUS_CONF(    TS, true, HIGHEST, 0,  256,  128,   64);  in mctl_set_master_priority_h5()
184 	MBUS_CONF(    DI, true,    HIGH, 0, 1024,  256,   64);  in mctl_set_master_priority_h5()
185 	MBUS_CONF(    DE, true, HIGHEST, 3, 3400, 2400, 1024);  in mctl_set_master_priority_h5()
186 	MBUS_CONF(DE_CFD, true, HIGHEST, 0,  600,  400,  200);  in mctl_set_master_priority_h5()
203 	MBUS_CONF(     CPU, true, HIGHEST, 0,  300,  260,  150);  in mctl_set_master_priority_r40()
204 	MBUS_CONF(     GPU, true, HIGHEST, 0,  600,  400,  200);  in mctl_set_master_priority_r40()
205 	MBUS_CONF(  UNUSED, true, HIGHEST, 0,  512,  256,   96);  in mctl_set_master_priority_r40()
206 	MBUS_CONF(     DMA, true, HIGHEST, 0,  256,  128,   32);  in mctl_set_master_priority_r40()
207 	MBUS_CONF(      VE, true, HIGHEST, 0, 1900, 1500, 1000);  in mctl_set_master_priority_r40()
208 	MBUS_CONF(     CSI, true, HIGHEST, 0,  150,  120,  100);  in mctl_set_master_priority_r40()
209 	MBUS_CONF(    NAND, true,    HIGH, 0,  256,  128,   64);  in mctl_set_master_priority_r40()
210 	MBUS_CONF(      SS, true, HIGHEST, 0,  256,  128,   64);  in mctl_set_master_priority_r40()
211 	MBUS_CONF(      TS, true, HIGHEST, 0,  256,  128,   64);  in mctl_set_master_priority_r40()
212 	MBUS_CONF(      DI, true,    HIGH, 0, 1024,  256,   64);  in mctl_set_master_priority_r40()
218 	MBUS_CONF(      DE, true,    HIGH, 0,  128,   48,    0);  in mctl_set_master_priority_r40()
219 	MBUS_CONF(  DE_CFD, true,    HIGH, 0,  384,  256,    0);  in mctl_set_master_priority_r40()
220 	MBUS_CONF(UNKNOWN1, true, HIGHEST, 0,  512,  384,  256);  in mctl_set_master_priority_r40()
221 	MBUS_CONF(UNKNOWN2, true, HIGHEST, 2, 8192, 6144, 1024);  in mctl_set_master_priority_r40()
222 	MBUS_CONF(UNKNOWN3, true,    HIGH, 0, 1280,  144,   64);  in mctl_set_master_priority_r40()