Lines Matching +full:refresh +full:- +full:power +full:- +full:source
1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2007-2015 Allwinner Technology Co.
23 writel(val | PIR_INIT, &mctl_ctl->pir); in mctl_phy_init()
24 mctl_await_completion(&mctl_ctl->pgsr[0], PGSR_INIT_DONE, 0x1); in mctl_phy_init()
33 clrbits_le32(&mctl_ctl->pgcr[0], 1 << 26); in mctl_set_bit_delays()
37 writel(DXBDLR_WRITE_DELAY(para->dx_write_delays[i][j]) | in mctl_set_bit_delays()
38 DXBDLR_READ_DELAY(para->dx_read_delays[i][j]), in mctl_set_bit_delays()
39 &mctl_ctl->dx[i].bdlr[j]); in mctl_set_bit_delays()
42 writel(ACBDLR_WRITE_DELAY(para->ac_delays[i]), in mctl_set_bit_delays()
43 &mctl_ctl->acbdlr[i]); in mctl_set_bit_delays()
48 writel(0x6 << 24, &mctl_ctl->dx[i].sdlr); in mctl_set_bit_delays()
51 setbits_le32(&mctl_ctl->pgcr[0], 1 << 26); in mctl_set_bit_delays()
101 writel(cfg0, &mctl_com->mcr[port][0]); in mbus_configure_port()
102 writel(cfg1, &mctl_com->mcr[port][1]); in mbus_configure_port()
115 writel((1 << 16) | (400 << 0), &mctl_com->bwcr); in mctl_set_master_priority_h3()
118 writel(0x00000001, &mctl_com->mapr); in mctl_set_master_priority_h3()
140 writel(399, &mctl_com->tmr); in mctl_set_master_priority_a64()
141 writel((1 << 16), &mctl_com->bwcr); in mctl_set_master_priority_a64()
143 /* Port 2 is reserved per Allwinner's linux-3.10 source, yet they in mctl_set_master_priority_a64()
158 writel(0x81000004, &mctl_com->mdfs_bwlr[2]); in mctl_set_master_priority_a64()
167 writel(399, &mctl_com->tmr); in mctl_set_master_priority_h5()
168 writel((1 << 16), &mctl_com->bwcr); in mctl_set_master_priority_h5()
171 writel(0x00000001, &mctl_com->mapr); in mctl_set_master_priority_h5()
173 /* Port 2 is reserved per Allwinner's linux-3.10 source, yet in mctl_set_master_priority_h5()
195 writel(399, &mctl_com->tmr); in mctl_set_master_priority_r40()
196 writel((1 << 16), &mctl_com->bwcr); in mctl_set_master_priority_r40()
199 writel(0x00000001, &mctl_com->mapr); in mctl_set_master_priority_r40()
201 /* Port 2 is reserved per Allwinner's linux-3.10 source, yet in mctl_set_master_priority_r40()
283 clrsetbits_le32(&mctl_ctl->zqcr, 0xffff, in mctl_h3_zq_calibration_quirk()
286 writel(PIR_CLRSR, &mctl_ctl->pir); in mctl_h3_zq_calibration_quirk()
289 reg_val = readl(&mctl_ctl->zqdr[0]); in mctl_h3_zq_calibration_quirk()
292 writel(reg_val, &mctl_ctl->zqdr[0]); in mctl_h3_zq_calibration_quirk()
294 reg_val = readl(&mctl_ctl->zqdr[1]); in mctl_h3_zq_calibration_quirk()
297 writel(reg_val, &mctl_ctl->zqdr[1]); in mctl_h3_zq_calibration_quirk()
298 writel(reg_val, &mctl_ctl->zqdr[2]); in mctl_h3_zq_calibration_quirk()
304 writel(0x0a0a0a0a, &mctl_ctl->zqdr[2]); in mctl_h3_zq_calibration_quirk()
311 &mctl_ctl->zqcr); in mctl_h3_zq_calibration_quirk()
313 writel(PIR_CLRSR, &mctl_ctl->pir); in mctl_h3_zq_calibration_quirk()
316 zq_val[i] = readl(&mctl_ctl->zqdr[0]) & 0xff; in mctl_h3_zq_calibration_quirk()
317 writel(REPEAT_BYTE(zq_val[i]), &mctl_ctl->zqdr[2]); in mctl_h3_zq_calibration_quirk()
319 writel(PIR_CLRSR, &mctl_ctl->pir); in mctl_h3_zq_calibration_quirk()
322 val = readl(&mctl_ctl->zqdr[0]) >> 24; in mctl_h3_zq_calibration_quirk()
323 zq_val[i] |= bin_to_mgray(mgray_to_bin(val) - 1) << 8; in mctl_h3_zq_calibration_quirk()
326 writel((zq_val[1] << 16) | zq_val[0], &mctl_ctl->zqdr[0]); in mctl_h3_zq_calibration_quirk()
327 writel((zq_val[3] << 16) | zq_val[2], &mctl_ctl->zqdr[1]); in mctl_h3_zq_calibration_quirk()
330 &mctl_ctl->zqdr[2]); in mctl_h3_zq_calibration_quirk()
349 (para->bank_bits == 3 ? MCTL_CR_EIGHT_BANKS : MCTL_CR_FOUR_BANKS) | in mctl_set_cr()
350 MCTL_CR_BUS_FULL_WIDTH(para->bus_full_width) | in mctl_set_cr()
351 (para->dual_rank ? MCTL_CR_DUAL_RANK : MCTL_CR_SINGLE_RANK) | in mctl_set_cr()
352 MCTL_CR_PAGE_SIZE(para->page_size) | in mctl_set_cr()
353 MCTL_CR_ROW_BITS(para->row_bits), &mctl_com->cr); in mctl_set_cr()
356 if (para->dual_rank) in mctl_set_cr()
360 setbits_le32(&mctl_com->cr_r1, MCTL_CR_R1_MUX_A15); in mctl_set_cr()
371 clrbits_le32(&ccm->mbus0_clk_cfg, MBUS_CLK_GATE); in mctl_sys_init()
372 clrbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET); in mctl_sys_init()
373 clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); in mctl_sys_init()
374 clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); in mctl_sys_init()
375 clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN); in mctl_sys_init()
377 clrbits_le32(&ccm->pll11_cfg, CCM_PLL11_CTRL_EN); in mctl_sys_init()
380 clrbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST); in mctl_sys_init()
385 clrsetbits_le32(&ccm->dram_clk_cfg, in mctl_sys_init()
393 clrsetbits_le32(&ccm->dram_clk_cfg, in mctl_sys_init()
400 mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0); in mctl_sys_init()
402 setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); in mctl_sys_init()
403 setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); in mctl_sys_init()
404 setbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET); in mctl_sys_init()
405 setbits_le32(&ccm->mbus0_clk_cfg, MBUS_CLK_GATE); in mctl_sys_init()
407 setbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST); in mctl_sys_init()
410 writel(socid == SOCID_H5 ? 0x8000 : 0xc00e, &mctl_ctl->clken); in mctl_sys_init()
433 clrbits_le32(&mctl_ctl->pgcr[0], (1 << 30) | 0x3f); in mctl_channel_init()
435 setbits_le32(&mctl_ctl->pgcr[1], (1 << 24) | (1 << 26)); in mctl_channel_init()
437 clrsetbits_le32(&mctl_ctl->pgcr[1], 1 << 24, 1 << 26); in mctl_channel_init()
440 writel(PROTECT_MAGIC, &mctl_com->protect); in mctl_channel_init()
442 clrsetbits_le32(&mctl_ctl->upd2, 0xfff << 16, 0x50 << 16); in mctl_channel_init()
443 writel(0x0, &mctl_com->protect); in mctl_channel_init()
457 clrsetbits_le32(&mctl_ctl->dx[i].gcr, clearmask, setmask); in mctl_channel_init()
461 clrsetbits_le32(&mctl_ctl->aciocr, socid == SOCID_H5 ? (0x1 << 11) : 0, in mctl_channel_init()
465 setbits_le32(&mctl_ctl->pgcr[2], 0x3 << 6); in mctl_channel_init()
469 clrbits_le32(&mctl_ctl->pgcr[0], (0x3 << 14) | (0x3 << 12)); in mctl_channel_init()
472 clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 << 8), in mctl_channel_init()
476 clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 << 8), in mctl_channel_init()
480 clrbits_le32(&mctl_ctl->pgcr[0], (0x3 << 14) | (0x3 << 12)); in mctl_channel_init()
483 clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 << 8), in mctl_channel_init()
488 if (!para->bus_full_width) { in mctl_channel_init()
490 writel(0x0, &mctl_ctl->dx[2].gcr); in mctl_channel_init()
491 writel(0x0, &mctl_ctl->dx[3].gcr); in mctl_channel_init()
493 writel(0x0, &mctl_ctl->dx[1].gcr); in mctl_channel_init()
500 clrsetbits_le32(&mctl_ctl->dtcr, 0xf << 24, in mctl_channel_init()
501 (para->dual_rank ? 0x3 : 0x1) << 24); in mctl_channel_init()
512 clrsetbits_le32(&mctl_ctl->zqcr, 0xffffff, CONFIG_DRAM_ZQ); in mctl_channel_init()
518 clrsetbits_le32(&mctl_ctl->zqcr, 0xffffff, CONFIG_DRAM_ZQ); in mctl_channel_init()
525 if (readl(&mctl_ctl->pgsr[0]) & (0xfe << 20)) { in mctl_channel_init()
527 if (((readl(&mctl_ctl->dx[0].gsr[0]) >> 24) & 0x2) in mctl_channel_init()
529 || ((readl(&mctl_ctl->dx[1].gsr[0]) >> 24) & 0x2) in mctl_channel_init()
532 clrsetbits_le32(&mctl_ctl->dtcr, 0xf << 24, 0x1 << 24); in mctl_channel_init()
533 para->dual_rank = 0; in mctl_channel_init()
538 if (((readl(&mctl_ctl->dx[2].gsr[0]) >> 24) & 0x1) || in mctl_channel_init()
539 ((readl(&mctl_ctl->dx[3].gsr[0]) >> 24) & 0x1)) { in mctl_channel_init()
540 writel(0x0, &mctl_ctl->dx[2].gcr); in mctl_channel_init()
541 writel(0x0, &mctl_ctl->dx[3].gcr); in mctl_channel_init()
542 para->bus_full_width = 0; in mctl_channel_init()
545 if ((readl(&mctl_ctl->dx[1].gsr[0]) >> 24) & 0x1) { in mctl_channel_init()
546 writel(0x0, &mctl_ctl->dx[1].gcr); in mctl_channel_init()
547 para->bus_full_width = 0; in mctl_channel_init()
554 /* re-train */ in mctl_channel_init()
556 if (readl(&mctl_ctl->pgsr[0]) & (0xfe << 20)) in mctl_channel_init()
561 mctl_await_completion(&mctl_ctl->statr, 0x1, 0x1); in mctl_channel_init()
563 /* liuke added for refresh debug */ in mctl_channel_init()
564 setbits_le32(&mctl_ctl->rfshctl0, 0x1 << 31); in mctl_channel_init()
566 clrbits_le32(&mctl_ctl->rfshctl0, 0x1 << 31); in mctl_channel_init()
571 writel(0x00aa0060, &mctl_ctl->pgcr[3]); in mctl_channel_init()
573 writel(0xc0aa0060, &mctl_ctl->pgcr[3]); in mctl_channel_init()
575 /* power down zq calibration module for power save */ in mctl_channel_init()
576 setbits_le32(&mctl_ctl->zqcr, ZQCR_PWRDOWN); in mctl_channel_init()
579 writel(0xffffffff, &mctl_com->maer); in mctl_channel_init()
587 para->page_size = 512; in mctl_auto_detect_dram_size()
588 para->row_bits = 16; in mctl_auto_detect_dram_size()
589 para->bank_bits = 2; in mctl_auto_detect_dram_size()
592 for (para->row_bits = 11; para->row_bits < 16; para->row_bits++) in mctl_auto_detect_dram_size()
593 if (mctl_mem_matches((1 << (para->row_bits + para->bank_bits)) * para->page_size)) in mctl_auto_detect_dram_size()
597 para->bank_bits = 3; in mctl_auto_detect_dram_size()
600 for (para->bank_bits = 2; para->bank_bits < 3; para->bank_bits++) in mctl_auto_detect_dram_size()
601 if (mctl_mem_matches((1 << para->bank_bits) * para->page_size)) in mctl_auto_detect_dram_size()
605 para->page_size = 8192; in mctl_auto_detect_dram_size()
608 for (para->page_size = 512; para->page_size < 8192; para->page_size *= 2) in mctl_auto_detect_dram_size()
609 if (mctl_mem_matches(para->page_size)) in mctl_auto_detect_dram_size()
741 writel(0x00000303, &mctl_ctl->odtmap); in sunxi_dram_init()
743 writel(0x00000201, &mctl_ctl->odtmap); in sunxi_dram_init()
748 writel(0x0c000400, &mctl_ctl->odtcfg); in sunxi_dram_init()
752 setbits_le32(&mctl_ctl->vtfcr, in sunxi_dram_init()
755 clrbits_le32(&mctl_ctl->pgcr[2], (1 << 13)); in sunxi_dram_init()
759 setbits_le32(&mctl_com->cccr, 1 << 31); in sunxi_dram_init()