1 // SPDX-License-Identifier: GPL-2.0+
17 	      int mode,  in atmel_mpddr_op()  argument
20 	writel(mode, &mpddr->mr);  in atmel_mpddr_op()
27 	u16 version = readl(&mpddr->version) & 0xffff;  in ddr2_decodtype_is_seq()
46 	ba_off = (mpddr_value->cr & ATMEL_MPDDRC_CR_NC_MASK) + 9;  in ddr2_init()
47 	if (ddr2_decodtype_is_seq(base, mpddr_value->cr))  in ddr2_init()
48 		ba_off += ((mpddr_value->cr & ATMEL_MPDDRC_CR_NR_MASK) >> 2) + 11;  in ddr2_init()
50 	ba_off += (mpddr_value->md & ATMEL_MPDDRC_MD_DBW_MASK) ? 1 : 2;  in ddr2_init()
53 	writel(mpddr_value->md, &mpddr->md);  in ddr2_init()
56 	writel(mpddr_value->cr, &mpddr->cr);  in ddr2_init()
59 	writel(mpddr_value->tpr0, &mpddr->tpr0);  in ddr2_init()
60 	writel(mpddr_value->tpr1, &mpddr->tpr1);  in ddr2_init()
61 	writel(mpddr_value->tpr2, &mpddr->tpr2);  in ddr2_init()
75 	/* Issue an extended mode register set(EMRS2) to choose operation */  in ddr2_init()
79 	/* Issue an extended mode register set(EMRS3) to set EMSR to 0 */  in ddr2_init()
84 	 * Issue an extended mode register set(EMRS1) to enable DLL and  in ddr2_init()
90 	/* Enable DLL reset */  in ddr2_init()
91 	cr = readl(&mpddr->cr);  in ddr2_init()
92 	writel(cr | ATMEL_MPDDRC_CR_DLL_RESET_ENABLED, &mpddr->cr);  in ddr2_init()
94 	/* A mode register set(MRS) cycle is issued to reset DLL */  in ddr2_init()
100 	/* Two auto-refresh (CBR) cycles are provided */  in ddr2_init()
104 	/* Disable DLL reset */  in ddr2_init()
105 	cr = readl(&mpddr->cr);  in ddr2_init()
106 	writel(cr & (~ATMEL_MPDDRC_CR_DLL_RESET_ENABLED), &mpddr->cr);  in ddr2_init()
108 	/* A mode register set (MRS) cycle is issued to disable DLL reset */  in ddr2_init()
112 	cr = readl(&mpddr->cr);  in ddr2_init()
113 	writel(cr | ATMEL_MPDDRC_CR_OCD_DEFAULT, &mpddr->cr);  in ddr2_init()
116 	 * An extended mode register set (EMRS1) cycle is issued  in ddr2_init()
122 	 /* OCD calibration mode exit */  in ddr2_init()
123 	cr = readl(&mpddr->cr);  in ddr2_init()
124 	writel(cr & (~ATMEL_MPDDRC_CR_OCD_DEFAULT), &mpddr->cr);  in ddr2_init()
127 	 * An extended mode register set (EMRS1) cycle is issued  in ddr2_init()
133 	/* A nornal mode command is provided */  in ddr2_init()
136 	/* Perform a write access to any DDR2-SDRAM address */  in ddr2_init()
140 	writel(mpddr_value->rtr, &mpddr->rtr);  in ddr2_init()
153 	ba_off = (mpddr_value->cr & ATMEL_MPDDRC_CR_NC_MASK) + 9;  in ddr3_init()
154 	if (ddr2_decodtype_is_seq(base, mpddr_value->cr))  in ddr3_init()
155 		ba_off += ((mpddr_value->cr &  in ddr3_init()
158 	ba_off += (mpddr_value->md & ATMEL_MPDDRC_MD_DBW_MASK) ? 1 : 2;  in ddr3_init()
161 	writel(mpddr_value->md, &mpddr->md);  in ddr3_init()
164 	 * Program features of the DDR3-SDRAM device and timing parameters  in ddr3_init()
166 	writel(mpddr_value->cr, &mpddr->cr);  in ddr3_init()
168 	writel(mpddr_value->tpr0, &mpddr->tpr0);  in ddr3_init()
169 	writel(mpddr_value->tpr1, &mpddr->tpr1);  in ddr3_init()
170 	writel(mpddr_value->tpr2, &mpddr->tpr2);  in ddr3_init()
172 	/* A NOP command is issued to the DDR3-SRAM */  in ddr3_init()
178 	/* A NOP command is issued to the DDR3-SDRAM */  in ddr3_init()
182 	 * An Extended Mode Register Set (EMRS2) cycle is issued to choose  in ddr3_init()
188 	 * Step 7: An Extended Mode Register Set (EMRS3) cycle is issued to set  in ddr3_init()
189 	 * the Extended Mode Register to 0.  in ddr3_init()
194 	 * An Extended Mode Register Set (EMRS1) cycle is issued to disable and  in ddr3_init()
201 	 * Write a one to the DLL bit (enable DLL reset) in the MPDDRC  in ddr3_init()
205 	/* A Mode Register Set (MRS) cycle is issued to reset DLL. */  in ddr3_init()
216 	/* A Normal Mode command is provided. */  in ddr3_init()
219 	/* Perform a write access to any DDR3-SDRAM address. */  in ddr3_init()
226 	writel(mpddr_value->rtr, &mpddr->rtr);  in ddr3_init()