Lines Matching refs:printf
46 printf("UnKnow-SOC: %llx\n", rev_id); in aspeed_print_soc_id()
48 printf("SOC: %4s \n",soc_map_table[i].name); in aspeed_print_soc_id()
101 printf("Secure Boot: "); in aspeed_print_security_info()
106 printf("Mode_2, "); in aspeed_print_security_info()
109 printf("AES_"); in aspeed_print_security_info()
113 printf("RSA1024_"); in aspeed_print_security_info()
116 printf("RSA2048_"); in aspeed_print_security_info()
119 printf("RSA3072_"); in aspeed_print_security_info()
122 printf("RSA4096_"); in aspeed_print_security_info()
127 printf("SHA224\n"); in aspeed_print_security_info()
130 printf("SHA256\n"); in aspeed_print_security_info()
133 printf("SHA384\n"); in aspeed_print_security_info()
136 printf("SHA512\n"); in aspeed_print_security_info()
140 printf("Mode_GCM\n"); in aspeed_print_security_info()
195 printf("RST: WDT%d ", x); \
197 printf("SOC "); \
201 printf("FULL "); \
205 printf("ARM "); \
209 printf("SW "); \
212 printf("\n"); \
222 printf("RST: Power On \n"); in aspeed_print_sysrst_info()
235 printf("RST: SYS_CM3_EXT_RESET \n"); in aspeed_print_sysrst_info()
240 printf("PCI RST: "); in aspeed_print_sysrst_info()
242 printf("#1 "); in aspeed_print_sysrst_info()
247 printf("#2 "); in aspeed_print_sysrst_info()
250 printf("\n"); in aspeed_print_sysrst_info()
254 printf("RST: DRAM_ECC_RESET \n"); in aspeed_print_sysrst_info()
259 printf("RST: SYS_FLASH_ABR_RESET \n"); in aspeed_print_sysrst_info()
263 printf("RST: External \n"); in aspeed_print_sysrst_info()
274 printf("[init by SOC]\n"); in aspeed_print_dram_initializer()
276 printf("[init by VBIOS]\n"); in aspeed_print_dram_initializer()
285 printf("eMMC 2nd Boot (ABR): Enable"); in aspeed_print_2nd_wdt_mode()
286 printf(", boot partition: %s", \ in aspeed_print_2nd_wdt_mode()
288 printf("\n"); in aspeed_print_2nd_wdt_mode()
290 printf("FMC 2nd Boot (ABR): Enable"); in aspeed_print_2nd_wdt_mode()
292 printf(", Single flash"); in aspeed_print_2nd_wdt_mode()
294 printf(", Dual flashes"); in aspeed_print_2nd_wdt_mode()
296 printf(", Source: %s", \ in aspeed_print_2nd_wdt_mode()
300 printf(", bspi_size: %ld MB", \ in aspeed_print_2nd_wdt_mode()
303 printf("\n"); in aspeed_print_2nd_wdt_mode()
312 printf("FMC aux control: Enable"); in aspeed_print_fmc_aux_ctrl()
315 printf(", Force Alt boot"); in aspeed_print_fmc_aux_ctrl()
319 printf(", BSPI_WP: Enable"); in aspeed_print_fmc_aux_ctrl()
323 printf(", FMC HW CRTM: Enable, size: %ld KB", \ in aspeed_print_fmc_aux_ctrl()
327 printf("\n"); in aspeed_print_fmc_aux_ctrl()
334 printf("SPI1 ABR: Enable"); in aspeed_print_spi1_abr_mode()
336 printf(", Single flash"); in aspeed_print_spi1_abr_mode()
338 printf(", Dual flashes"); in aspeed_print_spi1_abr_mode()
340 printf(", Source : %s", \ in aspeed_print_spi1_abr_mode()
344 printf(", hspi_size : %ld MB", \ in aspeed_print_spi1_abr_mode()
347 printf("\n"); in aspeed_print_spi1_abr_mode()
351 printf("SPI1 select pin: Enable"); in aspeed_print_spi1_abr_mode()
354 printf(", Force Alt boot"); in aspeed_print_spi1_abr_mode()
356 printf("\n"); in aspeed_print_spi1_abr_mode()
363 printf("SPI1 aux control: Enable"); in aspeed_print_spi1_aux_ctrl()
366 printf(", Force Alt boot"); in aspeed_print_spi1_aux_ctrl()
370 printf(", HPI_WP: Enable"); in aspeed_print_spi1_aux_ctrl()
374 printf(", SPI1 HW CRTM: Enable, size: %ld KB", \ in aspeed_print_spi1_aux_ctrl()
378 printf("\n"); in aspeed_print_spi1_aux_ctrl()
385 printf("SPI: 3/4 byte mode auto detection \n"); in aspeed_print_spi_strap_mode()
406 printf("eSPI Mode: SIO:%s ", sio_disable ? "Disable" : "Enable"); in aspeed_print_espi_mode()
408 printf("LPC Mode: SIO:%s ", sio_disable ? "Disable" : "Enable"); in aspeed_print_espi_mode()
411 printf(": SuperIO-%02x\n", sio_addr); in aspeed_print_espi_mode()
413 printf("\n"); in aspeed_print_espi_mode()
419 printf("Eth: "); in aspeed_print_mac_info()
421 printf("MAC%d: %s", i, in aspeed_print_mac_info()
424 printf(", "); in aspeed_print_mac_info()
426 printf("\n"); in aspeed_print_mac_info()