Lines Matching defs:sunxi_mctl_com_reg
17 struct sunxi_mctl_com_reg { struct
18 u32 cr; /* 0x00 control register */
19 u32 cr_r1; /* 0x04 rank 1 control register (R40 only) */
20 u8 res0[0x4]; /* 0x08 */
21 u32 tmr; /* 0x0c (unused on H3) */
22 u32 mcr[16][2]; /* 0x10 */
23 u32 bwcr; /* 0x90 bandwidth control register */
24 u32 maer; /* 0x94 master enable register */
25 u32 mapr; /* 0x98 master priority register */
26 u32 mcgcr; /* 0x9c */
27 u32 cpu_bwcr; /* 0xa0 */
28 u32 gpu_bwcr; /* 0xa4 */
29 u32 ve_bwcr; /* 0xa8 */
30 u32 disp_bwcr; /* 0xac */
31 u32 other_bwcr; /* 0xb0 */
32 u32 total_bwcr; /* 0xb4 */
33 u8 res1[0x8]; /* 0xb8 */
34 u32 swonr; /* 0xc0 */
35 u32 swoffr; /* 0xc4 */
36 u8 res2[0x8]; /* 0xc8 */
37 u32 cccr; /* 0xd0 */
38 u8 res3[0x54]; /* 0xd4 */
39 u32 mdfs_bwlr[3]; /* 0x128 (unused on H3) */
40 u8 res4[0x6cc]; /* 0x134 */
41 u32 protect; /* 0x800 */