Lines Matching +full:dma +full:- +full:names
1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2014 - 2015, Xilinx, Inc.
17 #address-cells = <2>;
18 #size-cells = <2>;
21 #address-cells = <1>;
22 #size-cells = <0>;
25 compatible = "arm,cortex-a53", "arm,armv8";
27 enable-method = "psci";
28 operating-points-v2 = <&cpu_opp_table>;
30 cpu-idle-states = <&CPU_SLEEP_0>;
34 compatible = "arm,cortex-a53", "arm,armv8";
36 enable-method = "psci";
38 operating-points-v2 = <&cpu_opp_table>;
39 cpu-idle-states = <&CPU_SLEEP_0>;
43 compatible = "arm,cortex-a53", "arm,armv8";
45 enable-method = "psci";
47 operating-points-v2 = <&cpu_opp_table>;
48 cpu-idle-states = <&CPU_SLEEP_0>;
52 compatible = "arm,cortex-a53", "arm,armv8";
54 enable-method = "psci";
56 operating-points-v2 = <&cpu_opp_table>;
57 cpu-idle-states = <&CPU_SLEEP_0>;
60 idle-states {
61 entry-method = "psci";
63 CPU_SLEEP_0: cpu-sleep-0 {
64 compatible = "arm,idle-state";
65 arm,psci-suspend-param = <0x40000000>;
66 local-timer-stop;
67 entry-latency-us = <300>;
68 exit-latency-us = <600>;
69 min-residency-us = <10000>;
75 compatible = "operating-points-v2";
76 opp-shared;
78 opp-hz = /bits/ 64 <1199999988>;
79 opp-microvolt = <1000000>;
80 clock-latency-ns = <500000>;
83 opp-hz = /bits/ 64 <599999994>;
84 opp-microvolt = <1000000>;
85 clock-latency-ns = <500000>;
88 opp-hz = /bits/ 64 <399999996>;
89 opp-microvolt = <1000000>;
90 clock-latency-ns = <500000>;
93 opp-hz = /bits/ 64 <299999997>;
94 opp-microvolt = <1000000>;
95 clock-latency-ns = <500000>;
102 u-boot,dm-pre-reloc;
106 compatible = "arm,armv8-pmuv3";
107 interrupt-parent = <&gic>;
115 compatible = "arm,psci-0.2";
120 compatible = "xlnx,zynqmp-pm";
122 interrupt-parent = <&gic>;
127 compatible = "arm,armv8-timer";
128 interrupt-parent = <&gic>;
136 compatible = "arm,cortex-a53-edac";
139 fpga_full: fpga-full {
140 compatible = "fpga-region";
141 fpga-mgr = <&pcap>;
142 #address-cells = <2>;
143 #size-cells = <2>;
147 compatible = "xlnx,zynqmp-nvmem-fw";
148 #address-cells = <1>;
149 #size-cells = <1>;
157 compatible = "xlnx,zynqmp-pcap-fpga";
160 rst: reset-controller {
161 compatible = "xlnx,zynqmp-reset";
162 #reset-cells = <1>;
166 compatible = "xlnx,dp-snd-card";
168 xlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>;
169 xlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>;
173 compatible = "xlnx,dp-snd-codec";
175 clock-names = "aud_clk";
179 compatible = "xlnx,dp-snd-pcm";
182 dma-names = "tx";
186 compatible = "xlnx,dp-snd-pcm";
189 dma-names = "tx";
195 xlnx,encoder-slave = <&xlnx_dp>;
196 xlnx,connector-type = "DisplayPort";
197 xlnx,dp-sub = <&xlnx_dp_sub>;
199 xlnx,pixel-format = "rgb565";
202 dma-names = "dma0";
208 dma-names = "dma0", "dma1", "dma2";
214 compatible = "simple-bus";
215 #address-cells = <2>;
216 #size-cells = <1>;
219 gic: interrupt-controller@f9010000 {
220 compatible = "arm,gic-400", "arm,cortex-a15-gic";
221 #interrupt-cells = <3>;
226 interrupt-controller;
227 interrupt-parent = <&gic>;
233 compatible = "simple-bus";
234 u-boot,dm-pre-reloc;
235 #address-cells = <2>;
236 #size-cells = <2>;
240 compatible = "xlnx,zynq-can-1.0";
242 clock-names = "can_clk", "pclk";
245 interrupt-parent = <&gic>;
246 tx-fifo-depth = <0x40>;
247 rx-fifo-depth = <0x40>;
251 compatible = "xlnx,zynq-can-1.0";
253 clock-names = "can_clk", "pclk";
256 interrupt-parent = <&gic>;
257 tx-fifo-depth = <0x40>;
258 rx-fifo-depth = <0x40>;
262 compatible = "arm,cci-400";
265 #address-cells = <1>;
266 #size-cells = <1>;
269 compatible = "arm,cci-400-pmu,r1";
271 interrupt-parent = <&gic>;
281 fpd_dma_chan1: dma@fd500000 {
283 compatible = "xlnx,zynqmp-dma-1.0";
285 interrupt-parent = <&gic>;
287 clock-names = "clk_main", "clk_apb";
288 xlnx,bus-width = <128>;
289 #stream-id-cells = <1>;
293 fpd_dma_chan2: dma@fd510000 {
295 compatible = "xlnx,zynqmp-dma-1.0";
297 interrupt-parent = <&gic>;
299 clock-names = "clk_main", "clk_apb";
300 xlnx,bus-width = <128>;
301 #stream-id-cells = <1>;
305 fpd_dma_chan3: dma@fd520000 {
307 compatible = "xlnx,zynqmp-dma-1.0";
309 interrupt-parent = <&gic>;
311 clock-names = "clk_main", "clk_apb";
312 xlnx,bus-width = <128>;
313 #stream-id-cells = <1>;
317 fpd_dma_chan4: dma@fd530000 {
319 compatible = "xlnx,zynqmp-dma-1.0";
321 interrupt-parent = <&gic>;
323 clock-names = "clk_main", "clk_apb";
324 xlnx,bus-width = <128>;
325 #stream-id-cells = <1>;
329 fpd_dma_chan5: dma@fd540000 {
331 compatible = "xlnx,zynqmp-dma-1.0";
333 interrupt-parent = <&gic>;
335 clock-names = "clk_main", "clk_apb";
336 xlnx,bus-width = <128>;
337 #stream-id-cells = <1>;
341 fpd_dma_chan6: dma@fd550000 {
343 compatible = "xlnx,zynqmp-dma-1.0";
345 interrupt-parent = <&gic>;
347 clock-names = "clk_main", "clk_apb";
348 xlnx,bus-width = <128>;
349 #stream-id-cells = <1>;
353 fpd_dma_chan7: dma@fd560000 {
355 compatible = "xlnx,zynqmp-dma-1.0";
357 interrupt-parent = <&gic>;
359 clock-names = "clk_main", "clk_apb";
360 xlnx,bus-width = <128>;
361 #stream-id-cells = <1>;
365 fpd_dma_chan8: dma@fd570000 {
367 compatible = "xlnx,zynqmp-dma-1.0";
369 interrupt-parent = <&gic>;
371 clock-names = "clk_main", "clk_apb";
372 xlnx,bus-width = <128>;
373 #stream-id-cells = <1>;
379 compatible = "arm,mali-400", "arm,mali-utgard";
381 interrupt-parent = <&gic>;
383 interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1";
384 clock-names = "gpu", "gpu_pp0", "gpu_pp1";
388 * These dma channels, Users should ensure that these dma
391 lpd_dma_chan1: dma@ffa80000 {
393 compatible = "xlnx,zynqmp-dma-1.0";
395 interrupt-parent = <&gic>;
397 clock-names = "clk_main", "clk_apb";
398 xlnx,bus-width = <64>;
399 #stream-id-cells = <1>;
403 lpd_dma_chan2: dma@ffa90000 {
405 compatible = "xlnx,zynqmp-dma-1.0";
407 interrupt-parent = <&gic>;
409 clock-names = "clk_main", "clk_apb";
410 xlnx,bus-width = <64>;
411 #stream-id-cells = <1>;
415 lpd_dma_chan3: dma@ffaa0000 {
417 compatible = "xlnx,zynqmp-dma-1.0";
419 interrupt-parent = <&gic>;
421 clock-names = "clk_main", "clk_apb";
422 xlnx,bus-width = <64>;
423 #stream-id-cells = <1>;
427 lpd_dma_chan4: dma@ffab0000 {
429 compatible = "xlnx,zynqmp-dma-1.0";
431 interrupt-parent = <&gic>;
433 clock-names = "clk_main", "clk_apb";
434 xlnx,bus-width = <64>;
435 #stream-id-cells = <1>;
439 lpd_dma_chan5: dma@ffac0000 {
441 compatible = "xlnx,zynqmp-dma-1.0";
443 interrupt-parent = <&gic>;
445 clock-names = "clk_main", "clk_apb";
446 xlnx,bus-width = <64>;
447 #stream-id-cells = <1>;
451 lpd_dma_chan6: dma@ffad0000 {
453 compatible = "xlnx,zynqmp-dma-1.0";
455 interrupt-parent = <&gic>;
457 clock-names = "clk_main", "clk_apb";
458 xlnx,bus-width = <64>;
459 #stream-id-cells = <1>;
463 lpd_dma_chan7: dma@ffae0000 {
465 compatible = "xlnx,zynqmp-dma-1.0";
467 interrupt-parent = <&gic>;
469 clock-names = "clk_main", "clk_apb";
470 xlnx,bus-width = <64>;
471 #stream-id-cells = <1>;
475 lpd_dma_chan8: dma@ffaf0000 {
477 compatible = "xlnx,zynqmp-dma-1.0";
479 interrupt-parent = <&gic>;
481 clock-names = "clk_main", "clk_apb";
482 xlnx,bus-width = <64>;
483 #stream-id-cells = <1>;
487 mc: memory-controller@fd070000 {
488 compatible = "xlnx,zynqmp-ddrc-2.40a";
490 interrupt-parent = <&gic>;
495 compatible = "arasan,nfc-v3p10";
498 clock-names = "clk_sys", "clk_flash";
499 interrupt-parent = <&gic>;
501 #address-cells = <2>;
502 #size-cells = <1>;
503 #stream-id-cells = <1>;
508 compatible = "cdns,zynqmp-gem";
510 interrupt-parent = <&gic>;
513 clock-names = "pclk", "hclk", "tx_clk";
514 #address-cells = <1>;
515 #size-cells = <0>;
516 #stream-id-cells = <1>;
521 compatible = "cdns,zynqmp-gem";
523 interrupt-parent = <&gic>;
526 clock-names = "pclk", "hclk", "tx_clk";
527 #address-cells = <1>;
528 #size-cells = <0>;
529 #stream-id-cells = <1>;
534 compatible = "cdns,zynqmp-gem";
536 interrupt-parent = <&gic>;
539 clock-names = "pclk", "hclk", "tx_clk";
540 #address-cells = <1>;
541 #size-cells = <0>;
542 #stream-id-cells = <1>;
547 compatible = "cdns,zynqmp-gem";
549 interrupt-parent = <&gic>;
552 clock-names = "pclk", "hclk", "tx_clk";
553 #address-cells = <1>;
554 #size-cells = <0>;
555 #stream-id-cells = <1>;
560 compatible = "xlnx,zynqmp-gpio-1.0";
562 #gpio-cells = <0x2>;
563 interrupt-parent = <&gic>;
565 interrupt-controller;
566 #interrupt-cells = <2>;
568 gpio-controller;
572 compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
574 interrupt-parent = <&gic>;
577 #address-cells = <1>;
578 #size-cells = <0>;
582 compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
584 interrupt-parent = <&gic>;
587 #address-cells = <1>;
588 #size-cells = <0>;
591 ocm: memory-controller@ff960000 {
592 compatible = "xlnx,zynqmp-ocmc-1.0";
594 interrupt-parent = <&gic>;
599 compatible = "xlnx,nwl-pcie-2.11";
601 #address-cells = <3>;
602 #size-cells = <2>;
603 #interrupt-cells = <1>;
604 msi-controller;
606 interrupt-parent = <&gic>;
612 interrupt-names = "misc", "dummy", "intx",
614 msi-parent = <&pcie>;
618 reg-names = "breg", "pcireg", "cfg";
619 …ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-pref…
621 bus-range = <0x00 0xff>;
622 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
623 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
627 pcie_intc: legacy-interrupt-controller {
628 interrupt-controller;
629 #address-cells = <0>;
630 #interrupt-cells = <1>;
635 u-boot,dm-pre-reloc;
636 compatible = "xlnx,zynqmp-qspi-1.0";
638 clock-names = "ref_clk", "pclk";
640 interrupt-parent = <&gic>;
641 num-cs = <1>;
644 #address-cells = <1>;
645 #size-cells = <0>;
646 #stream-id-cells = <1>;
651 compatible = "xlnx,zynqmp-rtc";
654 interrupt-parent = <&gic>;
656 interrupt-names = "alarm", "sec";
661 compatible = "xlnx,zynqmp-psgtr";
666 reg-names = "serdes", "siou", "lpd";
667 nvmem-cells = <&soc_revision>;
668 nvmem-cell-names = "soc_revision";
673 reset-names = "sata_rst", "usb0_crst", "usb1_crst",
678 #phy-cells = <4>;
681 #phy-cells = <4>;
684 #phy-cells = <4>;
687 #phy-cells = <4>;
692 compatible = "ceva,ahci-1v84";
695 interrupt-parent = <&gic>;
697 #stream-id-cells = <4>;
700 /* dma-coherent; */
704 u-boot,dm-pre-reloc;
705 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
707 interrupt-parent = <&gic>;
710 clock-names = "clk_xin", "clk_ahb";
712 #stream-id-cells = <1>;
714 nvmem-cells = <&soc_revision>;
715 nvmem-cell-names = "soc_revision";
719 u-boot,dm-pre-reloc;
720 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
722 interrupt-parent = <&gic>;
725 clock-names = "clk_xin", "clk_ahb";
727 #stream-id-cells = <1>;
729 nvmem-cells = <&soc_revision>;
730 nvmem-cell-names = "soc_revision";
734 compatible = "xlnx,pinctrl-zynqmp";
740 compatible = "arm,mmu-500";
742 #iommu-cells = <1>;
744 #global-interrupts = <1>;
745 interrupt-parent = <&gic>;
754 compatible = "cdns,spi-r1p6";
756 interrupt-parent = <&gic>;
759 clock-names = "ref_clk", "pclk";
760 #address-cells = <1>;
761 #size-cells = <0>;
765 compatible = "cdns,spi-r1p6";
767 interrupt-parent = <&gic>;
770 clock-names = "ref_clk", "pclk";
771 #address-cells = <1>;
772 #size-cells = <0>;
778 interrupt-parent = <&gic>;
781 timer-width = <32>;
787 interrupt-parent = <&gic>;
790 timer-width = <32>;
796 interrupt-parent = <&gic>;
799 timer-width = <32>;
805 interrupt-parent = <&gic>;
808 timer-width = <32>;
812 u-boot,dm-pre-reloc;
813 compatible = "cdns,uart-r1p12", "xlnx,xuartps";
815 interrupt-parent = <&gic>;
818 clock-names = "uart_clk", "pclk";
822 u-boot,dm-pre-reloc;
823 compatible = "cdns,uart-r1p12", "xlnx,xuartps";
825 interrupt-parent = <&gic>;
828 clock-names = "uart_clk", "pclk";
832 #address-cells = <2>;
833 #size-cells = <2>;
835 compatible = "xlnx,zynqmp-dwc3";
837 clock-names = "bus_clk", "ref_clk";
839 nvmem-cells = <&soc_revision>;
840 nvmem-cell-names = "soc_revision";
846 interrupt-parent = <&gic>;
848 #stream-id-cells = <1>;
850 snps,quirk-frame-length-adjustment = <0x20>;
852 /* dma-coherent; */
857 #address-cells = <2>;
858 #size-cells = <2>;
860 compatible = "xlnx,zynqmp-dwc3";
862 clock-names = "bus_clk", "ref_clk";
864 nvmem-cells = <&soc_revision>;
865 nvmem-cell-names = "soc_revision";
871 interrupt-parent = <&gic>;
873 #stream-id-cells = <1>;
875 snps,quirk-frame-length-adjustment = <0x20>;
877 /* dma-coherent; */
882 compatible = "cdns,wdt-r1p2";
884 interrupt-parent = <&gic>;
887 timeout-sec = <60>;
888 reset-on-timeout;
892 compatible = "xlnx,zynqmp-ams";
894 interrupt-parent = <&gic>;
896 interrupt-names = "ams-irq";
898 reg-names = "ams-base";
899 #address-cells = <2>;
900 #size-cells = <2>;
901 #io-channel-cells = <1>;
905 compatible = "xlnx,zynqmp-ams-ps";
911 compatible = "xlnx,zynqmp-ams-pl";
918 compatible = "xlnx,v-dp";
922 interrupt-parent = <&gic>;
923 clock-names = "aclk", "aud_clk";
924 xlnx,dp-version = "v1.2";
925 xlnx,max-lanes = <2>;
926 xlnx,max-link-rate = <540000>;
927 xlnx,max-bpc = <16>;
928 xlnx,enable-ycrcb;
931 xlnx,audio-chan = <2>;
932 xlnx,dp-sub = <&xlnx_dp_sub>;
933 xlnx,max-pclock-frequency = <300000>;
937 compatible = "xlnx,dp-sub";
942 reg-names = "blend", "av_buf", "aud";
943 xlnx,output-fmt = "rgb";
944 xlnx,vid-fmt = "yuyv";
945 xlnx,gfx-fmt = "rgb565";
948 xlnx_dpdma: dma@fd4c0000 {
953 interrupt-parent = <&gic>;
954 clock-names = "axi_clk";
955 dma-channels = <6>;
956 #dma-cells = <1>;
957 dma-video0channel {
960 dma-video1channel {
963 dma-video2channel {
966 dma-graphicschannel {
969 dma-audio0channel {
972 dma-audio1channel {