Lines Matching +full:dtr +full:- +full:gpios
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include <dt-bindings/gpio/gpio.h>
12 compatible = "toradex,imx6ull-colibri", "fsl,imx6ull";
15 stdout-path = &uart1;
18 reg_module_3v3: regulator-module-3v3 {
19 compatible = "regulator-fixed";
20 regulator-always-on;
21 regulator-name = "+V3.3";
22 regulator-min-microvolt = <3300000>;
23 regulator-max-microvolt = <3300000>;
26 reg_module_3v3_avdd: regulator-module-3v3-avdd {
27 compatible = "regulator-fixed";
28 regulator-always-on;
29 regulator-name = "+V3.3_AVDD_AUDIO";
30 regulator-min-microvolt = <3300000>;
31 regulator-max-microvolt = <3300000>;
34 reg_sd1_vmmc: regulator-sd1-vmmc {
35 compatible = "regulator-gpio";
37 pinctrl-names = "default";
38 pinctrl-0 = <&pinctrl_snvs_reg_sd>;
39 regulator-always-on;
40 regulator-name = "+V3.3_1.8_SD";
41 regulator-min-microvolt = <1800000>;
42 regulator-max-microvolt = <3300000>;
44 vin-supply = <®_module_3v3>;
49 num-channels = <10>;
50 vref-supply = <®_module_3v3_avdd>;
55 cs-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>;
56 pinctrl-names = "default";
57 pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
61 pinctrl-names = "default";
62 pinctrl-0 = <&pinctrl_enet2>;
63 phy-mode = "rmii";
64 phy-handle = <ðphy1>;
68 #address-cells = <1>;
69 #size-cells = <0>;
71 ethphy1: ethernet-phy@2 {
72 compatible = "ethernet-phy-ieee802.3-c22";
73 max-speed = <100>;
80 pinctrl-names = "default";
81 pinctrl-0 = <&pinctrl_gpmi_nand>;
82 nand-on-flash-bbt;
83 nand-ecc-mode = "hw";
84 nand-ecc-strength = <8>;
85 nand-ecc-step-size = <512>;
90 pinctrl-names = "default", "gpio";
91 pinctrl-0 = <&pinctrl_i2c1>;
92 pinctrl-1 = <&pinctrl_i2c1_gpio>;
93 sda-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
94 scl-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
99 pinctrl-names = "default", "gpio";
100 pinctrl-0 = <&pinctrl_i2c2>;
101 pinctrl-1 = <&pinctrl_i2c2_gpio>;
102 sda-gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
103 scl-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
107 compatible = "adi,ad7879-1";
108 pinctrl-names = "default";
109 pinctrl-0 = <&pinctrl_snvs_ad7879_int>;
111 interrupt-parent = <&gpio5>;
113 touchscreen-max-pressure = <4096>;
114 adi,resistance-plate-x = <120>;
115 adi,first-conversion-delay = /bits/ 8 <3>;
116 adi,acquisition-time = /bits/ 8 <1>;
117 adi,median-filter-size = /bits/ 8 <2>;
119 adi,conversion-interval = /bits/ 8 <255>;
124 pinctrl-names = "default";
125 pinctrl-0 = <&pinctrl_lcdif_dat
130 pinctrl-names = "default";
131 pinctrl-0 = <&pinctrl_pwm4>;
132 #pwm-cells = <3>;
136 pinctrl-names = "default";
137 pinctrl-0 = <&pinctrl_pwm5>;
138 #pwm-cells = <3>;
142 pinctrl-names = "default";
143 pinctrl-0 = <&pinctrl_pwm6>;
144 #pwm-cells = <3>;
148 pinctrl-names = "default";
149 pinctrl-0 = <&pinctrl_pwm7>;
150 #pwm-cells = <3>;
162 pinctrl-names = "default";
163 pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>;
164 fsl,uart-has-rtscts;
165 fsl,dte-mode;
170 pinctrl-names = "default";
171 pinctrl-0 = <&pinctrl_uart2>;
172 fsl,uart-has-rtscts;
173 fsl,dte-mode;
177 pinctrl-names = "default";
178 pinctrl-0 = <&pinctrl_uart5>;
179 fsl,dte-mode;
184 srp-disable;
185 hnp-disable;
186 adp-disable;
194 assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>;
195 assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
196 assigned-clock-rates = <0>, <198000000>;
200 pinctrl_gpio1: gpio1-grp {
215 pinctrl_gpio2: gpio2-grp { /* Camera */
225 pinctrl_gpio3: gpio3-grp { /* CAN2 */
232 pinctrl_gpio4: gpio4-grp {
238 pinctrl_gpio5: gpio5-grp { /* ATMEL MXT TOUCH */
244 pinctrl_gpio6: gpio6-grp { /* Wifi pins */
256 pinctrl_can_int: canint-grp {
262 pinctrl_enet2: enet2-grp {
277 pinctrl_ecspi1_cs: ecspi1-cs-grp {
283 pinctrl_ecspi1: ecspi1-grp {
291 pinctrl_flexcan2: flexcan2-grp {
298 pinctrl_gpio_bl_on: gpio-bl-on-grp {
304 pinctrl_gpmi_nand: gpmi-nand-grp {
323 pinctrl_i2c1: i2c1-grp {
330 pinctrl_i2c1_gpio: i2c1-gpio-grp {
337 pinctrl_i2c2: i2c2-grp {
344 pinctrl_i2c2_gpio: i2c2-gpio-grp {
351 pinctrl_lcdif_dat: lcdif-dat-grp {
374 pinctrl_lcdif_ctrl: lcdif-ctrl-grp {
383 pinctrl_pwm4: pwm4-grp {
389 pinctrl_pwm5: pwm5-grp {
395 pinctrl_pwm6: pwm6-grp {
401 pinctrl_pwm7: pwm7-grp {
407 pinctrl_uart1: uart1-grp {
416 pinctrl_uart1_ctrl1: uart1-ctrl1-grp { /* Additional DTR, DCD */
420 MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x1b0b1 /* DTR */
425 pinctrl_uart2: uart2-grp {
433 pinctrl_uart5: uart5-grp {
440 pinctrl_usbh_reg: gpio-usbh-reg {
446 pinctrl_usdhc1: usdhc1-grp {
457 pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
468 pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
479 pinctrl_usdhc2: usdhc2-grp {
492 pinctrl_snvs_gpio1: snvs-gpio1-grp {
502 pinctrl_snvs_gpio2: snvs-gpio2-grp { /* ATMEL MXT TOUCH */
508 pinctrl_snvs_gpio3: snvs-gpio3-grp { /* Wifi pins */
514 pinctrl_snvs_ad7879_int: snvs-ad7879-int { /* TOUCH Interrupt */
520 pinctrl_snvs_reg_sd: snvs-reg-sd-grp {
526 pinctrl_snvs_usbc_det: snvs-usbc-det-grp {
532 pinctrl_snvs_gpiokeys: snvs-gpiokeys-grp {
538 pinctrl_snvs_usdhc1_cd: snvs-usdhc1-cd-grp {
544 pinctrl_snvs_wifi_pdn: snvs-wifi-pdn-grp {