Lines Matching +full:build +full:- +full:without +full:- +full:default +full:- +full:features
5 default "arc"
8 default "arcv1" if ISA_ARCOMPACT
9 default "arcv2" if ISA_ARCV2
13 default ISA_ARCOMPACT
23 ISA for the Next Generation ARC-HS cores
29 default CPU_ARC770D if ISA_ARCOMPACT
30 default CPU_ARCHS38 if ISA_ARCV2
37 Choose this option to build an U-Boot for ARC750D CPU.
44 Choose this option to build an U-Boot for ARC770D CPU.
51 Next Generation ARC Core based on ISA-v2 ISA without MMU.
58 Next Generation ARC Core based on ISA-v2 ISA without MMU.
65 Next Generation ARC Core based on ISA-v2 ISA with MMU.
71 default ARC_MMU_V3 if CPU_ARC770D
72 default ARC_MMU_V2 if CPU_ARC750D
73 default ARC_MMU_ABSENT if CPU_ARCEM6
74 default ARC_MMU_ABSENT if CPU_ARCHS36
75 default ARC_MMU_V4 if CPU_ARCHS38
86 Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio
87 when 2 D-TLB and 1 I-TLB entries index into same 2way set.
93 Introduced with ARC700 4.10: New Features
94 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
107 default n
109 Build kernel for Big Endian Mode of ARC CPU
113 default n
115 Do not enable instruction cache in U-Boot
119 default n
121 Do not enable data cache in U-Boot
125 default n
132 default n
137 is enabled in u-boot!
143 default TARGET_AXS103