Lines Matching +full:- +full:a
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
21 #include "qemu/qemu-print.h"
23 #include "exec/exec-all.h"
24 #include "tcg/tcg-op.h"
25 #include "exec/helper-proto.h"
26 #include "exec/helper-gen.h"
31 #include "exec/helper-info.c.inc"
60 /* Target-specific values for dc->base.is_jmp. */
80 uint8_t b = translator_ldub(ctx->env, &ctx->base, ctx->base.pc_next++); in decode_load_bytes()
81 insn |= b << (32 - i * 8); in decode_load_bytes()
90 CPURXState *env = ctx->env; in li()
91 addr = ctx->base.pc_next; in li()
95 ctx->base.pc_next += 1; in li()
96 return (int8_t)translator_ldub(env, &ctx->base, addr); in li()
98 ctx->base.pc_next += 2; in li()
99 return (int16_t)translator_lduw(env, &ctx->base, addr); in li()
101 ctx->base.pc_next += 3; in li()
102 tmp = (int8_t)translator_ldub(env, &ctx->base, addr + 2); in li()
104 tmp |= translator_lduw(env, &ctx->base, addr); in li()
107 ctx->base.pc_next += 4; in li()
108 return translator_ldl(env, &ctx->base, addr); in li()
118 * 0 -> 8 in bdsp_s()
119 * 1 -> 9 in bdsp_s()
120 * 2 -> 10 in bdsp_s()
121 * 3 -> 3 in bdsp_s()
123 * 7 -> 7 in bdsp_s()
131 /* Include the auto-generated decoder. */
132 #include "decode-insns.c.inc"
142 env->pc, psw); in rx_cpu_dump_state()
145 i, env->regs[i], i + 1, env->regs[i + 1], in rx_cpu_dump_state()
146 i + 2, env->regs[i + 2], i + 3, env->regs[i + 3]); in rx_cpu_dump_state()
152 if (translator_use_goto_tb(&dc->base, dest)) { in gen_goto_tb()
155 tcg_gen_exit_tb(dc->base.tb, n); in gen_goto_tb()
160 dc->base.is_jmp = DISAS_NORETURN; in gen_goto_tb()
199 dsp = translator_ldub(ctx->env, &ctx->base, ctx->base.pc_next) << size; in rx_index_addr()
201 ctx->base.pc_next += 1; in rx_index_addr()
204 dsp = translator_lduw(ctx->env, &ctx->base, ctx->base.pc_next) << size; in rx_index_addr()
206 ctx->base.pc_next += 2; in rx_index_addr()
239 if (FIELD_EX32(ctx->tb_flags, PSW, PM)) { in is_privileged()
255 dc->cond = TCG_COND_EQ; in psw_cond()
256 dc->value = cpu_psw_z; in psw_cond()
259 dc->cond = TCG_COND_NE; in psw_cond()
260 dc->value = cpu_psw_z; in psw_cond()
263 dc->cond = TCG_COND_NE; in psw_cond()
264 dc->value = cpu_psw_c; in psw_cond()
267 dc->cond = TCG_COND_EQ; in psw_cond()
268 dc->value = cpu_psw_c; in psw_cond()
272 tcg_gen_setcondi_i32(TCG_COND_NE, dc->temp, cpu_psw_z, 0); in psw_cond()
273 tcg_gen_and_i32(dc->temp, dc->temp, cpu_psw_c); in psw_cond()
274 dc->cond = (cond == 4) ? TCG_COND_NE : TCG_COND_EQ; in psw_cond()
275 dc->value = dc->temp; in psw_cond()
278 dc->cond = TCG_COND_GE; in psw_cond()
279 dc->value = cpu_psw_s; in psw_cond()
282 dc->cond = TCG_COND_LT; in psw_cond()
283 dc->value = cpu_psw_s; in psw_cond()
287 tcg_gen_xor_i32(dc->temp, cpu_psw_o, cpu_psw_s); in psw_cond()
288 dc->cond = (cond == 8) ? TCG_COND_GE : TCG_COND_LT; in psw_cond()
289 dc->value = dc->temp; in psw_cond()
293 tcg_gen_xor_i32(dc->temp, cpu_psw_o, cpu_psw_s); in psw_cond()
294 tcg_gen_sari_i32(dc->temp, dc->temp, 31); in psw_cond()
295 tcg_gen_andc_i32(dc->temp, cpu_psw_z, dc->temp); in psw_cond()
296 dc->cond = (cond == 10) ? TCG_COND_NE : TCG_COND_EQ; in psw_cond()
297 dc->value = dc->temp; in psw_cond()
300 dc->cond = TCG_COND_LT; in psw_cond()
301 dc->value = cpu_psw_o; in psw_cond()
304 dc->cond = TCG_COND_GE; in psw_cond()
305 dc->value = cpu_psw_o; in psw_cond()
308 dc->cond = TCG_COND_ALWAYS; in psw_cond()
309 dc->value = dc->temp; in psw_cond()
312 dc->cond = TCG_COND_NEVER; in psw_cond()
313 dc->value = dc->temp; in psw_cond()
328 if (FIELD_EX32(ctx->tb_flags, PSW, U)) { in move_from_cr()
344 if (FIELD_EX32(ctx->tb_flags, PSW, U)) { in move_from_cr()
377 ctx->base.is_jmp = DISAS_UPDATE; in move_to_cr()
382 if (FIELD_EX32(ctx->tb_flags, PSW, U)) { in move_to_cr()
398 if (FIELD_EX32(ctx->tb_flags, PSW, U)) { in move_to_cr()
430 static bool trans_MOV_rm(DisasContext *ctx, arg_MOV_rm *a) in trans_MOV_rm() argument
434 tcg_gen_addi_i32(mem, cpu_regs[a->rd], a->dsp << a->sz); in trans_MOV_rm()
435 rx_gen_st(a->sz, cpu_regs[a->rs], mem); in trans_MOV_rm()
440 static bool trans_MOV_mr(DisasContext *ctx, arg_MOV_mr *a) in trans_MOV_mr() argument
444 tcg_gen_addi_i32(mem, cpu_regs[a->rs], a->dsp << a->sz); in trans_MOV_mr()
445 rx_gen_ld(a->sz, cpu_regs[a->rd], mem); in trans_MOV_mr()
452 static bool trans_MOV_ir(DisasContext *ctx, arg_MOV_ir *a) in trans_MOV_ir() argument
454 tcg_gen_movi_i32(cpu_regs[a->rd], a->imm); in trans_MOV_ir()
460 static bool trans_MOV_im(DisasContext *ctx, arg_MOV_im *a) in trans_MOV_im() argument
463 imm = tcg_constant_i32(a->imm); in trans_MOV_im()
465 tcg_gen_addi_i32(mem, cpu_regs[a->rd], a->dsp << a->sz); in trans_MOV_im()
466 rx_gen_st(a->sz, imm, mem); in trans_MOV_im()
471 static bool trans_MOV_ar(DisasContext *ctx, arg_MOV_ar *a) in trans_MOV_ar() argument
475 rx_gen_regindex(ctx, mem, a->sz, a->ri, a->rb); in trans_MOV_ar()
476 rx_gen_ld(a->sz, cpu_regs[a->rd], mem); in trans_MOV_ar()
481 static bool trans_MOV_ra(DisasContext *ctx, arg_MOV_ra *a) in trans_MOV_ra() argument
485 rx_gen_regindex(ctx, mem, a->sz, a->ri, a->rb); in trans_MOV_ra()
486 rx_gen_st(a->sz, cpu_regs[a->rs], mem); in trans_MOV_ra()
494 static bool trans_MOV_mm(DisasContext *ctx, arg_MOV_mm *a) in trans_MOV_mm() argument
498 if (a->lds == 3 && a->ldd == 3) { in trans_MOV_mm()
500 tcg_gen_ext_i32(cpu_regs[a->rd], cpu_regs[a->rs], a->sz | MO_SIGN); in trans_MOV_mm()
505 if (a->lds == 3) { in trans_MOV_mm()
507 addr = rx_index_addr(ctx, mem, a->ldd, a->sz, a->rs); in trans_MOV_mm()
508 rx_gen_st(a->sz, cpu_regs[a->rd], addr); in trans_MOV_mm()
509 } else if (a->ldd == 3) { in trans_MOV_mm()
511 addr = rx_index_addr(ctx, mem, a->lds, a->sz, a->rs); in trans_MOV_mm()
512 rx_gen_ld(a->sz, cpu_regs[a->rd], addr); in trans_MOV_mm()
516 addr = rx_index_addr(ctx, mem, a->lds, a->sz, a->rs); in trans_MOV_mm()
517 rx_gen_ld(a->sz, tmp, addr); in trans_MOV_mm()
518 addr = rx_index_addr(ctx, mem, a->ldd, a->sz, a->rd); in trans_MOV_mm()
519 rx_gen_st(a->sz, tmp, addr); in trans_MOV_mm()
525 /* mov.<bwl> rs,[-rd] */
526 static bool trans_MOV_rp(DisasContext *ctx, arg_MOV_rp *a) in trans_MOV_rp() argument
530 tcg_gen_mov_i32(val, cpu_regs[a->rs]); in trans_MOV_rp()
531 if (a->ad == 1) { in trans_MOV_rp()
532 tcg_gen_subi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); in trans_MOV_rp()
534 rx_gen_st(a->sz, val, cpu_regs[a->rd]); in trans_MOV_rp()
535 if (a->ad == 0) { in trans_MOV_rp()
536 tcg_gen_addi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); in trans_MOV_rp()
542 /* mov.<bwl> [-rd],rs */
543 static bool trans_MOV_pr(DisasContext *ctx, arg_MOV_pr *a) in trans_MOV_pr() argument
547 if (a->ad == 1) { in trans_MOV_pr()
548 tcg_gen_subi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); in trans_MOV_pr()
550 rx_gen_ld(a->sz, val, cpu_regs[a->rd]); in trans_MOV_pr()
551 if (a->ad == 0) { in trans_MOV_pr()
552 tcg_gen_addi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); in trans_MOV_pr()
554 tcg_gen_mov_i32(cpu_regs[a->rs], val); in trans_MOV_pr()
560 static bool trans_MOVU_mr(DisasContext *ctx, arg_MOVU_mr *a) in trans_MOVU_mr() argument
564 tcg_gen_addi_i32(mem, cpu_regs[a->rs], a->dsp << a->sz); in trans_MOVU_mr()
565 rx_gen_ldu(a->sz, cpu_regs[a->rd], mem); in trans_MOVU_mr()
570 static bool trans_MOVU_rr(DisasContext *ctx, arg_MOVU_rr *a) in trans_MOVU_rr() argument
572 tcg_gen_ext_i32(cpu_regs[a->rd], cpu_regs[a->rs], a->sz); in trans_MOVU_rr()
577 static bool trans_MOVU_ar(DisasContext *ctx, arg_MOVU_ar *a) in trans_MOVU_ar() argument
581 rx_gen_regindex(ctx, mem, a->sz, a->ri, a->rb); in trans_MOVU_ar()
582 rx_gen_ldu(a->sz, cpu_regs[a->rd], mem); in trans_MOVU_ar()
587 /* mov.<bw> [-rd],rs */
588 static bool trans_MOVU_pr(DisasContext *ctx, arg_MOVU_pr *a) in trans_MOVU_pr() argument
592 if (a->ad == 1) { in trans_MOVU_pr()
593 tcg_gen_subi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); in trans_MOVU_pr()
595 rx_gen_ldu(a->sz, val, cpu_regs[a->rd]); in trans_MOVU_pr()
596 if (a->ad == 0) { in trans_MOVU_pr()
597 tcg_gen_addi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); in trans_MOVU_pr()
599 tcg_gen_mov_i32(cpu_regs[a->rs], val); in trans_MOVU_pr()
605 static bool trans_POP(DisasContext *ctx, arg_POP *a) in trans_POP() argument
610 mov_a.rs = a->rd; in trans_POP()
618 static bool trans_POPC(DisasContext *ctx, arg_POPC *a) in trans_POPC() argument
623 move_to_cr(ctx, val, a->cr); in trans_POPC()
627 /* popm rd-rd2 */
628 static bool trans_POPM(DisasContext *ctx, arg_POPM *a) in trans_POPM() argument
631 if (a->rd == 0 || a->rd >= a->rd2) { in trans_POPM()
633 "Invalid register ranges r%d-r%d", a->rd, a->rd2); in trans_POPM()
635 r = a->rd; in trans_POPM()
636 while (r <= a->rd2 && r < 16) { in trans_POPM()
644 static bool trans_PUSH_r(DisasContext *ctx, arg_PUSH_r *a) in trans_PUSH_r() argument
648 tcg_gen_mov_i32(val, cpu_regs[a->rs]); in trans_PUSH_r()
650 rx_gen_st(a->sz, val, cpu_sp); in trans_PUSH_r()
655 static bool trans_PUSH_m(DisasContext *ctx, arg_PUSH_m *a) in trans_PUSH_m() argument
660 addr = rx_index_addr(ctx, mem, a->ld, a->sz, a->rs); in trans_PUSH_m()
661 rx_gen_ld(a->sz, val, addr); in trans_PUSH_m()
663 rx_gen_st(a->sz, val, cpu_sp); in trans_PUSH_m()
668 static bool trans_PUSHC(DisasContext *ctx, arg_PUSHC *a) in trans_PUSHC() argument
672 move_from_cr(ctx, val, a->cr, ctx->pc); in trans_PUSHC()
677 /* pushm rs-rs2 */
678 static bool trans_PUSHM(DisasContext *ctx, arg_PUSHM *a) in trans_PUSHM() argument
682 if (a->rs == 0 || a->rs >= a->rs2) { in trans_PUSHM()
684 "Invalid register ranges r%d-r%d", a->rs, a->rs2); in trans_PUSHM()
686 r = a->rs2; in trans_PUSHM()
687 while (r >= a->rs && r >= 0) { in trans_PUSHM()
688 push(cpu_regs[r--]); in trans_PUSHM()
694 static bool trans_XCHG_rr(DisasContext *ctx, arg_XCHG_rr *a) in trans_XCHG_rr() argument
698 tcg_gen_mov_i32(tmp, cpu_regs[a->rs]); in trans_XCHG_rr()
699 tcg_gen_mov_i32(cpu_regs[a->rs], cpu_regs[a->rd]); in trans_XCHG_rr()
700 tcg_gen_mov_i32(cpu_regs[a->rd], tmp); in trans_XCHG_rr()
705 static bool trans_XCHG_mr(DisasContext *ctx, arg_XCHG_mr *a) in trans_XCHG_mr() argument
709 switch (a->mi) { in trans_XCHG_mr()
713 addr = rx_index_addr(ctx, mem, a->ld, a->mi, a->rs); in trans_XCHG_mr()
717 addr = rx_index_addr(ctx, mem, a->ld, 4 - a->mi, a->rs); in trans_XCHG_mr()
722 tcg_gen_atomic_xchg_i32(cpu_regs[a->rd], addr, cpu_regs[a->rd], in trans_XCHG_mr()
723 0, mi_to_mop(a->mi)); in trans_XCHG_mr()
738 static bool trans_STZ(DisasContext *ctx, arg_STZ *a) in trans_STZ() argument
740 stcond(TCG_COND_EQ, a->rd, a->imm); in trans_STZ()
745 static bool trans_STNZ(DisasContext *ctx, arg_STNZ *a) in trans_STNZ() argument
747 stcond(TCG_COND_NE, a->rd, a->imm); in trans_STNZ()
753 static bool trans_SCCnd(DisasContext *ctx, arg_SCCnd *a) in trans_SCCnd() argument
758 psw_cond(&dc, a->cd); in trans_SCCnd()
759 if (a->ld < 3) { in trans_SCCnd()
763 addr = rx_index_addr(ctx, mem, a->sz, a->ld, a->rd); in trans_SCCnd()
764 rx_gen_st(a->sz, val, addr); in trans_SCCnd()
766 tcg_gen_setcondi_i32(dc.cond, cpu_regs[a->rd], dc.value, 0); in trans_SCCnd()
772 static bool trans_RTSD_i(DisasContext *ctx, arg_RTSD_i *a) in trans_RTSD_i() argument
774 tcg_gen_addi_i32(cpu_sp, cpu_sp, a->imm << 2); in trans_RTSD_i()
776 ctx->base.is_jmp = DISAS_JUMP; in trans_RTSD_i()
780 /* rtsd #imm, rd-rd2 */
781 static bool trans_RTSD_irr(DisasContext *ctx, arg_RTSD_irr *a) in trans_RTSD_irr() argument
786 if (a->rd2 >= a->rd) { in trans_RTSD_irr()
787 adj = a->imm - (a->rd2 - a->rd + 1); in trans_RTSD_irr()
789 adj = a->imm - (15 - a->rd + 1); in trans_RTSD_irr()
793 dst = a->rd; in trans_RTSD_irr()
794 while (dst <= a->rd2 && dst < 16) { in trans_RTSD_irr()
798 ctx->base.is_jmp = DISAS_JUMP; in trans_RTSD_irr()
839 static bool trans_AND_ir(DisasContext *ctx, arg_AND_ir *a) in trans_AND_ir() argument
841 rx_gen_op_irr(rx_and, a->rd, a->rd, a->imm); in trans_AND_ir()
847 static bool trans_AND_mr(DisasContext *ctx, arg_AND_mr *a) in trans_AND_mr() argument
849 rx_gen_op_mr(rx_and, ctx, a->rd, a->rs, a->ld, a->mi); in trans_AND_mr()
854 static bool trans_AND_rrr(DisasContext *ctx, arg_AND_rrr *a) in trans_AND_rrr() argument
856 rx_gen_op_rrr(rx_and, a->rd, a->rs, a->rs2); in trans_AND_rrr()
869 static bool trans_OR_ir(DisasContext *ctx, arg_OR_ir *a) in trans_OR_ir() argument
871 rx_gen_op_irr(rx_or, a->rd, a->rd, a->imm); in trans_OR_ir()
877 static bool trans_OR_mr(DisasContext *ctx, arg_OR_mr *a) in trans_OR_mr() argument
879 rx_gen_op_mr(rx_or, ctx, a->rd, a->rs, a->ld, a->mi); in trans_OR_mr()
884 static bool trans_OR_rrr(DisasContext *ctx, arg_OR_rrr *a) in trans_OR_rrr() argument
886 rx_gen_op_rrr(rx_or, a->rd, a->rs, a->rs2); in trans_OR_rrr()
898 static bool trans_XOR_ir(DisasContext *ctx, arg_XOR_ir *a) in trans_XOR_ir() argument
900 rx_gen_op_irr(rx_xor, a->rd, a->rd, a->imm); in trans_XOR_ir()
906 static bool trans_XOR_mr(DisasContext *ctx, arg_XOR_mr *a) in trans_XOR_mr() argument
908 rx_gen_op_mr(rx_xor, ctx, a->rd, a->rs, a->ld, a->mi); in trans_XOR_mr()
919 static bool trans_TST_ir(DisasContext *ctx, arg_TST_ir *a) in trans_TST_ir() argument
921 rx_gen_op_irr(rx_tst, a->rd, a->rd, a->imm); in trans_TST_ir()
927 static bool trans_TST_mr(DisasContext *ctx, arg_TST_mr *a) in trans_TST_mr() argument
929 rx_gen_op_mr(rx_tst, ctx, a->rd, a->rs, a->ld, a->mi); in trans_TST_mr()
942 static bool trans_NOT_rr(DisasContext *ctx, arg_NOT_rr *a) in trans_NOT_rr() argument
944 rx_gen_op_rr(rx_not, a->rd, a->rs); in trans_NOT_rr()
960 static bool trans_NEG_rr(DisasContext *ctx, arg_NEG_rr *a) in trans_NEG_rr() argument
962 rx_gen_op_rr(rx_neg, a->rd, a->rs); in trans_NEG_rr()
980 static bool trans_ADC_ir(DisasContext *ctx, arg_ADC_ir *a) in trans_ADC_ir() argument
982 rx_gen_op_irr(rx_adc, a->rd, a->rd, a->imm); in trans_ADC_ir()
987 static bool trans_ADC_rr(DisasContext *ctx, arg_ADC_rr *a) in trans_ADC_rr() argument
989 rx_gen_op_rrr(rx_adc, a->rd, a->rd, a->rs); in trans_ADC_rr()
994 static bool trans_ADC_mr(DisasContext *ctx, arg_ADC_mr *a) in trans_ADC_mr() argument
997 if (a->mi != 2) { in trans_ADC_mr()
1000 rx_gen_op_mr(rx_adc, ctx, a->rd, a->rs, a->ld, a->mi); in trans_ADC_mr()
1018 static bool trans_ADD_irr(DisasContext *ctx, arg_ADD_irr *a) in trans_ADD_irr() argument
1020 rx_gen_op_irr(rx_add, a->rd, a->rs2, a->imm); in trans_ADD_irr()
1026 static bool trans_ADD_mr(DisasContext *ctx, arg_ADD_mr *a) in trans_ADD_mr() argument
1028 rx_gen_op_mr(rx_add, ctx, a->rd, a->rs, a->ld, a->mi); in trans_ADD_mr()
1033 static bool trans_ADD_rrr(DisasContext *ctx, arg_ADD_rrr *a) in trans_ADD_rrr() argument
1035 rx_gen_op_rrr(rx_add, a->rd, a->rs, a->rs2); in trans_ADD_rrr()
1039 /* ret = arg1 - arg2 */
1059 /* ret = arg1 - arg2 - !psw_c */
1060 /* -> ret = arg1 + ~arg2 + psw_c */
1072 static bool trans_CMP_ir(DisasContext *ctx, arg_CMP_ir *a) in trans_CMP_ir() argument
1074 rx_gen_op_irr(rx_cmp, 0, a->rs2, a->imm); in trans_CMP_ir()
1080 static bool trans_CMP_mr(DisasContext *ctx, arg_CMP_mr *a) in trans_CMP_mr() argument
1082 rx_gen_op_mr(rx_cmp, ctx, a->rd, a->rs, a->ld, a->mi); in trans_CMP_mr()
1087 static bool trans_SUB_ir(DisasContext *ctx, arg_SUB_ir *a) in trans_SUB_ir() argument
1089 rx_gen_op_irr(rx_sub, a->rd, a->rd, a->imm); in trans_SUB_ir()
1095 static bool trans_SUB_mr(DisasContext *ctx, arg_SUB_mr *a) in trans_SUB_mr() argument
1097 rx_gen_op_mr(rx_sub, ctx, a->rd, a->rs, a->ld, a->mi); in trans_SUB_mr()
1102 static bool trans_SUB_rrr(DisasContext *ctx, arg_SUB_rrr *a) in trans_SUB_rrr() argument
1104 rx_gen_op_rrr(rx_sub, a->rd, a->rs2, a->rs); in trans_SUB_rrr()
1109 static bool trans_SBB_rr(DisasContext *ctx, arg_SBB_rr *a) in trans_SBB_rr() argument
1111 rx_gen_op_rrr(rx_sbb, a->rd, a->rd, a->rs); in trans_SBB_rr()
1116 static bool trans_SBB_mr(DisasContext *ctx, arg_SBB_mr *a) in trans_SBB_mr() argument
1119 if (a->mi != 2) { in trans_SBB_mr()
1122 rx_gen_op_mr(rx_sbb, ctx, a->rd, a->rs, a->ld, a->mi); in trans_SBB_mr()
1128 static bool trans_ABS_rr(DisasContext *ctx, arg_ABS_rr *a) in trans_ABS_rr() argument
1130 rx_gen_op_rr(tcg_gen_abs_i32, a->rd, a->rs); in trans_ABS_rr()
1135 static bool trans_MAX_ir(DisasContext *ctx, arg_MAX_ir *a) in trans_MAX_ir() argument
1137 rx_gen_op_irr(tcg_gen_smax_i32, a->rd, a->rd, a->imm); in trans_MAX_ir()
1143 static bool trans_MAX_mr(DisasContext *ctx, arg_MAX_mr *a) in trans_MAX_mr() argument
1145 rx_gen_op_mr(tcg_gen_smax_i32, ctx, a->rd, a->rs, a->ld, a->mi); in trans_MAX_mr()
1150 static bool trans_MIN_ir(DisasContext *ctx, arg_MIN_ir *a) in trans_MIN_ir() argument
1152 rx_gen_op_irr(tcg_gen_smin_i32, a->rd, a->rd, a->imm); in trans_MIN_ir()
1158 static bool trans_MIN_mr(DisasContext *ctx, arg_MIN_mr *a) in trans_MIN_mr() argument
1160 rx_gen_op_mr(tcg_gen_smin_i32, ctx, a->rd, a->rs, a->ld, a->mi); in trans_MIN_mr()
1166 static bool trans_MUL_ir(DisasContext *ctx, arg_MUL_ir *a) in trans_MUL_ir() argument
1168 rx_gen_op_irr(tcg_gen_mul_i32, a->rd, a->rd, a->imm); in trans_MUL_ir()
1174 static bool trans_MUL_mr(DisasContext *ctx, arg_MUL_mr *a) in trans_MUL_mr() argument
1176 rx_gen_op_mr(tcg_gen_mul_i32, ctx, a->rd, a->rs, a->ld, a->mi); in trans_MUL_mr()
1181 static bool trans_MUL_rrr(DisasContext *ctx, arg_MUL_rrr *a) in trans_MUL_rrr() argument
1183 rx_gen_op_rrr(tcg_gen_mul_i32, a->rd, a->rs, a->rs2); in trans_MUL_rrr()
1188 static bool trans_EMUL_ir(DisasContext *ctx, arg_EMUL_ir *a) in trans_EMUL_ir() argument
1190 TCGv imm = tcg_constant_i32(a->imm); in trans_EMUL_ir()
1191 if (a->rd > 14) { in trans_EMUL_ir()
1192 qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd); in trans_EMUL_ir()
1194 tcg_gen_muls2_i32(cpu_regs[a->rd], cpu_regs[(a->rd + 1) & 15], in trans_EMUL_ir()
1195 cpu_regs[a->rd], imm); in trans_EMUL_ir()
1201 static bool trans_EMUL_mr(DisasContext *ctx, arg_EMUL_mr *a) in trans_EMUL_mr() argument
1204 if (a->rd > 14) { in trans_EMUL_mr()
1205 qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd); in trans_EMUL_mr()
1208 val = rx_load_source(ctx, mem, a->ld, a->mi, a->rs); in trans_EMUL_mr()
1209 tcg_gen_muls2_i32(cpu_regs[a->rd], cpu_regs[(a->rd + 1) & 15], in trans_EMUL_mr()
1210 cpu_regs[a->rd], val); in trans_EMUL_mr()
1215 static bool trans_EMULU_ir(DisasContext *ctx, arg_EMULU_ir *a) in trans_EMULU_ir() argument
1217 TCGv imm = tcg_constant_i32(a->imm); in trans_EMULU_ir()
1218 if (a->rd > 14) { in trans_EMULU_ir()
1219 qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd); in trans_EMULU_ir()
1221 tcg_gen_mulu2_i32(cpu_regs[a->rd], cpu_regs[(a->rd + 1) & 15], in trans_EMULU_ir()
1222 cpu_regs[a->rd], imm); in trans_EMULU_ir()
1228 static bool trans_EMULU_mr(DisasContext *ctx, arg_EMULU_mr *a) in trans_EMULU_mr() argument
1231 if (a->rd > 14) { in trans_EMULU_mr()
1232 qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd); in trans_EMULU_mr()
1235 val = rx_load_source(ctx, mem, a->ld, a->mi, a->rs); in trans_EMULU_mr()
1236 tcg_gen_mulu2_i32(cpu_regs[a->rd], cpu_regs[(a->rd + 1) & 15], in trans_EMULU_mr()
1237 cpu_regs[a->rd], val); in trans_EMULU_mr()
1252 static bool trans_DIV_ir(DisasContext *ctx, arg_DIV_ir *a) in trans_DIV_ir() argument
1254 rx_gen_op_irr(rx_div, a->rd, a->rd, a->imm); in trans_DIV_ir()
1260 static bool trans_DIV_mr(DisasContext *ctx, arg_DIV_mr *a) in trans_DIV_mr() argument
1262 rx_gen_op_mr(rx_div, ctx, a->rd, a->rs, a->ld, a->mi); in trans_DIV_mr()
1267 static bool trans_DIVU_ir(DisasContext *ctx, arg_DIVU_ir *a) in trans_DIVU_ir() argument
1269 rx_gen_op_irr(rx_divu, a->rd, a->rd, a->imm); in trans_DIVU_ir()
1275 static bool trans_DIVU_mr(DisasContext *ctx, arg_DIVU_mr *a) in trans_DIVU_mr() argument
1277 rx_gen_op_mr(rx_divu, ctx, a->rd, a->rs, a->ld, a->mi); in trans_DIVU_mr()
1284 static bool trans_SHLL_irr(DisasContext *ctx, arg_SHLL_irr *a) in trans_SHLL_irr() argument
1288 if (a->imm) { in trans_SHLL_irr()
1289 tcg_gen_sari_i32(cpu_psw_c, cpu_regs[a->rs2], 32 - a->imm); in trans_SHLL_irr()
1290 tcg_gen_shli_i32(cpu_regs[a->rd], cpu_regs[a->rs2], a->imm); in trans_SHLL_irr()
1296 tcg_gen_mov_i32(cpu_regs[a->rd], cpu_regs[a->rs2]); in trans_SHLL_irr()
1300 tcg_gen_mov_i32(cpu_psw_z, cpu_regs[a->rd]); in trans_SHLL_irr()
1301 tcg_gen_mov_i32(cpu_psw_s, cpu_regs[a->rd]); in trans_SHLL_irr()
1306 static bool trans_SHLL_rr(DisasContext *ctx, arg_SHLL_rr *a) in trans_SHLL_rr() argument
1313 /* if (cpu_regs[a->rs]) { */ in trans_SHLL_rr()
1314 tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_regs[a->rs], 0, noshift); in trans_SHLL_rr()
1317 tcg_gen_andi_i32(tmp, cpu_regs[a->rs], 31); in trans_SHLL_rr()
1319 tcg_gen_sar_i32(cpu_psw_c, cpu_regs[a->rd], count); in trans_SHLL_rr()
1320 tcg_gen_shl_i32(cpu_regs[a->rd], cpu_regs[a->rd], tmp); in trans_SHLL_rr()
1332 tcg_gen_mov_i32(cpu_psw_z, cpu_regs[a->rd]); in trans_SHLL_rr()
1333 tcg_gen_mov_i32(cpu_psw_s, cpu_regs[a->rd]); in trans_SHLL_rr()
1345 gen_sXri[alith](cpu_regs[rd], cpu_regs[rs], imm - 1); in shiftr_imm()
1391 static bool trans_SHAR_irr(DisasContext *ctx, arg_SHAR_irr *a) in trans_SHAR_irr() argument
1393 shiftr_imm(a->rd, a->rs2, a->imm, 1); in trans_SHAR_irr()
1398 static bool trans_SHAR_rr(DisasContext *ctx, arg_SHAR_rr *a) in trans_SHAR_rr() argument
1400 shiftr_reg(a->rd, a->rs, 1); in trans_SHAR_rr()
1406 static bool trans_SHLR_irr(DisasContext *ctx, arg_SHLR_irr *a) in trans_SHLR_irr() argument
1408 shiftr_imm(a->rd, a->rs2, a->imm, 0); in trans_SHLR_irr()
1413 static bool trans_SHLR_rr(DisasContext *ctx, arg_SHLR_rr *a) in trans_SHLR_rr() argument
1415 shiftr_reg(a->rd, a->rs, 0); in trans_SHLR_rr()
1420 static bool trans_ROLC(DisasContext *ctx, arg_ROLC *a) in trans_ROLC() argument
1424 tcg_gen_shri_i32(tmp, cpu_regs[a->rd], 31); in trans_ROLC()
1425 tcg_gen_shli_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1); in trans_ROLC()
1426 tcg_gen_or_i32(cpu_regs[a->rd], cpu_regs[a->rd], cpu_psw_c); in trans_ROLC()
1428 tcg_gen_mov_i32(cpu_psw_z, cpu_regs[a->rd]); in trans_ROLC()
1429 tcg_gen_mov_i32(cpu_psw_s, cpu_regs[a->rd]); in trans_ROLC()
1434 static bool trans_RORC(DisasContext *ctx, arg_RORC *a) in trans_RORC() argument
1438 tcg_gen_andi_i32(tmp, cpu_regs[a->rd], 0x00000001); in trans_RORC()
1439 tcg_gen_shri_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1); in trans_RORC()
1441 tcg_gen_or_i32(cpu_regs[a->rd], cpu_regs[a->rd], cpu_psw_c); in trans_RORC()
1443 tcg_gen_mov_i32(cpu_psw_z, cpu_regs[a->rd]); in trans_RORC()
1444 tcg_gen_mov_i32(cpu_psw_s, cpu_regs[a->rd]); in trans_RORC()
1475 static bool trans_ROTL_ir(DisasContext *ctx, arg_ROTL_ir *a) in trans_ROTL_ir() argument
1477 rx_rot(ROT_IMM, ROTL, a->rd, a->imm); in trans_ROTL_ir()
1482 static bool trans_ROTL_rr(DisasContext *ctx, arg_ROTL_rr *a) in trans_ROTL_rr() argument
1484 rx_rot(ROT_REG, ROTL, a->rd, a->rs); in trans_ROTL_rr()
1489 static bool trans_ROTR_ir(DisasContext *ctx, arg_ROTR_ir *a) in trans_ROTR_ir() argument
1491 rx_rot(ROT_IMM, ROTR, a->rd, a->imm); in trans_ROTR_ir()
1496 static bool trans_ROTR_rr(DisasContext *ctx, arg_ROTR_rr *a) in trans_ROTR_rr() argument
1498 rx_rot(ROT_REG, ROTR, a->rd, a->rs); in trans_ROTR_rr()
1503 static bool trans_REVL(DisasContext *ctx, arg_REVL *a) in trans_REVL() argument
1505 tcg_gen_bswap32_i32(cpu_regs[a->rd], cpu_regs[a->rs]); in trans_REVL()
1510 static bool trans_REVW(DisasContext *ctx, arg_REVW *a) in trans_REVW() argument
1514 tcg_gen_andi_i32(tmp, cpu_regs[a->rs], 0x00ff00ff); in trans_REVW()
1516 tcg_gen_shri_i32(cpu_regs[a->rd], cpu_regs[a->rs], 8); in trans_REVW()
1517 tcg_gen_andi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 0x00ff00ff); in trans_REVW()
1518 tcg_gen_or_i32(cpu_regs[a->rd], cpu_regs[a->rd], tmp); in trans_REVW()
1535 gen_goto_tb(ctx, 0, ctx->base.pc_next); in rx_bcnd_main()
1538 gen_goto_tb(ctx, 1, ctx->pc + dst); in rx_bcnd_main()
1543 gen_goto_tb(ctx, 0, ctx->pc + dst); in rx_bcnd_main()
1561 static bool trans_BCnd(DisasContext *ctx, arg_BCnd *a) in trans_BCnd() argument
1563 rx_bcnd_main(ctx, a->cd, a->dsp); in trans_BCnd()
1571 static bool trans_BRA(DisasContext *ctx, arg_BRA *a) in trans_BRA() argument
1573 rx_bcnd_main(ctx, 14, a->dsp); in trans_BRA()
1578 static bool trans_BRA_l(DisasContext *ctx, arg_BRA_l *a) in trans_BRA_l() argument
1580 tcg_gen_addi_i32(cpu_pc, cpu_regs[a->rd], ctx->pc); in trans_BRA_l()
1581 ctx->base.is_jmp = DISAS_JUMP; in trans_BRA_l()
1587 TCGv pc = tcg_constant_i32(ctx->base.pc_next); in rx_save_pc()
1592 static bool trans_JMP(DisasContext *ctx, arg_JMP *a) in trans_JMP() argument
1594 tcg_gen_mov_i32(cpu_pc, cpu_regs[a->rs]); in trans_JMP()
1595 ctx->base.is_jmp = DISAS_JUMP; in trans_JMP()
1600 static bool trans_JSR(DisasContext *ctx, arg_JSR *a) in trans_JSR() argument
1603 tcg_gen_mov_i32(cpu_pc, cpu_regs[a->rs]); in trans_JSR()
1604 ctx->base.is_jmp = DISAS_JUMP; in trans_JSR()
1610 static bool trans_BSR(DisasContext *ctx, arg_BSR *a) in trans_BSR() argument
1613 rx_bcnd_main(ctx, 14, a->dsp); in trans_BSR()
1618 static bool trans_BSR_l(DisasContext *ctx, arg_BSR_l *a) in trans_BSR_l() argument
1621 tcg_gen_addi_i32(cpu_pc, cpu_regs[a->rd], ctx->pc); in trans_BSR_l()
1622 ctx->base.is_jmp = DISAS_JUMP; in trans_BSR_l()
1627 static bool trans_RTS(DisasContext *ctx, arg_RTS *a) in trans_RTS() argument
1630 ctx->base.is_jmp = DISAS_JUMP; in trans_RTS()
1635 static bool trans_NOP(DisasContext *ctx, arg_NOP *a) in trans_NOP() argument
1641 static bool trans_SCMPU(DisasContext *ctx, arg_SCMPU *a) in trans_SCMPU() argument
1648 static bool trans_SMOVU(DisasContext *ctx, arg_SMOVU *a) in trans_SMOVU() argument
1655 static bool trans_SMOVF(DisasContext *ctx, arg_SMOVF *a) in trans_SMOVF() argument
1662 static bool trans_SMOVB(DisasContext *ctx, arg_SMOVB *a) in trans_SMOVB() argument
1670 TCGv size = tcg_constant_i32(a->sz); \
1675 static bool trans_SUNTIL(DisasContext *ctx, arg_SUNTIL *a) in trans_SUNTIL() argument
1682 static bool trans_SWHILE(DisasContext *ctx, arg_SWHILE *a) in trans_SWHILE() argument
1688 static bool trans_SSTR(DisasContext *ctx, arg_SSTR *a) in trans_SSTR() argument
1695 static bool trans_RMPA(DisasContext *ctx, arg_RMPA *a) in trans_RMPA() argument
1728 static bool trans_MULHI(DisasContext *ctx, arg_MULHI *a) in trans_MULHI() argument
1730 rx_mul64hi(cpu_acc, a->rs, a->rs2); in trans_MULHI()
1735 static bool trans_MULLO(DisasContext *ctx, arg_MULLO *a) in trans_MULLO() argument
1737 rx_mul64lo(cpu_acc, a->rs, a->rs2); in trans_MULLO()
1742 static bool trans_MACHI(DisasContext *ctx, arg_MACHI *a) in trans_MACHI() argument
1746 rx_mul64hi(tmp, a->rs, a->rs2); in trans_MACHI()
1752 static bool trans_MACLO(DisasContext *ctx, arg_MACLO *a) in trans_MACLO() argument
1756 rx_mul64lo(tmp, a->rs, a->rs2); in trans_MACLO()
1762 static bool trans_MVFACHI(DisasContext *ctx, arg_MVFACHI *a) in trans_MVFACHI() argument
1764 tcg_gen_extrh_i64_i32(cpu_regs[a->rd], cpu_acc); in trans_MVFACHI()
1769 static bool trans_MVFACMI(DisasContext *ctx, arg_MVFACMI *a) in trans_MVFACMI() argument
1774 tcg_gen_extrl_i64_i32(cpu_regs[a->rd], rd64); in trans_MVFACMI()
1779 static bool trans_MVTACHI(DisasContext *ctx, arg_MVTACHI *a) in trans_MVTACHI() argument
1783 tcg_gen_extu_i32_i64(rs64, cpu_regs[a->rs]); in trans_MVTACHI()
1789 static bool trans_MVTACLO(DisasContext *ctx, arg_MVTACLO *a) in trans_MVTACLO() argument
1793 tcg_gen_extu_i32_i64(rs64, cpu_regs[a->rs]); in trans_MVTACLO()
1799 static bool trans_RACW(DisasContext *ctx, arg_RACW *a) in trans_RACW() argument
1801 TCGv imm = tcg_constant_i32(a->imm + 1); in trans_RACW()
1807 static bool trans_SAT(DisasContext *ctx, arg_SAT *a) in trans_SAT() argument
1812 /* S == 1 -> 0xffffffff / S == 0 -> 0x00000000 */ in trans_SAT()
1814 /* S == 1 -> 0x7fffffff / S == 0 -> 0x80000000 */ in trans_SAT()
1816 tcg_gen_movcond_i32(TCG_COND_LT, cpu_regs[a->rd], in trans_SAT()
1817 cpu_psw_o, z, tmp, cpu_regs[a->rd]); in trans_SAT()
1822 static bool trans_SATR(DisasContext *ctx, arg_SATR *a) in trans_SATR() argument
1828 #define cat3(a, b, c) a##b##c argument
1831 cat3(arg_, name, _ir) * a) \
1834 gen_helper_##op(cpu_regs[a->rd], tcg_env, \
1835 cpu_regs[a->rd], imm); \
1839 cat3(arg_, name, _mr) * a) \
1843 val = rx_load_source(ctx, mem, a->ld, MO_32, a->rs); \
1844 gen_helper_##op(cpu_regs[a->rd], tcg_env, \
1845 cpu_regs[a->rd], val); \
1850 static bool trans_##name(DisasContext *ctx, arg_##name * a) \
1854 val = rx_load_source(ctx, mem, a->ld, MO_32, a->rs); \
1855 gen_helper_##op(cpu_regs[a->rd], tcg_env, val); \
1865 static bool trans_FCMP_ir(DisasContext *ctx, arg_FCMP_ir * a) in FOP()
1868 gen_helper_fcmp(tcg_env, cpu_regs[a->rd], imm); in FOP()
1874 static bool trans_FCMP_mr(DisasContext *ctx, arg_FCMP_mr *a) in trans_FCMP_mr() argument
1878 val = rx_load_source(ctx, mem, a->ld, MO_32, a->rs); in trans_FCMP_mr()
1879 gen_helper_fcmp(tcg_env, cpu_regs[a->rd], val); in trans_FCMP_mr()
1888 static bool trans_ITOF(DisasContext *ctx, arg_ITOF * a) in FCONVOP()
1892 val = rx_load_source(ctx, mem, a->ld, a->mi, a->rs); in FCONVOP()
1893 gen_helper_itof(cpu_regs[a->rd], tcg_env, val); in FCONVOP()
1960 cat3(arg_, name, _im) * a) \
1964 mask = tcg_constant_i32(1 << a->imm); \
1965 addr = rx_index_addr(ctx, mem, a->ld, MO_8, a->rs); \
1970 cat3(arg_, name, _ir) * a) \
1973 mask = tcg_constant_i32(1 << a->imm); \
1974 cat3(rx_, op, r)(cpu_regs[a->rd], mask); \
1978 cat3(arg_, name, _rr) * a) \
1983 tcg_gen_andi_i32(b, cpu_regs[a->rs], 31); \
1985 cat3(rx_, op, r)(cpu_regs[a->rd], mask); \
1989 cat3(arg_, name, _rm) * a) \
1994 tcg_gen_andi_i32(b, cpu_regs[a->rd], 7); \
1997 addr = rx_index_addr(ctx, mem, a->ld, MO_8, a->rs); \
2020 static bool trans_BMCnd_im(DisasContext *ctx, arg_BMCnd_im *a) in trans_BMCnd_im() argument
2025 addr = rx_index_addr(ctx, mem, a->ld, MO_8, a->rd); in trans_BMCnd_im()
2027 bmcnd_op(val, a->cd, a->imm); in trans_BMCnd_im()
2033 static bool trans_BMCnd_ir(DisasContext *ctx, arg_BMCnd_ir *a) in trans_BMCnd_ir() argument
2035 bmcnd_op(cpu_regs[a->rd], a->cd, a->imm); in trans_BMCnd_ir()
2059 tcg_gen_movi_i32(cpu_psw_s, val ? -1 : 0); in clrsetpsw()
2072 ctx->base.is_jmp = DISAS_UPDATE; in clrsetpsw()
2075 if (FIELD_EX32(ctx->tb_flags, PSW, U) != val) { in clrsetpsw()
2076 ctx->tb_flags = FIELD_DP32(ctx->tb_flags, PSW, U, val); in clrsetpsw()
2090 static bool trans_CLRPSW(DisasContext *ctx, arg_CLRPSW *a) in trans_CLRPSW() argument
2092 clrsetpsw(ctx, a->cb, 0); in trans_CLRPSW()
2097 static bool trans_SETPSW(DisasContext *ctx, arg_SETPSW *a) in trans_SETPSW() argument
2099 clrsetpsw(ctx, a->cb, 1); in trans_SETPSW()
2104 static bool trans_MVTIPL(DisasContext *ctx, arg_MVTIPL *a) in trans_MVTIPL() argument
2107 tcg_gen_movi_i32(cpu_psw_ipl, a->imm); in trans_MVTIPL()
2108 ctx->base.is_jmp = DISAS_UPDATE; in trans_MVTIPL()
2114 static bool trans_MVTC_i(DisasContext *ctx, arg_MVTC_i *a) in trans_MVTC_i() argument
2118 imm = tcg_constant_i32(a->imm); in trans_MVTC_i()
2119 move_to_cr(ctx, imm, a->cr); in trans_MVTC_i()
2124 static bool trans_MVTC_r(DisasContext *ctx, arg_MVTC_r *a) in trans_MVTC_r() argument
2126 move_to_cr(ctx, cpu_regs[a->rs], a->cr); in trans_MVTC_r()
2131 static bool trans_MVFC(DisasContext *ctx, arg_MVFC *a) in trans_MVFC() argument
2133 move_from_cr(ctx, cpu_regs[a->rd], a->cr, ctx->pc); in trans_MVFC()
2138 static bool trans_RTFI(DisasContext *ctx, arg_RTFI *a) in trans_RTFI() argument
2146 ctx->base.is_jmp = DISAS_EXIT; in trans_RTFI()
2152 static bool trans_RTE(DisasContext *ctx, arg_RTE *a) in trans_RTE() argument
2160 ctx->base.is_jmp = DISAS_EXIT; in trans_RTE()
2166 static bool trans_BRK(DisasContext *ctx, arg_BRK *a) in trans_BRK() argument
2168 tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next); in trans_BRK()
2170 ctx->base.is_jmp = DISAS_NORETURN; in trans_BRK()
2175 static bool trans_INT(DisasContext *ctx, arg_INT *a) in trans_INT() argument
2179 tcg_debug_assert(a->imm < 0x100); in trans_INT()
2180 vec = tcg_constant_i32(a->imm); in trans_INT()
2181 tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next); in trans_INT()
2183 ctx->base.is_jmp = DISAS_NORETURN; in trans_INT()
2188 static bool trans_WAIT(DisasContext *ctx, arg_WAIT *a) in trans_WAIT() argument
2191 tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next); in trans_WAIT()
2200 ctx->env = cpu_env(cs); in rx_tr_init_disas_context()
2201 ctx->tb_flags = ctx->base.tb->flags; in rx_tr_init_disas_context()
2212 tcg_gen_insn_start(ctx->base.pc_next); in rx_tr_insn_start()
2220 ctx->pc = ctx->base.pc_next; in rx_tr_translate_insn()
2231 switch (ctx->base.is_jmp) { in rx_tr_tb_stop()
2234 gen_goto_tb(ctx, 0, dcbase->pc_next); in rx_tr_tb_stop()
2240 tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next); in rx_tr_tb_stop()