riscv/insn_trans/trans_rvd.c.inc

2  * RISC-V translation routines for the RV64D Standard Extension.
4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5  * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
6  *                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
17  * You should have received a copy of the GNU General Public License along with
22     if (!ctx->cfg_ptr->ext_zdinx) { \
28     if (ctx->cfg_ptr->ext_zdinx && (get_xl(ctx) == MXL_RV32) && \
35     if (!ctx->cfg_ptr->ext_zcd) { \
42 static bool trans_fld(DisasContext *ctx, arg_fld *a)
58     } else if (ctx->cfg_ptr->ext_zama16b) {
65     addr = get_address(ctx, a->rs1, a->imm);
66     tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], addr, ctx->mem_idx, memop);
72 static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
82     } else if (ctx->cfg_ptr->ext_zama16b) {
89     addr = get_address(ctx, a->rs1, a->imm);
90     tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, memop);
94 static bool trans_c_fld(DisasContext *ctx, arg_fld *a)
97     return trans_fld(ctx, a);
100 static bool trans_c_fsd(DisasContext *ctx, arg_fsd *a)
103     return trans_fsd(ctx, a);
106 static bool trans_fmadd_d(DisasContext *ctx, arg_fmadd_d *a)
110     REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2 | a->rs3);
112     TCGv_i64 dest = dest_fpr(ctx, a->rd);
113     TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
114     TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
115     TCGv_i64 src3 = get_fpr_d(ctx, a->rs3);
117     gen_set_rm(ctx, a->rm);
119     gen_set_fpr_d(ctx, a->rd, dest);
124 static bool trans_fmsub_d(DisasContext *ctx, arg_fmsub_d *a)
128     REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2 | a->rs3);
130     TCGv_i64 dest = dest_fpr(ctx, a->rd);
131     TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
132     TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
133     TCGv_i64 src3 = get_fpr_d(ctx, a->rs3);
135     gen_set_rm(ctx, a->rm);
137     gen_set_fpr_d(ctx, a->rd, dest);
142 static bool trans_fnmsub_d(DisasContext *ctx, arg_fnmsub_d *a)
146     REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2 | a->rs3);
148     TCGv_i64 dest = dest_fpr(ctx, a->rd);
149     TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
150     TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
151     TCGv_i64 src3 = get_fpr_d(ctx, a->rs3);
153     gen_set_rm(ctx, a->rm);
155     gen_set_fpr_d(ctx, a->rd, dest);
160 static bool trans_fnmadd_d(DisasContext *ctx, arg_fnmadd_d *a)
164     REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2 | a->rs3);
166     TCGv_i64 dest = dest_fpr(ctx, a->rd);
167     TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
168     TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
169     TCGv_i64 src3 = get_fpr_d(ctx, a->rs3);
171     gen_set_rm(ctx, a->rm);
173     gen_set_fpr_d(ctx, a->rd, dest);
178 static bool trans_fadd_d(DisasContext *ctx, arg_fadd_d *a)
182     REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2);
184     TCGv_i64 dest = dest_fpr(ctx, a->rd);
185     TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
186     TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
188     gen_set_rm(ctx, a->rm);
190     gen_set_fpr_d(ctx, a->rd, dest);
195 static bool trans_fsub_d(DisasContext *ctx, arg_fsub_d *a)
199     REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2);
201     TCGv_i64 dest = dest_fpr(ctx, a->rd);
202     TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
203     TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
205     gen_set_rm(ctx, a->rm);
207     gen_set_fpr_d(ctx, a->rd, dest);
212 static bool trans_fmul_d(DisasContext *ctx, arg_fmul_d *a)
216     REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2);
218     TCGv_i64 dest = dest_fpr(ctx, a->rd);
219     TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
220     TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
222     gen_set_rm(ctx, a->rm);
224     gen_set_fpr_d(ctx, a->rd, dest);
229 static bool trans_fdiv_d(DisasContext *ctx, arg_fdiv_d *a)
233     REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2);
235     TCGv_i64 dest = dest_fpr(ctx, a->rd);
236     TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
237     TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
239     gen_set_rm(ctx, a->rm);
241     gen_set_fpr_d(ctx, a->rd, dest);
246 static bool trans_fsqrt_d(DisasContext *ctx, arg_fsqrt_d *a)
250     REQUIRE_EVEN(ctx, a->rd | a->rs1);
252     TCGv_i64 dest = dest_fpr(ctx, a->rd);
253     TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
255     gen_set_rm(ctx, a->rm);
257     gen_set_fpr_d(ctx, a->rd, dest);
262 static bool trans_fsgnj_d(DisasContext *ctx, arg_fsgnj_d *a)
266     REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2);
268     TCGv_i64 dest = dest_fpr(ctx, a->rd);
269     if (a->rs1 == a->rs2) { /* FMOV */
270         dest = get_fpr_d(ctx, a->rs1);
272         TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
273         TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
276     gen_set_fpr_d(ctx, a->rd, dest);
281 static bool trans_fsgnjn_d(DisasContext *ctx, arg_fsgnjn_d *a)
285     REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2);
287     TCGv_i64 dest = dest_fpr(ctx, a->rd);
288     TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
290     if (a->rs1 == a->rs2) { /* FNEG */
293         TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
298     gen_set_fpr_d(ctx, a->rd, dest);
303 static bool trans_fsgnjx_d(DisasContext *ctx, arg_fsgnjx_d *a)
307     REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2);
309     TCGv_i64 dest = dest_fpr(ctx, a->rd);
310     TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
312     if (a->rs1 == a->rs2) { /* FABS */
315         TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
320     gen_set_fpr_d(ctx, a->rd, dest);
325 static bool trans_fmin_d(DisasContext *ctx, arg_fmin_d *a)
329     REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2);
331     TCGv_i64 dest = dest_fpr(ctx, a->rd);
332     TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
333     TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
336     gen_set_fpr_d(ctx, a->rd, dest);
341 static bool trans_fmax_d(DisasContext *ctx, arg_fmax_d *a)
345     REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2);
347     TCGv_i64 dest = dest_fpr(ctx, a->rd);
348     TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
349     TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
352     gen_set_fpr_d(ctx, a->rd, dest);
357 static bool trans_fcvt_s_d(DisasContext *ctx, arg_fcvt_s_d *a)
361     REQUIRE_EVEN(ctx, a->rs1);
363     TCGv_i64 dest = dest_fpr(ctx, a->rd);
364     TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
366     gen_set_rm(ctx, a->rm);
368     gen_set_fpr_hs(ctx, a->rd, dest);
373 static bool trans_fcvt_d_s(DisasContext *ctx, arg_fcvt_d_s *a)
377     REQUIRE_EVEN(ctx, a->rd);
379     TCGv_i64 dest = dest_fpr(ctx, a->rd);
380     TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
382     gen_set_rm(ctx, a->rm);
384     gen_set_fpr_d(ctx, a->rd, dest);
389 static bool trans_feq_d(DisasContext *ctx, arg_feq_d *a)
393     REQUIRE_EVEN(ctx, a->rs1 | a->rs2);
395     TCGv dest = dest_gpr(ctx, a->rd);
396     TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
397     TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
400     gen_set_gpr(ctx, a->rd, dest);
404 static bool trans_flt_d(DisasContext *ctx, arg_flt_d *a)
408     REQUIRE_EVEN(ctx, a->rs1 | a->rs2);
410     TCGv dest = dest_gpr(ctx, a->rd);
411     TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
412     TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
415     gen_set_gpr(ctx, a->rd, dest);
419 static bool trans_fle_d(DisasContext *ctx, arg_fle_d *a)
423     REQUIRE_EVEN(ctx, a->rs1 | a->rs2);
425     TCGv dest = dest_gpr(ctx, a->rd);
426     TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
427     TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
430     gen_set_gpr(ctx, a->rd, dest);
434 static bool trans_fclass_d(DisasContext *ctx, arg_fclass_d *a)
438     REQUIRE_EVEN(ctx, a->rs1);
440     TCGv dest = dest_gpr(ctx, a->rd);
441     TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
444     gen_set_gpr(ctx, a->rd, dest);
448 static bool trans_fcvt_w_d(DisasContext *ctx, arg_fcvt_w_d *a)
452     REQUIRE_EVEN(ctx, a->rs1);
454     TCGv dest = dest_gpr(ctx, a->rd);
455     TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
457     gen_set_rm(ctx, a->rm);
459     gen_set_gpr(ctx, a->rd, dest);
463 static bool trans_fcvt_wu_d(DisasContext *ctx, arg_fcvt_wu_d *a)
467     REQUIRE_EVEN(ctx, a->rs1);
469     TCGv dest = dest_gpr(ctx, a->rd);
470     TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
472     gen_set_rm(ctx, a->rm);
474     gen_set_gpr(ctx, a->rd, dest);
478 static bool trans_fcvt_d_w(DisasContext *ctx, arg_fcvt_d_w *a)
482     REQUIRE_EVEN(ctx, a->rd);
484     TCGv_i64 dest = dest_fpr(ctx, a->rd);
485     TCGv src = get_gpr(ctx, a->rs1, EXT_SIGN);
487     gen_set_rm(ctx, a->rm);
489     gen_set_fpr_d(ctx, a->rd, dest);
495 static bool trans_fcvt_d_wu(DisasContext *ctx, arg_fcvt_d_wu *a)
499     REQUIRE_EVEN(ctx, a->rd);
501     TCGv_i64 dest = dest_fpr(ctx, a->rd);
502     TCGv src = get_gpr(ctx, a->rs1, EXT_ZERO);
504     gen_set_rm(ctx, a->rm);
506     gen_set_fpr_d(ctx, a->rd, dest);
512 static bool trans_fcvt_l_d(DisasContext *ctx, arg_fcvt_l_d *a)
517     REQUIRE_EVEN(ctx, a->rs1);
519     TCGv dest = dest_gpr(ctx, a->rd);
520     TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
522     gen_set_rm(ctx, a->rm);
524     gen_set_gpr(ctx, a->rd, dest);
528 static bool trans_fcvt_lu_d(DisasContext *ctx, arg_fcvt_lu_d *a)
533     REQUIRE_EVEN(ctx, a->rs1);
535     TCGv dest = dest_gpr(ctx, a->rd);
536     TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
538     gen_set_rm(ctx, a->rm);
540     gen_set_gpr(ctx, a->rd, dest);
544 static bool trans_fmv_x_d(DisasContext *ctx, arg_fmv_x_d *a)
551     gen_set_gpr(ctx, a->rd, cpu_fpr[a->rs1]);
558 static bool trans_fcvt_d_l(DisasContext *ctx, arg_fcvt_d_l *a)
563     REQUIRE_EVEN(ctx, a->rd);
565     TCGv_i64 dest = dest_fpr(ctx, a->rd);
566     TCGv src = get_gpr(ctx, a->rs1, EXT_SIGN);
568     gen_set_rm(ctx, a->rm);
570     gen_set_fpr_d(ctx, a->rd, dest);
576 static bool trans_fcvt_d_lu(DisasContext *ctx, arg_fcvt_d_lu *a)
581     REQUIRE_EVEN(ctx, a->rd);
583     TCGv_i64 dest = dest_fpr(ctx, a->rd);
584     TCGv src = get_gpr(ctx, a->rs1, EXT_ZERO);
586     gen_set_rm(ctx, a->rm);
588     gen_set_fpr_d(ctx, a->rd, dest);
594 static bool trans_fmv_d_x(DisasContext *ctx, arg_fmv_d_x *a)
601     tcg_gen_mov_tl(cpu_fpr[a->rd], get_gpr(ctx, a->rs1, EXT_NONE));