Lines Matching +full:lock +full:- +full:pr
4 * Copyright (c) 2003-2007 Jocelyn Mayer
25 #include "tcg/tcg-op.h"
26 #include "tcg/tcg-op-gvec.h"
27 #include "qemu/host-utils.h"
29 #include "exec/helper-proto.h"
30 #include "exec/helper-gen.h"
33 #include "exec/translation-block.h"
37 #include "power8-pmu.h"
39 #include "qemu/qemu-print.h"
43 #include "exec/helper-info.c.inc"
98 cpu_reg_names_size -= 5; in ppc_translate_init()
106 cpu_reg_names_size -= (i < 10) ? 3 : 4; in ppc_translate_init()
111 cpu_reg_names_size -= (i < 10) ? 4 : 5; in ppc_translate_init()
174 bool pr, hv, dr, le_mode; member
216 return ctx->le_mode; in need_byteswap()
218 return !ctx->le_mode; in need_byteswap()
224 # define NARROW_MODE(C) (!(C)->sf_mode)
244 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { in gen_serialize()
245 /* Restart with exclusive lock. */ in gen_serialize()
247 ctx->base.is_jmp = DISAS_NORETURN; in gen_serialize()
257 if (ctx->flags & POWERPC_FLAG_SMT) { in gen_serialize_core()
267 if (ctx->flags & POWERPC_FLAG_SMT_1LPAR) { in gen_serialize_core_lpar()
288 if (ctx->need_access_type && ctx->access_type != access_type) { in gen_set_access_type()
290 ctx->access_type = access_type; in gen_set_access_type()
311 ctx->base.is_jmp = DISAS_NORETURN; in gen_exception_err_nip()
321 gen_exception_err_nip(ctx, excp, error, ctx->cia); in gen_exception_err()
332 ctx->base.is_jmp = DISAS_NORETURN; in gen_exception_nip()
341 gen_exception_nip(ctx, excp, ctx->cia); in gen_exception()
347 translator_io_start(&ctx->base); in gen_ppc_maybe_interrupt()
362 if (ctx->flags & POWERPC_FLAG_DE) { in gen_debug_exception()
364 if (ctx->singlestep_enabled & CPU_SINGLE_STEP) { in gen_debug_exception()
376 ctx->base.is_jmp = DISAS_NORETURN; in gen_debug_exception()
380 tcg_gen_movi_tl(t0, ctx->cia); in gen_debug_exception()
382 ctx->base.is_jmp = DISAS_NORETURN; in gen_debug_exception()
464 if (!(ctx->flags & POWERPC_FLAG_SMT)) { in spr_core_write_generic()
482 if (!(ctx->flags & POWERPC_FLAG_SMT)) { in spr_core_write_generic32()
499 if (ctx->flags & POWERPC_FLAG_SMT_1LPAR) { in spr_core_lpar_write_generic()
519 if (!(ctx->flags & POWERPC_FLAG_SMT_1LPAR)) { in spr_write_CTRL()
520 /* CTRL behaves as 1-thread in LPAR-per-thread mode */ in spr_write_CTRL()
539 ctx->base.is_jmp = DISAS_EXIT_UPDATE; in spr_write_CTRL()
624 translator_io_start(&ctx->base); in spr_write_ciabr()
631 translator_io_start(&ctx->base); in spr_write_dawr0()
637 translator_io_start(&ctx->base); in spr_write_dawrx0()
643 translator_io_start(&ctx->base); in spr_write_dawr1()
649 translator_io_start(&ctx->base); in spr_write_dawrx1()
683 /* SPR common to all non-embedded PowerPC */
688 translator_io_start(&ctx->base); in spr_read_decr()
694 translator_io_start(&ctx->base); in spr_write_decr()
699 /* SPR common to all non-embedded PowerPC, except 601 */
703 translator_io_start(&ctx->base); in spr_read_tbl()
709 translator_io_start(&ctx->base); in spr_read_tbu()
730 translator_io_start(&ctx->base); in spr_write_tbl()
740 translator_io_start(&ctx->base); in spr_write_tbu()
757 translator_io_start(&ctx->base); in spr_read_purr()
766 translator_io_start(&ctx->base); in spr_write_purr()
773 translator_io_start(&ctx->base); in spr_read_hdecr()
782 translator_io_start(&ctx->base); in spr_write_hdecr()
788 translator_io_start(&ctx->base); in spr_read_vtb()
797 translator_io_start(&ctx->base); in spr_write_vtb()
806 translator_io_start(&ctx->base); in spr_write_tbu40()
820 IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); in spr_read_ibat()
827 IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4])); in spr_read_ibat_h()
832 TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0U) / 2); in spr_write_ibatu()
838 TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4U) / 2) + 4); in spr_write_ibatu_h()
844 TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0L) / 2); in spr_write_ibatl()
850 TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4L) / 2) + 4); in spr_write_ibatl_h()
860 DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2])); in spr_read_dbat()
867 DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4])); in spr_read_dbat_h()
872 TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0U) / 2); in spr_write_dbatu()
878 TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4U) / 2) + 4); in spr_write_dbatu_h()
884 TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0L) / 2); in spr_write_dbatl()
890 TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4L) / 2) + 4); in spr_write_dbatl_h()
963 translator_io_start(&ctx->base); in spr_read_40x_pit()
969 translator_io_start(&ctx->base); in spr_write_40x_pit()
975 translator_io_start(&ctx->base); in spr_write_40x_dbcr0()
979 ctx->base.is_jmp = DISAS_EXIT_UPDATE; in spr_write_40x_dbcr0()
984 translator_io_start(&ctx->base); in spr_write_40x_sler()
990 translator_io_start(&ctx->base); in spr_write_40x_tcr()
996 translator_io_start(&ctx->base); in spr_write_40x_tsr()
1009 translator_io_start(&ctx->base); in spr_write_booke_tcr()
1015 translator_io_start(&ctx->base); in spr_write_booke_tsr()
1061 sprn_offs = sprn - SPR_BOOKE_IVOR0; in spr_write_excp_vector()
1063 sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32; in spr_write_excp_vector()
1065 sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38; in spr_write_excp_vector()
1090 * Note, the HV=1 PR=0 case is handled earlier by simply using in spr_write_amr()
1095 if (ctx->pr) { in spr_write_amr()
1276 gen_load_spr(spr, sprn - 1); in spr_read_prev_upper32()
1285 gen_load_spr(spr, sprn - 1); in spr_write_prev_upper32()
1287 gen_store_spr(sprn - 1, spr); in spr_write_prev_upper32()
1338 translator_io_start(&ctx->base); in spr_write_lpcr()
1344 translator_io_start(&ctx->base); in spr_read_pmsr()
1353 translator_io_start(&ctx->base); in spr_write_pmcr()
1429 * See section 9.3.1-9.3.2 of PowerISA v3.1B in spr_read_dexcr_ureg()
1436 /* The PPR32 SPR accesses the upper 32-bits of PPR */
1449 * Don't clobber the low 32-bits of the PPR. These are all reserved bits in spr_write_ppr32()
1506 if (unlikely(ctx->pr || !ctx->hv)) {\
1512 if (unlikely(ctx->pr)) { \
1518 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \
1692 tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); in gen_op_arith_compute_ov()
1732 * Caution: a non-obvious corner case of the spec is that in gen_op_arith_add()
1733 * we must produce the *entire* 64-bit addition, but in gen_op_arith_add()
1788 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); in gen_op_arith_divw()
1830 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); in gen_op_arith_divd()
1869 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); in gen_op_arith_modw()
1899 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); in gen_op_arith_modd()
1930 * Caution: a non-obvious corner case of the spec is that in gen_op_arith_subf()
1931 * we must produce the *entire* 64-bit addition, but in gen_op_arith_subf()
1961 * Since we're ignoring carry-out, we can simplify the in gen_op_arith_subf()
1962 * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. in gen_op_arith_subf()
1990 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); in gen_pause()
1993 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); in gen_pause()
2002 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; in gen_rlwimi()
2003 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; in gen_rlwimi()
2004 uint32_t sh = SH(ctx->opcode); in gen_rlwimi()
2005 uint32_t mb = MB(ctx->opcode); in gen_rlwimi()
2006 uint32_t me = ME(ctx->opcode); in gen_rlwimi()
2008 if (sh == (31 - me) && mb <= me) { in gen_rlwimi()
2009 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); in gen_rlwimi()
2045 if (unlikely(Rc(ctx->opcode) != 0)) { in gen_rlwimi()
2053 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; in gen_rlwinm()
2054 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; in gen_rlwinm()
2055 int sh = SH(ctx->opcode); in gen_rlwinm()
2056 int mb = MB(ctx->opcode); in gen_rlwinm()
2057 int me = ME(ctx->opcode); in gen_rlwinm()
2058 int len = me - mb + 1; in gen_rlwinm()
2059 int rsh = (32 - sh) & 31; in gen_rlwinm()
2061 if (sh != 0 && len > 0 && me == (31 - sh)) { in gen_rlwinm()
2098 if (unlikely(Rc(ctx->opcode) != 0)) { in gen_rlwinm()
2106 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; in gen_rlwnm()
2107 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; in gen_rlwnm()
2108 TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; in gen_rlwnm()
2109 uint32_t mb = MB(ctx->opcode); in gen_rlwnm()
2110 uint32_t me = ME(ctx->opcode); in gen_rlwnm()
2146 if (unlikely(Rc(ctx->opcode) != 0)) { in gen_rlwnm()
2185 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; in gen_rldinm()
2186 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; in gen_rldinm()
2187 int len = me - mb + 1; in gen_rldinm()
2188 int rsh = (64 - sh) & 63; in gen_rldinm()
2190 if (sh != 0 && len > 0 && me == (63 - sh)) { in gen_rldinm()
2198 if (unlikely(Rc(ctx->opcode) != 0)) { in gen_rldinm()
2203 /* rldicl - rldicl. */
2208 sh = SH(ctx->opcode) | (shn << 5); in gen_rldicl()
2209 mb = MB(ctx->opcode) | (mbn << 5); in gen_rldicl()
2214 /* rldicr - rldicr. */
2219 sh = SH(ctx->opcode) | (shn << 5); in gen_rldicr()
2220 me = MB(ctx->opcode) | (men << 5); in gen_rldicr()
2225 /* rldic - rldic. */
2230 sh = SH(ctx->opcode) | (shn << 5); in gen_rldic()
2231 mb = MB(ctx->opcode) | (mbn << 5); in gen_rldic()
2232 gen_rldinm(ctx, mb, 63 - sh, sh); in gen_rldic()
2238 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; in gen_rldnm()
2239 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; in gen_rldnm()
2240 TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; in gen_rldnm()
2248 if (unlikely(Rc(ctx->opcode) != 0)) { in gen_rldnm()
2253 /* rldcl - rldcl. */
2258 mb = MB(ctx->opcode) | (mbn << 5); in gen_rldcl()
2263 /* rldcr - rldcr. */
2268 me = MB(ctx->opcode) | (men << 5); in gen_rldcr()
2273 /* rldimi - rldimi. */
2276 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; in gen_rldimi()
2277 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; in gen_rldimi()
2278 uint32_t sh = SH(ctx->opcode) | (shn << 5); in gen_rldimi()
2279 uint32_t mb = MB(ctx->opcode) | (mbn << 5); in gen_rldimi()
2280 uint32_t me = 63 - sh; in gen_rldimi()
2283 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); in gen_rldimi()
2293 if (unlikely(Rc(ctx->opcode) != 0)) { in gen_rldimi()
2310 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); in gen_slw()
2313 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); in gen_slw()
2316 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); in gen_slw()
2318 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); in gen_slw()
2319 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); in gen_slw()
2320 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); in gen_slw()
2321 if (unlikely(Rc(ctx->opcode) != 0)) { in gen_slw()
2322 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); in gen_slw()
2329 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], tcg_env, in gen_sraw()
2330 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); in gen_sraw()
2331 if (unlikely(Rc(ctx->opcode) != 0)) { in gen_sraw()
2332 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); in gen_sraw()
2339 int sh = SH(ctx->opcode); in gen_srawi()
2340 TCGv dst = cpu_gpr[rA(ctx->opcode)]; in gen_srawi()
2341 TCGv src = cpu_gpr[rS(ctx->opcode)]; in gen_srawi()
2351 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); in gen_srawi()
2353 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); in gen_srawi()
2361 if (unlikely(Rc(ctx->opcode) != 0)) { in gen_srawi()
2374 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); in gen_srw()
2377 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); in gen_srw()
2380 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); in gen_srw()
2383 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); in gen_srw()
2384 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); in gen_srw()
2385 if (unlikely(Rc(ctx->opcode) != 0)) { in gen_srw()
2386 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); in gen_srw()
2398 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); in gen_sld()
2400 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); in gen_sld()
2402 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); in gen_sld()
2403 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); in gen_sld()
2404 if (unlikely(Rc(ctx->opcode) != 0)) { in gen_sld()
2405 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); in gen_sld()
2412 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], tcg_env, in gen_srad()
2413 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); in gen_srad()
2414 if (unlikely(Rc(ctx->opcode) != 0)) { in gen_srad()
2415 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); in gen_srad()
2421 int sh = SH(ctx->opcode) + (n << 5); in gen_sradi()
2422 TCGv dst = cpu_gpr[rA(ctx->opcode)]; in gen_sradi()
2423 TCGv src = cpu_gpr[rS(ctx->opcode)]; in gen_sradi()
2432 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); in gen_sradi()
2434 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); in gen_sradi()
2442 if (unlikely(Rc(ctx->opcode) != 0)) { in gen_sradi()
2460 int sh = SH(ctx->opcode) + (n << 5); in gen_extswsli()
2461 TCGv dst = cpu_gpr[rA(ctx->opcode)]; in gen_extswsli()
2462 TCGv src = cpu_gpr[rS(ctx->opcode)]; in gen_extswsli()
2466 if (unlikely(Rc(ctx->opcode) != 0)) { in gen_extswsli()
2488 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); in gen_srd()
2490 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); in gen_srd()
2492 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); in gen_srd()
2493 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); in gen_srd()
2494 if (unlikely(Rc(ctx->opcode) != 0)) { in gen_srd()
2495 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); in gen_srd()
2505 target_long simm = SIMM(ctx->opcode); in gen_addr_imm_index()
2508 if (rA(ctx->opcode) == 0) { in gen_addr_imm_index()
2514 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); in gen_addr_imm_index()
2520 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); in gen_addr_imm_index()
2522 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); in gen_addr_imm_index()
2529 if (rA(ctx->opcode) == 0) { in gen_addr_reg_index()
2531 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); in gen_addr_reg_index()
2533 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); in gen_addr_reg_index()
2536 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); in gen_addr_reg_index()
2545 if (rA(ctx->opcode) == 0) { in gen_addr_register()
2548 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); in gen_addr_register()
2550 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); in gen_addr_register()
2566 (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); in gen_align_no_le()
2569 /* EA <- {(ra == 0) ? 0 : GPR[ra]} + displ */
2585 /* EA <- (ra == 0) ? 0 : GPR[ra] */
2601 #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask)
2602 #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP))
2609 tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \
2626 tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \
2644 tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \
2661 tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \
2681 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2698 tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\
2725 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2742 cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \
2786 if (ctx->le_mode) { in gen_lmw()
2792 t1 = tcg_constant_i32(rD(ctx->opcode)); in gen_lmw()
2803 if (ctx->le_mode) { in gen_stmw()
2809 t1 = tcg_constant_i32(rS(ctx->opcode)); in gen_stmw()
2827 int nb = NB(ctx->opcode); in gen_lswi()
2828 int start = rD(ctx->opcode); in gen_lswi()
2829 int ra = rA(ctx->opcode); in gen_lswi()
2832 if (ctx->le_mode) { in gen_lswi()
2858 if (ctx->le_mode) { in gen_lswx()
2865 t1 = tcg_constant_i32(rD(ctx->opcode)); in gen_lswx()
2866 t2 = tcg_constant_i32(rA(ctx->opcode)); in gen_lswx()
2867 t3 = tcg_constant_i32(rB(ctx->opcode)); in gen_lswx()
2876 int nb = NB(ctx->opcode); in gen_stswi()
2878 if (ctx->le_mode) { in gen_stswi()
2889 t2 = tcg_constant_i32(rS(ctx->opcode)); in gen_stswi()
2899 if (ctx->le_mode) { in gen_stswx()
2909 t2 = tcg_constant_i32(rS(ctx->opcode)); in gen_stswx()
2919 if (!ctx->lazy_tlb_flush) { in gen_check_tlb_flush()
2934 * Global TLB flush uses async-work which must run before the in gen_check_tlb_flush()
2937 ctx->base.is_jmp = DISAS_EXIT_UPDATE; in gen_check_tlb_flush()
2951 if (!ctx->pr) { in gen_isync()
2955 ctx->base.is_jmp = DISAS_EXIT_UPDATE; in gen_isync()
2960 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; in gen_load_locked()
2965 tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, DEF_MEMOP(memop) | MO_ALIGN); in gen_load_locked()
2989 tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); in LARX()
2991 tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); in LARX()
2997 tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); in LARX()
2999 /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */ in LARX()
3000 tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, in LARX()
3001 tcg_constant_tl(1 << (memop_size(memop) * 8 - 1))); in LARX()
3006 uint32_t gpr_FC = FC(ctx->opcode); in gen_ld_atomic()
3008 int rt = rD(ctx->opcode); in gen_ld_atomic()
3020 tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); in gen_ld_atomic()
3023 tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); in gen_ld_atomic()
3026 tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); in gen_ld_atomic()
3029 tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); in gen_ld_atomic()
3032 tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); in gen_ld_atomic()
3035 tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); in gen_ld_atomic()
3038 tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); in gen_ld_atomic()
3041 tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); in gen_ld_atomic()
3044 tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); in gen_ld_atomic()
3048 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { in gen_ld_atomic()
3054 tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); in gen_ld_atomic()
3062 tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); in gen_ld_atomic()
3068 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { in gen_ld_atomic()
3075 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { in gen_ld_atomic()
3082 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { in gen_ld_atomic()
3085 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); in gen_ld_atomic()
3095 /* Restart with exclusive lock. */ in gen_ld_atomic()
3097 ctx->base.is_jmp = DISAS_NORETURN; in gen_ld_atomic()
3115 uint32_t gpr_FC = FC(ctx->opcode); in gen_st_atomic()
3120 src = cpu_gpr[rD(ctx->opcode)]; in gen_st_atomic()
3126 tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); in gen_st_atomic()
3129 tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); in gen_st_atomic()
3132 tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); in gen_st_atomic()
3135 tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); in gen_st_atomic()
3138 tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); in gen_st_atomic()
3141 tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); in gen_st_atomic()
3144 tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); in gen_st_atomic()
3147 tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); in gen_st_atomic()
3150 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { in gen_st_atomic()
3151 /* Restart with exclusive lock. */ in gen_st_atomic()
3153 ctx->base.is_jmp = DISAS_NORETURN; in gen_st_atomic()
3161 tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); in gen_st_atomic()
3163 tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); in gen_st_atomic()
3166 tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); in gen_st_atomic()
3167 tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); in gen_st_atomic()
3194 int rs = rS(ctx->opcode); in gen_conditional_store()
3208 cpu_gpr[rs], ctx->mem_idx, in gen_conditional_store()
3216 tcg_gen_movi_tl(cpu_reserve, -1); in gen_conditional_store()
3238 int rd = rD(ctx->opcode); in STCX()
3242 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || in STCX()
3243 (rd == rB(ctx->opcode)))) { in STCX()
3257 tcg_gen_qemu_ld_i128(t16, EA, ctx->mem_idx, DEF_MEMOP(MO_128 | MO_ALIGN)); in STCX()
3273 int rs = rS(ctx->opcode); in gen_stqcx_()
3298 tcg_gen_atomic_cmpxchg_i128(val, cpu_reserve, cmp, val, ctx->mem_idx, in gen_stqcx_()
3315 tcg_gen_movi_tl(cpu_reserve, -1); in gen_stqcx_()
3324 if (ctx->insns_flags & PPC_WAIT) { in gen_wait()
3325 /* v2.03-v2.07 define an older incompatible 'wait' encoding. */ in gen_wait()
3327 if (ctx->insns_flags2 & PPC2_PM_ISA206) { in gen_wait()
3328 /* v2.06 introduced the WC field. WC > 0 may be treated as no-op. */ in gen_wait()
3329 wc = WC(ctx->opcode); in gen_wait()
3334 } else if (ctx->insns_flags2 & PPC2_ISA300) { in gen_wait()
3336 wc = WC(ctx->opcode); in gen_wait()
3337 if (ctx->insns_flags2 & PPC2_ISA310) { in gen_wait()
3338 uint32_t pl = PL(ctx->opcode); in gen_wait()
3340 /* WC 1,2 may be treated as no-op. WC 3 is reserved. */ in gen_wait()
3346 /* PL 1-3 are reserved. If WC=2 then the insn is treated as noop. */ in gen_wait()
3353 /* WC 1-3 are reserved */ in gen_wait()
3373 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); in gen_wait()
3375 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); in gen_wait()
3380 * ignoring their other wake-up conditions could cause a hang. in gen_wait()
3383 * no-ops. in gen_wait()
3385 * wc=1 and wc=3 explicitly allow the instruction to be treated as a no-op. in gen_wait()
3387 * wc=2 waits for an implementation-specific condition, such could be in gen_wait()
3388 * always true, so it can be implemented as a no-op. in gen_wait()
3390 * For v3.1, wc=1,2 are architected but may be implemented as no-ops. in gen_wait()
3393 * Reservation-loss may have implementation-specific conditions, so it in gen_wait()
3394 * can be implemented as a no-op. in gen_wait()
3397 * amount is implementation-specific so it can be implemented as a in gen_wait()
3398 * no-op. in gen_wait()
3401 * an implementation-dependent event", so in any case software must in gen_wait()
3403 * true, so no-op implementations should be architecturally correct in gen_wait()
3417 translator_io_start(&ctx->base); in gen_doze()
3421 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); in gen_doze()
3433 translator_io_start(&ctx->base); in gen_nap()
3437 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); in gen_nap()
3449 translator_io_start(&ctx->base); in gen_stop()
3453 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); in gen_stop()
3465 translator_io_start(&ctx->base); in gen_sleep()
3469 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); in gen_sleep()
3481 translator_io_start(&ctx->base); in gen_rvwinkle()
3485 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); in gen_rvwinkle()
3521 if (ctx->has_cfar) { in gen_update_branch_history()
3525 if (!ctx->has_bhrb || in gen_update_branch_history()
3526 !ctx->bhrb_enable || in gen_update_branch_history()
3554 /* Also record the target address for XL-Form branches */ in gen_update_branch_history()
3577 if (!ctx->pmu_insn_cnt) { in pmu_count_insns()
3591 translator_io_start(&ctx->base); in pmu_count_insns()
3593 /* Avoid helper calls when only PMC5-6 are enabled. */ in pmu_count_insns()
3594 if (!ctx->pmc_other) { in pmu_count_insns()
3599 tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); in pmu_count_insns()
3602 if (ctx->mmcr0_pmcjce) { in pmu_count_insns()
3609 gen_helper_insns_inc(tcg_env, tcg_constant_i32(ctx->base.num_insns)); in pmu_count_insns()
3620 tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); in pmu_count_insns()
3632 if (unlikely(ctx->singlestep_enabled)) { in use_goto_tb()
3635 return translator_use_goto_tb(&ctx->base, dest); in use_goto_tb()
3640 if (unlikely(ctx->singlestep_enabled)) { in gen_lookup_and_goto_ptr()
3647 if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { in gen_lookup_and_goto_ptr()
3665 tcg_gen_exit_tb(ctx->base.tb, n); in gen_goto_tb()
3686 li = LI(ctx->opcode); in gen_b()
3687 li = (li ^ 0x02000000) - 0x02000000; in gen_b()
3688 if (likely(AA(ctx->opcode) == 0)) { in gen_b()
3689 target = ctx->cia + li; in gen_b()
3693 if (LK(ctx->opcode)) { in gen_b()
3694 gen_setlr(ctx, ctx->base.pc_next); in gen_b()
3695 gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_CALL); in gen_b()
3697 gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_OTHER); in gen_b()
3700 ctx->base.is_jmp = DISAS_NORETURN; in gen_b()
3710 uint32_t bo = BO(ctx->opcode); in gen_bcond()
3724 if (!LK(ctx->opcode)) { in gen_bcond()
3731 if (LK(ctx->opcode)) { in gen_bcond()
3732 gen_setlr(ctx, ctx->base.pc_next); in gen_bcond()
3743 * some processors, ie. 64-bit server processors compliant with in gen_bcond()
3749 * This form was hence chosen to trigger extra micro-architectural in gen_bcond()
3750 * side-effect on real HW needed for the Spectre v2 workaround. in gen_bcond()
3752 * use this form in a way it just triggers the side-effect without in gen_bcond()
3788 uint32_t bi = BI(ctx->opcode); in gen_bcond()
3802 gen_update_branch_history(ctx, ctx->cia, target, bhrb_type); in gen_bcond()
3805 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); in gen_bcond()
3806 if (likely(AA(ctx->opcode) == 0)) { in gen_bcond()
3807 gen_goto_tb(ctx, 0, ctx->cia + li); in gen_bcond()
3822 gen_goto_tb(ctx, 1, ctx->base.pc_next); in gen_bcond()
3824 ctx->base.is_jmp = DISAS_NORETURN; in gen_bcond()
3854 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3857 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3859 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3861 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3863 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3865 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3867 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3869 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3871 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
3873 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3874 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3897 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); in gen_mcrf()
3909 * This instruction doesn't exist anymore on 64-bit server in gen_rfi()
3918 translator_io_start(&ctx->base); in gen_rfi()
3919 gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_NORECORD); in gen_rfi()
3921 ctx->base.is_jmp = DISAS_EXIT; in gen_rfi()
3933 translator_io_start(&ctx->base); in gen_rfid()
3934 gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_NORECORD); in gen_rfid()
3936 ctx->base.is_jmp = DISAS_EXIT; in gen_rfid()
3948 translator_io_start(&ctx->base); in gen_rfscv()
3949 gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_NORECORD); in gen_rfscv()
3951 ctx->base.is_jmp = DISAS_EXIT; in gen_rfscv()
3963 translator_io_start(&ctx->base); in gen_hrfid()
3965 ctx->base.is_jmp = DISAS_EXIT; in gen_hrfid()
3981 * LEV is a 7-bit field, but the top 6 bits are treated as a reserved in gen_sc()
3985 lev = (ctx->opcode >> 5) & 0x1; in gen_sc()
3993 uint32_t lev = (ctx->opcode >> 5) & 0x7F; in gen_scv()
3996 gen_update_nip(ctx, ctx->cia); in gen_scv()
3999 ctx->base.is_jmp = DISAS_NORETURN; in gen_scv()
4028 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; in gen_mcrxr()
4050 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; in gen_mcrxrx()
4069 if (likely(ctx->opcode & 0x00100000)) { in gen_mfcr()
4070 crm = CRM(ctx->opcode); in gen_mfcr()
4071 if (likely(crm && ((crm & (crm - 1)) == 0))) { in gen_mfcr()
4073 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); in gen_mfcr()
4074 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], in gen_mfcr()
4075 cpu_gpr[rD(ctx->opcode)], crn * 4); in gen_mfcr()
4094 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); in gen_mfcr()
4102 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); in gen_mfmsr()
4109 uint32_t sprn = SPR(ctx->opcode); in gen_op_mfspr()
4112 read_cb = ctx->spr_cb[sprn].uea_read; in gen_op_mfspr()
4114 if (ctx->pr) { in gen_op_mfspr()
4115 read_cb = ctx->spr_cb[sprn].uea_read; in gen_op_mfspr()
4116 } else if (ctx->hv) { in gen_op_mfspr()
4117 read_cb = ctx->spr_cb[sprn].hea_read; in gen_op_mfspr()
4119 read_cb = ctx->spr_cb[sprn].oea_read; in gen_op_mfspr()
4124 (*read_cb)(ctx, rD(ctx->opcode), sprn); in gen_op_mfspr()
4135 ctx->cia); in gen_op_mfspr()
4140 /* ISA 2.07 defines these as no-ops */ in gen_op_mfspr()
4141 if ((ctx->insns_flags2 & PPC2_ISA207S) && in gen_op_mfspr()
4149 TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); in gen_op_mfspr()
4152 * The behaviour depends on MSR:PR and SPR# bit 0x10, it can in gen_op_mfspr()
4153 * generate a priv, a hv emu or a no-op in gen_op_mfspr()
4156 if (ctx->pr) { in gen_op_mfspr()
4160 if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { in gen_op_mfspr()
4183 crm = CRM(ctx->opcode); in gen_mtcrf()
4184 if (likely((ctx->opcode & 0x00100000))) { in gen_mtcrf()
4185 if (crm && ((crm & (crm - 1)) == 0)) { in gen_mtcrf()
4188 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); in gen_mtcrf()
4190 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); in gen_mtcrf()
4194 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); in gen_mtcrf()
4197 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); in gen_mtcrf()
4198 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); in gen_mtcrf()
4222 translator_io_start(&ctx->base); in gen_mtmsrd()
4224 if (ctx->opcode & 0x00010000) { in gen_mtmsrd()
4236 gen_update_nip(ctx, ctx->base.pc_next); in gen_mtmsrd()
4239 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); in gen_mtmsrd()
4246 ctx->base.is_jmp = DISAS_EXIT_UPDATE; in gen_mtmsrd()
4262 translator_io_start(&ctx->base); in gen_mtmsr()
4263 if (ctx->opcode & 0x00010000) { in gen_mtmsr()
4275 gen_update_nip(ctx, ctx->base.pc_next); in gen_mtmsr()
4278 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); in gen_mtmsr()
4285 ctx->base.is_jmp = DISAS_EXIT_UPDATE; in gen_mtmsr()
4293 uint32_t sprn = SPR(ctx->opcode); in gen_mtspr()
4296 write_cb = ctx->spr_cb[sprn].uea_write; in gen_mtspr()
4298 if (ctx->pr) { in gen_mtspr()
4299 write_cb = ctx->spr_cb[sprn].uea_write; in gen_mtspr()
4300 } else if (ctx->hv) { in gen_mtspr()
4301 write_cb = ctx->spr_cb[sprn].hea_write; in gen_mtspr()
4303 write_cb = ctx->spr_cb[sprn].oea_write; in gen_mtspr()
4308 (*write_cb)(ctx, sprn, rS(ctx->opcode)); in gen_mtspr()
4313 ctx->cia); in gen_mtspr()
4317 /* ISA 2.07 defines these as no-ops */ in gen_mtspr()
4318 if ((ctx->insns_flags2 & PPC2_ISA207S) && in gen_mtspr()
4327 TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); in gen_mtspr()
4331 * The behaviour depends on MSR:PR and SPR# bit 0x10, it can in gen_mtspr()
4332 * generate a priv, a hv emu or a no-op in gen_mtspr()
4335 if (ctx->pr) { in gen_mtspr()
4339 if (ctx->pr || sprn == 0) { in gen_mtspr()
4352 TCGv_i32 tm1 = tcg_constant_i32(-1); in gen_setb()
4353 int crf = crfS(ctx->opcode); in gen_setb()
4357 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); in gen_setb()
4431 * interpreted as no-op in gen_dcbt()
4441 * interpreted as no-op in gen_dcbtep()
4451 * interpreted as no-op in gen_dcbtst()
4461 * interpreted as no-op in gen_dcbtstep()
4481 * interpreted as no-op in gen_dcblc()
4494 if (ctx->excp_model == POWERPC_EXCP_970 && !(ctx->opcode & 0x00200000)) { in gen_dcbz()
4500 gen_helper_dcbz(tcg_env, tcgv_addr, tcg_constant_i32(ctx->mem_idx)); in gen_dcbz()
4516 if (rA(ctx->opcode) == 0) { in gen_dst()
4519 /* interpreted as no-op */ in gen_dst()
4526 if (rA(ctx->opcode) == 0) { in gen_dstst()
4529 /* interpreted as no-op */ in gen_dstst()
4537 /* interpreted as no-op */ in gen_dss()
4565 * interpreted as no-op in gen_dcba()
4583 t0 = tcg_constant_tl(SR(ctx->opcode)); in gen_mfsr()
4584 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], tcg_env, t0); in gen_mfsr()
4598 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); in gen_mfsrin()
4599 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], tcg_env, t0); in gen_mfsrin()
4612 t0 = tcg_constant_tl(SR(ctx->opcode)); in gen_mtsr()
4613 gen_helper_store_sr(tcg_env, t0, cpu_gpr[rS(ctx->opcode)]); in gen_mtsr()
4627 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); in gen_mtsrin()
4628 gen_helper_store_sr(tcg_env, t0, cpu_gpr[rD(ctx->opcode)]); in gen_mtsrin()
4644 t0 = tcg_constant_tl(SR(ctx->opcode)); in gen_mfsr_64b()
4645 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], tcg_env, t0); in gen_mfsr_64b()
4659 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); in gen_mfsrin_64b()
4660 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], tcg_env, t0); in gen_mfsrin_64b()
4673 t0 = tcg_constant_tl(SR(ctx->opcode)); in gen_mtsr_64b()
4674 gen_helper_store_sr(tcg_env, t0, cpu_gpr[rS(ctx->opcode)]); in gen_mtsr_64b()
4688 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); in gen_mtsrin_64b()
4689 gen_helper_store_sr(tcg_env, t0, cpu_gpr[rS(ctx->opcode)]); in gen_mtsrin_64b()
4717 if (ctx->gtse) { in gen_tlbsync()
4724 if (ctx->insns_flags & PPC_BOOKE) { in gen_tlbsync()
4741 tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, in gen_eciwx()
4753 tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, in gen_ecowx()
4757 /* 602 - 603 - G2 TLB management */
4766 gen_helper_6xx_tlbd(tcg_env, cpu_gpr[rB(ctx->opcode)]); in gen_tlbld_6xx()
4777 gen_helper_6xx_tlbi(tcg_env, cpu_gpr[rB(ctx->opcode)]); in gen_tlbli_6xx()
4801 gen_helper_tlbiva(tcg_env, cpu_gpr[rB(ctx->opcode)]); in gen_tlbiva()
4816 /* macchw - macchw. - macchwo - macchwo. */ in gen_405_mulladd_insn()
4817 /* macchws - macchws. - macchwso - macchwso. */ in gen_405_mulladd_insn()
4818 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ in gen_405_mulladd_insn()
4819 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ in gen_405_mulladd_insn()
4820 /* mulchw - mulchw. */ in gen_405_mulladd_insn()
4826 /* macchwu - macchwu. - macchwuo - macchwuo. */ in gen_405_mulladd_insn()
4827 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ in gen_405_mulladd_insn()
4828 /* mulchwu - mulchwu. */ in gen_405_mulladd_insn()
4834 /* machhw - machhw. - machhwo - machhwo. */ in gen_405_mulladd_insn()
4835 /* machhws - machhws. - machhwso - machhwso. */ in gen_405_mulladd_insn()
4836 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ in gen_405_mulladd_insn()
4837 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ in gen_405_mulladd_insn()
4838 /* mulhhw - mulhhw. */ in gen_405_mulladd_insn()
4845 /* machhwu - machhwu. - machhwuo - machhwuo. */ in gen_405_mulladd_insn()
4846 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ in gen_405_mulladd_insn()
4847 /* mulhhwu - mulhhwu. */ in gen_405_mulladd_insn()
4854 /* maclhw - maclhw. - maclhwo - maclhwo. */ in gen_405_mulladd_insn()
4855 /* maclhws - maclhws. - maclhwso - maclhwso. */ in gen_405_mulladd_insn()
4856 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ in gen_405_mulladd_insn()
4857 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ in gen_405_mulladd_insn()
4858 /* mullhw - mullhw. */ in gen_405_mulladd_insn()
4863 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ in gen_405_mulladd_insn()
4864 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ in gen_405_mulladd_insn()
4865 /* mullhwu - mullhwu. */ in gen_405_mulladd_insn()
4871 /* (n)multiply-and-accumulate (0x0C / 0x0E) */ in gen_405_mulladd_insn()
4874 /* nmultiply-and-accumulate (0x0E) */ in gen_405_mulladd_insn()
4877 /* multiply-and-accumulate (0x0C) */ in gen_405_mulladd_insn()
4928 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
4929 rD(ctx->opcode), Rc(ctx->opcode)); \
4932 /* macchw - macchw. */
4934 /* macchwo - macchwo. */
4936 /* macchws - macchws. */
4938 /* macchwso - macchwso. */
4940 /* macchwsu - macchwsu. */
4942 /* macchwsuo - macchwsuo. */
4944 /* macchwu - macchwu. */
4946 /* macchwuo - macchwuo. */
4948 /* machhw - machhw. */
4950 /* machhwo - machhwo. */
4952 /* machhws - machhws. */
4954 /* machhwso - machhwso. */
4956 /* machhwsu - machhwsu. */
4958 /* machhwsuo - machhwsuo. */
4960 /* machhwu - machhwu. */
4962 /* machhwuo - machhwuo. */
4964 /* maclhw - maclhw. */
4966 /* maclhwo - maclhwo. */
4968 /* maclhws - maclhws. */
4970 /* maclhwso - maclhwso. */
4972 /* maclhwu - maclhwu. */
4974 /* maclhwuo - maclhwuo. */
4976 /* maclhwsu - maclhwsu. */
4978 /* maclhwsuo - maclhwsuo. */
4980 /* nmacchw - nmacchw. */
4982 /* nmacchwo - nmacchwo. */
4984 /* nmacchws - nmacchws. */
4986 /* nmacchwso - nmacchwso. */
4988 /* nmachhw - nmachhw. */
4990 /* nmachhwo - nmachhwo. */
4992 /* nmachhws - nmachhws. */
4994 /* nmachhwso - nmachhwso. */
4996 /* nmaclhw - nmaclhw. */
4998 /* nmaclhwo - nmaclhwo. */
5000 /* nmaclhws - nmaclhws. */
5002 /* nmaclhwso - nmaclhwso. */
5005 /* mulchw - mulchw. */
5007 /* mulchwu - mulchwu. */
5009 /* mulhhw - mulhhw. */
5011 /* mulhhwu - mulhhwu. */
5013 /* mullhw - mullhw. */
5015 /* mullhwu - mullhwu. */
5027 dcrn = tcg_constant_tl(SPR(ctx->opcode)); in gen_mfdcr()
5028 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], tcg_env, dcrn); in gen_mfdcr()
5041 dcrn = tcg_constant_tl(SPR(ctx->opcode)); in gen_mtdcr()
5042 gen_helper_store_dcr(tcg_env, dcrn, cpu_gpr[rS(ctx->opcode)]); in gen_mtdcr()
5054 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], tcg_env, in gen_mfdcrx()
5055 cpu_gpr[rA(ctx->opcode)]); in gen_mfdcrx()
5068 gen_helper_store_dcr(tcg_env, cpu_gpr[rA(ctx->opcode)], in gen_mtdcrx()
5069 cpu_gpr[rS(ctx->opcode)]); in gen_mtdcrx()
5078 /* interpreted as no-op */ in gen_dccci()
5095 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); in gen_dcread()
5103 * interpreted as no-op in gen_icbt_40x()
5113 /* interpreted as no-op */ in gen_iccci()
5120 /* interpreted as no-op */ in gen_icread()
5132 ctx->base.is_jmp = DISAS_EXIT; in gen_rfci_40x()
5144 ctx->base.is_jmp = DISAS_EXIT; in gen_rfci()
5159 ctx->base.is_jmp = DISAS_EXIT; in gen_rfdi()
5172 ctx->base.is_jmp = DISAS_EXIT; in gen_rfmci()
5176 /* TLB management - PowerPC 405 implementation */
5185 switch (rB(ctx->opcode)) { in gen_tlbre_40x()
5187 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], tcg_env, in gen_tlbre_40x()
5188 cpu_gpr[rA(ctx->opcode)]); in gen_tlbre_40x()
5191 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], tcg_env, in gen_tlbre_40x()
5192 cpu_gpr[rA(ctx->opcode)]); in gen_tlbre_40x()
5201 /* tlbsx - tlbsx. */
5212 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], tcg_env, t0); in gen_tlbsx_40x()
5213 if (Rc(ctx->opcode)) { in gen_tlbsx_40x()
5216 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); in gen_tlbsx_40x()
5231 switch (rB(ctx->opcode)) { in gen_tlbwe_40x()
5233 gen_helper_4xx_tlbwe_hi(tcg_env, cpu_gpr[rA(ctx->opcode)], in gen_tlbwe_40x()
5234 cpu_gpr[rS(ctx->opcode)]); in gen_tlbwe_40x()
5237 gen_helper_4xx_tlbwe_lo(tcg_env, cpu_gpr[rA(ctx->opcode)], in gen_tlbwe_40x()
5238 cpu_gpr[rS(ctx->opcode)]); in gen_tlbwe_40x()
5247 /* TLB management - PowerPC 440 implementation */
5257 switch (rB(ctx->opcode)) { in gen_tlbre_440()
5262 TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode)); in gen_tlbre_440()
5263 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], tcg_env, in gen_tlbre_440()
5264 t0, cpu_gpr[rA(ctx->opcode)]); in gen_tlbre_440()
5274 /* tlbsx - tlbsx. */
5285 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], tcg_env, t0); in gen_tlbsx_440()
5286 if (Rc(ctx->opcode)) { in gen_tlbsx_440()
5289 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); in gen_tlbsx_440()
5303 switch (rB(ctx->opcode)) { in gen_tlbwe_440()
5308 TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode)); in gen_tlbwe_440()
5309 gen_helper_440_tlbwe(tcg_env, t0, cpu_gpr[rA(ctx->opcode)], in gen_tlbwe_440()
5310 cpu_gpr[rS(ctx->opcode)]); in gen_tlbwe_440()
5320 /* TLB management - PowerPC BookE 2.06 implementation */
5333 /* tlbsx - tlbsx. */
5342 if (rA(ctx->opcode)) { in gen_tlbsx_booke206()
5344 tcg_gen_add_tl(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); in gen_tlbsx_booke206()
5346 t0 = cpu_gpr[rB(ctx->opcode)]; in gen_tlbsx_booke206()
5388 switch ((ctx->opcode >> 21) & 0x3) { in gen_tlbilx_booke206()
5415 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); in gen_wrtee()
5423 ctx->base.is_jmp = DISAS_EXIT_UPDATE; in gen_wrtee()
5434 if (ctx->opcode & 0x00008000) { in gen_wrteei()
5438 ctx->base.is_jmp = DISAS_EXIT_UPDATE; in gen_wrteei()
5450 TCGv_i32 t0 = tcg_constant_i32(Rc(ctx->opcode)); in gen_dlmzb()
5451 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], tcg_env, in gen_dlmzb()
5452 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); in gen_dlmzb()
5459 * interpreted as no-op in gen_icbt_440()
5467 if (unlikely(!ctx->tm_enabled)) { in gen_tbegin()
5477 if (unlikely(!ctx->tm_enabled)) { \
5519 if (unlikely(!ctx->tm_enabled)) { in GEN_CP_PASTE_NOOP()
5530 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); in GEN_CP_PASTE_NOOP()
5546 if (unlikely(!ctx->tm_enabled)) { \
5613 if (((CTX)->insns_flags & PPC_##NAME) == 0) { \
5620 if (((CTX)->insns_flags2 & PPC2_##NAME) == 0) { \
5625 /* Then special-case the check for 64-bit so that we elide code for ppc32. */
5634 if (unlikely(!(CTX)->altivec_enabled)) { \
5642 if (unlikely(!(CTX)->vsx_enabled)) { \
5650 if (unlikely(!(ctx)->fpu_enabled)) { \
5659 if (unlikely((CTX)->pr)) { \
5667 if (unlikely((CTX)->pr || !(CTX)->hv)) { \
5711 #include "decode-insn32.c.inc"
5712 #include "decode-insn64.c.inc"
5713 #include "power8-pmu-regs.c.inc"
5721 d->rt = a->rt; in resolve_PLS_D()
5722 d->ra = a->ra; in resolve_PLS_D()
5723 d->si = a->si; in resolve_PLS_D()
5724 if (a->r) { in resolve_PLS_D()
5725 if (unlikely(a->ra != 0)) { in resolve_PLS_D()
5729 d->si += ctx->cia; in resolve_PLS_D()
5734 #include "translate/fixedpoint-impl.c.inc"
5736 #include "translate/fp-impl.c.inc"
5738 #include "translate/vmx-impl.c.inc"
5740 #include "translate/vsx-impl.c.inc"
5742 #include "translate/dfp-impl.c.inc"
5744 #include "translate/spe-impl.c.inc"
5746 #include "translate/branch-impl.c.inc"
5748 #include "translate/processor-ctrl-impl.c.inc"
5750 #include "translate/storage-ctrl-impl.c.inc"
5752 #include "translate/misc-impl.c.inc"
5754 #include "translate/bhrb-impl.c.inc"
5759 if ((ctx->opcode & 0x3) == 0) { in gen_dform39()
5760 if (ctx->insns_flags2 & PPC2_ISA205) { in gen_dform39()
5770 if ((ctx->opcode & 3) == 0) { /* DS-FORM */ in gen_dform3D()
5772 if (ctx->insns_flags2 & PPC2_ISA205) { in gen_dform3D()
5783 tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); in gen_brd()
5789 tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); in gen_brw()
5790 tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32); in gen_brw()
5801 tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8); in gen_brh()
5803 tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], mask); in gen_brh()
5805 tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2); in gen_brh()
6146 #include "translate/fp-ops.c.inc"
6148 #include "translate/vmx-ops.c.inc"
6150 #include "translate/vsx-ops.c.inc"
6152 #include "translate/spe-ops.c.inc"
6200 return -1; in insert_in_table()
6213 return -1; in register_direct_insn()
6227 return -1; in register_ind_in_table()
6233 return -1; in register_ind_in_table()
6240 return -1; in register_ind_in_table()
6259 "[%02x-%02x]\n", idx1, idx2); in register_dblind_insn()
6260 return -1; in register_dblind_insn()
6265 "[%02x-%02x-%02x]\n", idx1, idx2, idx3); in register_dblind_insn()
6266 return -1; in register_dblind_insn()
6281 "[%02x-%02x]\n", idx1, idx2); in register_trplind_insn()
6282 return -1; in register_trplind_insn()
6286 printf("*** ERROR: unable to join 2nd-level indirect table idx " in register_trplind_insn()
6287 "[%02x-%02x-%02x]\n", idx1, idx2, idx3); in register_trplind_insn()
6288 return -1; in register_trplind_insn()
6293 "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4); in register_trplind_insn()
6294 return -1; in register_trplind_insn()
6300 if (insn->opc2 != 0xFF) { in register_insn()
6301 if (insn->opc3 != 0xFF) { in register_insn()
6302 if (insn->opc4 != 0xFF) { in register_insn()
6303 if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2, in register_insn()
6304 insn->opc3, insn->opc4, in register_insn()
6305 &insn->handler) < 0) { in register_insn()
6306 return -1; in register_insn()
6309 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2, in register_insn()
6310 insn->opc3, &insn->handler) < 0) { in register_insn()
6311 return -1; in register_insn()
6315 if (register_ind_insn(ppc_opcodes, insn->opc1, in register_insn()
6316 insn->opc2, &insn->handler) < 0) { in register_insn()
6317 return -1; in register_insn()
6321 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) { in register_insn()
6322 return -1; in register_insn()
6370 fill_new_table(cpu->opcodes, PPC_CPU_OPCODES_LEN); in create_ppc_opcodes()
6372 if (((opc->handler.type & pcc->insns_flags) != 0) || in create_ppc_opcodes()
6373 ((opc->handler.type2 & pcc->insns_flags2) != 0)) { in create_ppc_opcodes()
6374 if (register_insn(cpu->opcodes, opc) < 0) { in create_ppc_opcodes()
6376 "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2, in create_ppc_opcodes()
6377 opc->opc3); in create_ppc_opcodes()
6382 fix_opcode_tables(cpu->opcodes); in create_ppc_opcodes()
6393 if (cpu->opcodes[i] == &invalid_handler) { in destroy_ppc_opcodes()
6396 if (is_indirect_opcode(cpu->opcodes[i])) { in destroy_ppc_opcodes()
6397 table = ind_table(cpu->opcodes[i]); in destroy_ppc_opcodes()
6415 g_free((opc_handler_t *)((uintptr_t)cpu->opcodes[i] & in destroy_ppc_opcodes()
6423 CPUPPCState *env = &cpu->env; in ppc_fixup_cpu()
6434 if ((env->insns_flags & ~PPC_TCG_INSNS) in ppc_fixup_cpu()
6435 || (env->insns_flags2 & ~PPC_TCG_INSNS2)) { in ppc_fixup_cpu()
6438 env->insns_flags & ~PPC_TCG_INSNS, in ppc_fixup_cpu()
6439 env->insns_flags2 & ~PPC_TCG_INSNS2); in ppc_fixup_cpu()
6441 env->insns_flags &= PPC_TCG_INSNS; in ppc_fixup_cpu()
6442 env->insns_flags2 &= PPC_TCG_INSNS2; in ppc_fixup_cpu()
6453 ctx->le_mode ? "little" : "big"); in decode_legacy()
6455 table = cpu->opcodes; in decode_legacy()
6471 if (unlikely(handler->handler == &gen_invalid)) { in decode_legacy()
6473 "%02x - %02x - %02x - %02x (%08x) " in decode_legacy()
6476 insn, ctx->cia); in decode_legacy()
6480 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) in decode_legacy()
6482 inval = handler->inval2; in decode_legacy()
6484 inval = handler->inval1; in decode_legacy()
6489 "%02x - %02x - %02x - %02x (%08x) " in decode_legacy()
6492 insn, ctx->cia); in decode_legacy()
6496 handler->handler(ctx); in decode_legacy()
6504 uint32_t hflags = ctx->base.tb->flags; in ppc_tr_init_disas_context()
6506 ctx->spr_cb = env->spr_cb; in ppc_tr_init_disas_context()
6507 ctx->pr = (hflags >> HFLAGS_PR) & 1; in ppc_tr_init_disas_context()
6508 ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7; in ppc_tr_init_disas_context()
6509 ctx->dr = (hflags >> HFLAGS_DR) & 1; in ppc_tr_init_disas_context()
6510 ctx->hv = (hflags >> HFLAGS_HV) & 1; in ppc_tr_init_disas_context()
6511 ctx->insns_flags = env->insns_flags; in ppc_tr_init_disas_context()
6512 ctx->insns_flags2 = env->insns_flags2; in ppc_tr_init_disas_context()
6513 ctx->access_type = -1; in ppc_tr_init_disas_context()
6514 ctx->need_access_type = !mmu_is_64bit(env->mmu_model); in ppc_tr_init_disas_context()
6515 ctx->le_mode = (hflags >> HFLAGS_LE) & 1; in ppc_tr_init_disas_context()
6516 ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; in ppc_tr_init_disas_context()
6517 ctx->flags = env->flags; in ppc_tr_init_disas_context()
6519 ctx->excp_model = env->excp_model; in ppc_tr_init_disas_context()
6520 ctx->sf_mode = (hflags >> HFLAGS_64) & 1; in ppc_tr_init_disas_context()
6521 ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); in ppc_tr_init_disas_context()
6522 ctx->has_bhrb = !!(env->flags & POWERPC_FLAG_BHRB); in ppc_tr_init_disas_context()
6524 ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B in ppc_tr_init_disas_context()
6525 || env->mmu_model & POWERPC_MMU_64; in ppc_tr_init_disas_context()
6527 ctx->fpu_enabled = (hflags >> HFLAGS_FP) & 1; in ppc_tr_init_disas_context()
6528 ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1; in ppc_tr_init_disas_context()
6529 ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1; in ppc_tr_init_disas_context()
6530 ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1; in ppc_tr_init_disas_context()
6531 ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1; in ppc_tr_init_disas_context()
6532 ctx->gtse = (hflags >> HFLAGS_GTSE) & 1; in ppc_tr_init_disas_context()
6533 ctx->hr = (hflags >> HFLAGS_HR) & 1; in ppc_tr_init_disas_context()
6534 ctx->mmcr0_pmcc0 = (hflags >> HFLAGS_PMCC0) & 1; in ppc_tr_init_disas_context()
6535 ctx->mmcr0_pmcc1 = (hflags >> HFLAGS_PMCC1) & 1; in ppc_tr_init_disas_context()
6536 ctx->mmcr0_pmcjce = (hflags >> HFLAGS_PMCJCE) & 1; in ppc_tr_init_disas_context()
6537 ctx->pmc_other = (hflags >> HFLAGS_PMC_OTHER) & 1; in ppc_tr_init_disas_context()
6538 ctx->pmu_insn_cnt = (hflags >> HFLAGS_INSN_CNT) & 1; in ppc_tr_init_disas_context()
6539 ctx->bhrb_enable = (hflags >> HFLAGS_BHRB_ENABLE) & 1; in ppc_tr_init_disas_context()
6541 ctx->singlestep_enabled = 0; in ppc_tr_init_disas_context()
6543 ctx->singlestep_enabled |= CPU_SINGLE_STEP; in ppc_tr_init_disas_context()
6544 ctx->base.max_insns = 1; in ppc_tr_init_disas_context()
6547 ctx->singlestep_enabled |= CPU_BRANCH_STEP; in ppc_tr_init_disas_context()
6557 tcg_gen_insn_start(dcbase->pc_next); in ppc_tr_insn_start()
6575 LOG_DISAS("----------------\n"); in ppc_tr_translate_insn()
6577 ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); in ppc_tr_translate_insn()
6579 ctx->cia = pc = ctx->base.pc_next; in ppc_tr_translate_insn()
6581 ctx->base.pc_next = pc += 4; in ppc_tr_translate_insn()
6584 ctx->opcode = insn; in ppc_tr_translate_insn()
6591 * 64-byte address boundary (system alignment error). in ppc_tr_translate_insn()
6598 ctx->base.pc_next = pc += 4; in ppc_tr_translate_insn()
6606 if (ctx->base.is_jmp == DISAS_NEXT && !(pc & ~TARGET_PAGE_MASK)) { in ppc_tr_translate_insn()
6607 ctx->base.is_jmp = DISAS_TOO_MANY; in ppc_tr_translate_insn()
6614 DisasJumpType is_jmp = ctx->base.is_jmp; in ppc_tr_tb_stop()
6615 target_ulong nip = ctx->base.pc_next; in ppc_tr_tb_stop()
6623 if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP)) { in ppc_tr_tb_stop()
6656 tcg_gen_exit_tb(ctx->base.tb, 0); in ppc_tr_tb_stop()
6668 if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { in ppc_tr_tb_stop()