Lines Matching +full:rs +full:-
2 * Toshiba TX79-specific instructions translation routines
5 * Copyright (c) 2021 Philippe Mathieu-Daudé
7 * SPDX-License-Identifier: GPL-2.0-or-later
12 #include "tcg/tcg-op-gvec.h"
14 /* Include the auto-generated decoder. */
15 #include "decode-tx79.c.inc"
18 * Overview of the TX79-specific instruction set
21 * The R5900 and the C790 have 128-bit wide GPRs, where the upper 64 bits
22 * are only used by the specific quadword (128-bit) LQ/SQ load/store
24 * configure the 128-bit data path as two 64-bit, four 32-bit, eight 16-bit
25 * or sixteen 8-bit paths.
42 * Three-Operand Multiply and Multiply-Add (4 instructions)
43 * --------------------------------------------------------
44 * MADD [rd,] rs, rt Multiply/Add
45 * MADDU [rd,] rs, rt Multiply/Add Unsigned
46 * MULT [rd,] rs, rt Multiply (3-operand)
47 * MULTU [rd,] rs, rt Multiply Unsigned (3-operand)
52 * ------------------------------------------------------
53 * MULT1 [rd,] rs, rt Multiply Pipeline 1
54 * MULTU1 [rd,] rs, rt Multiply Unsigned Pipeline 1
55 * DIV1 rs, rt Divide Pipeline 1
56 * DIVU1 rs, rt Divide Unsigned Pipeline 1
57 * MADD1 [rd,] rs, rt Multiply-Add Pipeline 1
58 * MADDU1 [rd,] rs, rt Multiply-Add Unsigned Pipeline 1
61 * MTHI1 rs Move To HI1 Register
62 * MTLO1 rs Move To LO1 Register
67 gen_store_gpr(cpu_HI[1], a->rd); in trans_MFHI1()
74 gen_store_gpr(cpu_LO[1], a->rd); in trans_MFLO1()
81 gen_load_gpr(cpu_HI[1], a->rs); in trans_MTHI1()
88 gen_load_gpr(cpu_LO[1], a->rs); in trans_MTLO1()
95 * ----------------------------
96 * PADDB rd, rs, rt Parallel Add Byte
97 * PSUBB rd, rs, rt Parallel Subtract Byte
98 * PADDH rd, rs, rt Parallel Add Halfword
99 * PSUBH rd, rs, rt Parallel Subtract Halfword
100 * PADDW rd, rs, rt Parallel Add Word
101 * PSUBW rd, rs, rt Parallel Subtract Word
102 * PADSBH rd, rs, rt Parallel Add/Subtract Halfword
103 * PADDSB rd, rs, rt Parallel Add with Signed Saturation Byte
104 * PSUBSB rd, rs, rt Parallel Subtract with Signed Saturation Byte
105 * PADDSH rd, rs, rt Parallel Add with Signed Saturation Halfword
106 * PSUBSH rd, rs, rt Parallel Subtract with Signed Saturation Halfword
107 * PADDSW rd, rs, rt Parallel Add with Signed Saturation Word
108 * PSUBSW rd, rs, rt Parallel Subtract with Signed Saturation Word
109 * PADDUB rd, rs, rt Parallel Add with Unsigned saturation Byte
110 * PSUBUB rd, rs, rt Parallel Subtract with Unsigned saturation Byte
111 * PADDUH rd, rs, rt Parallel Add with Unsigned saturation Halfword
112 * PSUBUH rd, rs, rt Parallel Subtract with Unsigned saturation Halfword
113 * PADDUW rd, rs, rt Parallel Add with Unsigned saturation Word
114 * PSUBUW rd, rs, rt Parallel Subtract with Unsigned saturation Word
122 if (a->rd == 0) { in trans_parallel_arith()
131 gen_load_gpr(ax, a->rs); in trans_parallel_arith()
132 gen_load_gpr(bx, a->rt); in trans_parallel_arith()
133 gen_logic_i64(cpu_gpr[a->rd], ax, bx); in trans_parallel_arith()
136 gen_load_gpr_hi(ax, a->rs); in trans_parallel_arith()
137 gen_load_gpr_hi(bx, a->rt); in trans_parallel_arith()
138 gen_logic_i64(cpu_gpr_hi[a->rd], ax, bx); in trans_parallel_arith()
162 * ------------------------
163 * PMAXH rd, rs, rt Parallel Maximum Halfword
164 * PMINH rd, rs, rt Parallel Minimum Halfword
165 * PMAXW rd, rs, rt Parallel Maximum Word
166 * PMINW rd, rs, rt Parallel Minimum Word
171 * -------------------------
178 * ------------------------
179 * PAND rd, rs, rt Parallel AND
180 * POR rd, rs, rt Parallel OR
181 * PXOR rd, rs, rt Parallel XOR
182 * PNOR rd, rs, rt Parallel NOR
211 * ----------------------
218 * PSLLVW rd, rt, rs Parallel Shift Left Logical Variable Word
219 * PSRLVW rd, rt, rs Parallel Shift Right Logical Variable Word
220 * PSRAVW rd, rt, rs Parallel Shift Right Arithmetic Variable Word
225 * ------------------------
226 * PCGTB rd, rs, rt Parallel Compare for Greater Than Byte
227 * PCEQB rd, rs, rt Parallel Compare for Equal Byte
228 * PCGTH rd, rs, rt Parallel Compare for Greater Than Halfword
229 * PCEQH rd, rs, rt Parallel Compare for Equal Halfword
230 * PCGTW rd, rs, rt Parallel Compare for Greater Than Word
231 * PCEQW rd, rs, rt Parallel Compare for Equal Word
239 if (a->rd == 0) { in trans_parallel_compare()
253 gen_load_gpr(ax, a->rs); in trans_parallel_compare()
254 gen_load_gpr(bx, a->rt); in trans_parallel_compare()
259 tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], t2, wlen * i, wlen); in trans_parallel_compare()
262 gen_load_gpr_hi(ax, a->rs); in trans_parallel_compare()
263 gen_load_gpr_hi(bx, a->rt); in trans_parallel_compare()
268 tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rd], t2, wlen * i, wlen); in trans_parallel_compare()
311 * -------------------
312 * PLZCW rd, rs Parallel Leading Zero or One Count Word
317 * ----------------------------------------
327 if (a->rt == 0) { in trans_LQ()
335 gen_base_offset_addr(ctx, addr, a->base, a->offset); in trans_LQ()
337 * Clear least-significant four bits of the effective in trans_LQ()
343 tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, mo_endian(ctx) | MO_UQ); in trans_LQ()
344 gen_store_gpr(t0, a->rt); in trans_LQ()
348 tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, mo_endian(ctx) | MO_UQ); in trans_LQ()
349 gen_store_gpr_hi(t0, a->rt); in trans_LQ()
358 gen_base_offset_addr(ctx, addr, a->base, a->offset); in trans_SQ()
360 * Clear least-significant four bits of the effective in trans_SQ()
366 gen_load_gpr(t0, a->rt); in trans_SQ()
367 tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, mo_endian(ctx) | MO_UQ); in trans_SQ()
371 gen_load_gpr_hi(t0, a->rt); in trans_SQ()
372 tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, mo_endian(ctx) | MO_UQ); in trans_SQ()
378 * -------------------------------------
379 * PMULTW rd, rs, rt Parallel Multiply Word
380 * PMULTUW rd, rs, rt Parallel Multiply Unsigned Word
381 * PDIVW rs, rt Parallel Divide Word
382 * PDIVUW rs, rt Parallel Divide Unsigned Word
383 * PMADDW rd, rs, rt Parallel Multiply-Add Word
384 * PMADDUW rd, rs, rt Parallel Multiply-Add Unsigned Word
385 * PMSUBW rd, rs, rt Parallel Multiply-Subtract Word
386 * PMULTH rd, rs, rt Parallel Multiply Halfword
387 * PMADDH rd, rs, rt Parallel Multiply-Add Halfword
388 * PMSUBH rd, rs, rt Parallel Multiply-Subtract Halfword
389 * PHMADH rd, rs, rt Parallel Horizontal Multiply-Add Halfword
390 * PHMSBH rd, rs, rt Parallel Horizontal Multiply-Subtract Halfword
391 * PDIVBW rs, rt Parallel Divide Broadcast Word
394 * PMTHI rs Parallel Move To HI Register
395 * PMTLO rs Parallel Move To LO Register
397 * PMTHL rs Parallel Move To HI/LO Register
402 * -----------------------------
404 * PPACB rd, rs, rt Parallel Pack to Byte
405 * PPACH rd, rs, rt Parallel Pack to Halfword
406 * PPACW rd, rs, rt Parallel Pack to Word
408 * PEXTUB rd, rs, rt Parallel Extend Upper from Byte
409 * PEXTLB rd, rs, rt Parallel Extend Lower from Byte
410 * PEXTUH rd, rs, rt Parallel Extend Upper from Halfword
411 * PEXTLH rd, rs, rt Parallel Extend Lower from Halfword
412 * PEXTUW rd, rs, rt Parallel Extend Upper from Word
413 * PEXTLW rd, rs, rt Parallel Extend Lower from Word
421 if (a->rd == 0) { in trans_PPACW()
430 gen_load_gpr(a0, a->rs); in trans_PPACW()
431 gen_load_gpr(b0, a->rt); in trans_PPACW()
433 gen_load_gpr_hi(t0, a->rt); /* b1 */ in trans_PPACW()
434 tcg_gen_deposit_i64(cpu_gpr[a->rd], b0, t0, 32, 32); in trans_PPACW()
436 gen_load_gpr_hi(t0, a->rs); /* a1 */ in trans_PPACW()
437 tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], a0, t0, 32, 32); in trans_PPACW()
452 if (a->rd == 0) { in trans_PEXTLx()
460 gen_load_gpr(ax, a->rs); in trans_PEXTLx()
461 gen_load_gpr(bx, a->rt); in trans_PEXTLx()
465 tcg_gen_deposit_i64(cpu_gpr[a->rd], in trans_PEXTLx()
466 cpu_gpr[a->rd], bx, 2 * wlen * i, wlen); in trans_PEXTLx()
467 tcg_gen_deposit_i64(cpu_gpr[a->rd], in trans_PEXTLx()
468 cpu_gpr[a->rd], ax, 2 * wlen * i + wlen, wlen); in trans_PEXTLx()
474 tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], in trans_PEXTLx()
475 cpu_gpr_hi[a->rd], bx, 2 * wlen * i, wlen); in trans_PEXTLx()
476 tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], in trans_PEXTLx()
477 cpu_gpr_hi[a->rd], ax, 2 * wlen * i + wlen, wlen); in trans_PEXTLx()
501 if (a->rd == 0) { in trans_PEXTLW()
509 gen_load_gpr(ax, a->rs); in trans_PEXTLW()
510 gen_load_gpr(bx, a->rt); in trans_PEXTLW()
511 gen_pextw(cpu_gpr[a->rd], cpu_gpr_hi[a->rd], ax, bx); in trans_PEXTLW()
520 if (a->rd == 0) { in trans_PEXTUW()
528 gen_load_gpr_hi(ax, a->rs); in trans_PEXTUW()
529 gen_load_gpr_hi(bx, a->rt); in trans_PEXTUW()
530 gen_pextw(cpu_gpr[a->rd], cpu_gpr_hi[a->rd], ax, bx); in trans_PEXTUW()
536 * ------------------------
538 * PCPYLD rd, rs, rt Parallel Copy Lower Doubleword
539 * PCPYUD rd, rs, rt Parallel Copy Upper Doubleword
541 * PINTH rd, rs, rt Parallel Interleave Halfword
542 * PINTEH rd, rs, rt Parallel Interleave Even Halfword
547 * QFSRV rd, rs, rt Quadword Funnel Shift Right Variable
549 * MTSA rs Move to Shift Amount Register
550 * MTSAB rs, immediate Move Byte Count to Shift Amount Register
551 * MTSAH rs, immediate Move Halfword Count to Shift Amount Register
558 if (a->rd == 0) { in trans_PCPYH()
563 if (a->rt == 0) { in trans_PCPYH()
564 tcg_gen_movi_i64(cpu_gpr[a->rd], 0); in trans_PCPYH()
565 tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0); in trans_PCPYH()
569 tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rt], cpu_gpr[a->rt], 16, 16); in trans_PCPYH()
570 tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], cpu_gpr[a->rd], 32, 32); in trans_PCPYH()
571 tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rt], cpu_gpr_hi[a->rt], 16, 16); in trans_PCPYH()
572 tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rd], 32, 32); in trans_PCPYH()
580 if (a->rd == 0) { in trans_PCPYLD()
585 if (a->rs == 0) { in trans_PCPYLD()
586 tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0); in trans_PCPYLD()
588 tcg_gen_mov_i64(cpu_gpr_hi[a->rd], cpu_gpr[a->rs]); in trans_PCPYLD()
591 if (a->rt == 0) { in trans_PCPYLD()
592 tcg_gen_movi_i64(cpu_gpr[a->rd], 0); in trans_PCPYLD()
593 } else if (a->rd != a->rt) { in trans_PCPYLD()
594 tcg_gen_mov_i64(cpu_gpr[a->rd], cpu_gpr[a->rt]); in trans_PCPYLD()
603 if (a->rd == 0) { in trans_PCPYUD()
608 gen_load_gpr_hi(cpu_gpr[a->rd], a->rs); in trans_PCPYUD()
610 if (a->rt == 0) { in trans_PCPYUD()
611 tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0); in trans_PCPYUD()
612 } else if (a->rd != a->rt) { in trans_PCPYUD()
613 tcg_gen_mov_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rt]); in trans_PCPYUD()
624 if (a->rd == 0) { in trans_PROT3W()
628 if (a->rt == 0) { in trans_PROT3W()
629 tcg_gen_movi_i64(cpu_gpr[a->rd], 0); in trans_PROT3W()
630 tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0); in trans_PROT3W()
636 tcg_gen_mov_i64(ax, cpu_gpr_hi[a->rt]); in trans_PROT3W()
637 tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], ax, cpu_gpr[a->rt], 0, 32); in trans_PROT3W()
639 tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rt], ax, 0, 32); in trans_PROT3W()
640 tcg_gen_rotri_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], 32); in trans_PROT3W()