Lines Matching +full:se +full:- +full:neg
22 #include "qemu/host-utils.h"
23 #include "exec/exec-all.h"
24 #include "exec/page-protection.h"
25 #include "tcg/tcg-op.h"
26 #include "tcg/tcg-op-gvec.h"
27 #include "exec/helper-proto.h"
28 #include "exec/helper-gen.h"
33 #include "exec/helper-info.c.inc"
98 #define UNALIGN(C) (C)->unalign
102 #define MMU_DISABLED(C) MMU_IDX_MMU_DISABLED((C)->mmu_idx)
108 /* Keep unimplemented bits disabled -- see cpu_hppa_put_psw. */ in expand_sm_imm()
109 if (ctx->is_pa20) { in expand_sm_imm()
126 /* Convert the M:A bits within a memory insn to the tri-state value
130 return val & 2 ? (val & 1 ? -1 : 1) : 0; in ma_to_m()
133 /* Convert the sign of the displacement to a pre or post-modify. */
136 return val ? 1 : -1; in pos_to_m()
141 return val ? -1 : 1; in neg_to_m()
159 * Officially, 32 * x + 32 - y. in assemble_6()
161 * Since -y = ~y + 1, in 5 bits 32 - y => y ^ 31 + 1, in assemble_6()
176 int i = (-(val & 1) << 13) | (im10a << 3); in expand_11a()
178 if (ctx->tb_flags & PSW_W) { in expand_11a()
193 int i = (-(val & 1) << 13) | (im11a << 2); in expand_12a()
195 if (ctx->tb_flags & PSW_W) { in expand_12a()
209 int i = (-(val & 1) << 13) | extract32(val, 1, 13); in expand_16()
211 if (ctx->tb_flags & PSW_W) { in expand_16()
220 return ctx->tb_flags & PSW_W ? 0 : sp; in sp0_if_wide()
235 return ctx->is_pa20 & val; in pa20_d()
238 /* Include the auto-generated decoder. */
239 #include "decode-insns.c.inc"
293 /* SR[4-7] are not global registers so that we can index them. */ in hppa_translate_init()
317 *v->var = tcg_global_mem_new(tcg_env, v->ofs, v->name); in hppa_translate_init()
333 assert(!ctx->insn_start_updated); in set_insn_breg()
334 ctx->insn_start_updated = true; in set_insn_breg()
335 tcg_set_insn_start_param(ctx->base.insn_start, 2, breg); in set_insn_breg()
396 return ctx->zero; in load_gpr()
404 if (reg == 0 || ctx->null_cond.c != TCG_COND_NEVER) { in dest_gpr()
413 if (ctx->null_cond.c != TCG_COND_NEVER) { in save_or_nullify()
414 tcg_gen_movcond_i64(ctx->null_cond.c, dest, ctx->null_cond.a0, in save_or_nullify()
415 ctx->null_cond.a1, dest, t); in save_or_nullify()
509 } else if (ctx->tb_flags & TB_FLAG_SR_SAME) { in load_spr()
524 if (ctx->psw_xb != xb) { in store_psw_xb()
533 ctx->psw_xb = xb; in set_psw_xb()
540 if (ctx->null_cond.c != TCG_COND_NEVER) { in nullify_over()
542 assert(ctx->null_cond.c != TCG_COND_ALWAYS); in nullify_over()
544 ctx->null_lab = gen_new_label(); in nullify_over()
547 if (ctx->null_cond.a0 == cpu_psw_n) { in nullify_over()
548 ctx->null_cond.a0 = tcg_temp_new_i64(); in nullify_over()
549 tcg_gen_mov_i64(ctx->null_cond.a0, cpu_psw_n); in nullify_over()
554 if (ctx->psw_n_nonzero) { in nullify_over()
555 ctx->psw_n_nonzero = false; in nullify_over()
559 tcg_gen_brcond_i64(ctx->null_cond.c, ctx->null_cond.a0, in nullify_over()
560 ctx->null_cond.a1, ctx->null_lab); in nullify_over()
561 ctx->null_cond = cond_make_f(); in nullify_over()
568 if (ctx->null_cond.c == TCG_COND_NEVER) { in nullify_save()
569 if (ctx->psw_n_nonzero) { in nullify_save()
574 if (ctx->null_cond.a0 != cpu_psw_n) { in nullify_save()
575 tcg_gen_setcond_i64(ctx->null_cond.c, cpu_psw_n, in nullify_save()
576 ctx->null_cond.a0, ctx->null_cond.a1); in nullify_save()
577 ctx->psw_n_nonzero = true; in nullify_save()
579 ctx->null_cond = cond_make_f(); in nullify_save()
587 if (ctx->psw_n_nonzero || x) { in nullify_set()
594 it may be tail-called from a translate function. */
597 TCGLabel *null_lab = ctx->null_lab; in nullify_end()
598 DisasJumpType status = ctx->base.is_jmp; in nullify_end()
604 assert(!ctx->psw_b_next); in nullify_end()
612 ctx->null_lab = NULL; in nullify_end()
614 if (likely(ctx->null_cond.c == TCG_COND_NEVER)) { in nullify_end()
625 ctx->null_cond = cond_make_n(); in nullify_end()
628 ctx->base.is_jmp = DISAS_NEXT; in nullify_end()
635 return e->base || e->space; in iaqe_variable()
641 .space = e->space, in iaqe_incr()
642 .base = e->base, in iaqe_incr()
643 .disp = e->disp + disp, in iaqe_incr()
650 .space = ctx->iaq_b.space, in iaqe_branchi()
651 .disp = ctx->iaq_f.disp + 8 + disp, in iaqe_branchi()
658 .space = ctx->iaq_b.space, in iaqe_next_absv()
666 tcg_gen_addi_i64(dest, src->base ? : cpu_iaoq_f, src->disp); in copy_iaoq_entry()
687 if (f->base != cpu_iaoq_b) { in install_iaq_entries()
690 } else if (f->base == b->base) { in install_iaq_entries()
692 tcg_gen_addi_i64(cpu_iaoq_b, cpu_iaoq_f, b->disp - f->disp); in install_iaq_entries()
700 if (f->space) { in install_iaq_entries()
701 tcg_gen_mov_i64(cpu_iasq_f, f->space); in install_iaq_entries()
703 if (b->space || f->space) { in install_iaq_entries()
704 tcg_gen_mov_i64(cpu_iasq_b, b->space ? : f->space); in install_iaq_entries()
710 tcg_debug_assert(ctx->null_cond.c == TCG_COND_NEVER); in install_link()
714 DisasIAQE next = iaqe_incr(&ctx->iaq_b, 4); in install_link()
730 install_iaq_entries(ctx, &ctx->iaq_f, &ctx->iaq_b); in gen_excp()
733 ctx->base.is_jmp = DISAS_NORETURN; in gen_excp()
741 e->next = ctx->delay_excp_list; in delay_excp()
742 ctx->delay_excp_list = e; in delay_excp()
744 e->lab = gen_new_label(); in delay_excp()
745 e->insn = ctx->insn; in delay_excp()
746 e->set_iir = true; in delay_excp()
747 e->set_n = ctx->psw_n_nonzero ? 0 : -1; in delay_excp()
748 e->excp = excp; in delay_excp()
749 e->iaq_f = ctx->iaq_f; in delay_excp()
750 e->iaq_b = ctx->iaq_b; in delay_excp()
757 if (ctx->null_cond.c == TCG_COND_NEVER) { in gen_excp_iir()
758 tcg_gen_st_i64(tcg_constant_i64(ctx->insn), in gen_excp_iir()
763 tcg_gen_brcond_i64(tcg_invert_cond(ctx->null_cond.c), in gen_excp_iir()
764 ctx->null_cond.a0, ctx->null_cond.a1, e->lab); in gen_excp_iir()
765 ctx->null_cond = cond_make_f(); in gen_excp_iir()
781 if (ctx->privilege != 0) { \
792 translator_use_goto_tb(&ctx->base, ctx->iaoq_first + f->disp)); in use_goto_tb()
801 return (!(tb_cflags(ctx->base.tb) & CF_BP_PAGE) in use_nullify_skip()
802 && !iaqe_variable(&ctx->iaq_b) in use_nullify_skip()
803 && (((ctx->iaoq_first + ctx->iaq_b.disp) ^ ctx->iaoq_first) in use_nullify_skip()
813 tcg_gen_exit_tb(ctx->base.tb, which); in gen_goto_tb()
830 * Compute conditional for arithmetic. See Page 5-3, Table 5-1, of
843 /* 64-bit condition. */ in do_cond()
849 /* 32-bit condition. */ in do_cond()
881 ctx->zero, res); in do_cond()
889 tcg_gen_movcond_i64(TCG_COND_EQ, tmp, uv, ctx->zero, ctx->zero, res); in do_cond()
1021 0-2 are the same as logicals (nv,<,<=), while 3 is OD. in do_sed_cond()
1022 4-7 are the reverse of 0-3. */ in do_sed_cond()
1120 tcg_gen_extract_i64(tmp, tmp, sign_bit - shift, shift); in do_add_sv()
1121 tcg_gen_movcond_i64(TCG_COND_NE, sv, tmp, ctx->zero, in do_add_sv()
1122 tcg_constant_i64(-1), sv); in do_add_sv()
1136 tcg_gen_extract_i64(tmp, in1, (d ? 63 : 31) - shift, shift); in do_add_uv()
1160 switch (cond->c) { in gen_tc()
1168 tcg_gen_brcond_i64(cond->c, cond->a0, cond->a1, e->lab); in gen_tc()
1169 /* In the non-trap path, the condition is known false. */ in gen_tc()
1180 tcg_gen_brcond_i64(cond.c, cond.a0, cond.a1, e->lab); in gen_tsv()
1182 /* In the non-trap path, V is known zero. */ in gen_tsv()
1209 tcg_gen_add2_i64(dest, cb_msb, in1, ctx->zero, in2, ctx->zero); in do_add()
1212 get_psw_carry(ctx, d), ctx->zero); in do_add()
1252 ctx->null_cond = cond; in do_add()
1260 if (unlikely(is_tc && a->cf == 1)) { in do_add_reg()
1264 if (a->cf) { in do_add_reg()
1267 tcg_r1 = load_gpr(ctx, a->r1); in do_add_reg()
1268 tcg_r2 = load_gpr(ctx, a->r2); in do_add_reg()
1269 do_add(ctx, a->t, tcg_r1, tcg_r2, a->sh, is_l, in do_add_reg()
1270 is_tsv, is_tc, is_c, a->cf, a->d); in do_add_reg()
1279 if (unlikely(is_tc && a->cf == 1)) { in do_add_imm()
1283 if (a->cf) { in do_add_imm()
1286 tcg_im = tcg_constant_i64(a->i); in do_add_imm()
1287 tcg_r2 = load_gpr(ctx, a->r); in do_add_imm()
1288 /* All ADDI conditions are 32-bit. */ in do_add_imm()
1289 do_add(ctx, a->t, tcg_im, tcg_r2, 0, 0, is_tsv, is_tc, 0, a->cf, false); in do_add_imm()
1308 tcg_gen_add2_i64(dest, cb_msb, in1, ctx->zero, in do_sub()
1309 get_psw_carry(ctx, d), ctx->zero); in do_sub()
1310 tcg_gen_add2_i64(dest, cb_msb, dest, cb_msb, cb, ctx->zero); in do_sub()
1319 tcg_gen_sub2_i64(dest, cb_msb, in1, one, in2, ctx->zero); in do_sub()
1351 ctx->null_cond = cond; in do_sub()
1359 if (a->cf) { in do_sub_reg()
1362 tcg_r1 = load_gpr(ctx, a->r1); in do_sub_reg()
1363 tcg_r2 = load_gpr(ctx, a->r2); in do_sub_reg()
1364 do_sub(ctx, a->t, tcg_r1, tcg_r2, is_tsv, is_b, is_tc, a->cf, a->d); in do_sub_reg()
1372 if (a->cf) { in do_sub_imm()
1375 tcg_im = tcg_constant_i64(a->i); in do_sub_imm()
1376 tcg_r2 = load_gpr(ctx, a->r); in do_sub_imm()
1377 /* All SUBI conditions are 32-bit. */ in do_sub_imm()
1378 do_sub(ctx, a->t, tcg_im, tcg_r2, is_tsv, 0, 0, a->cf, false); in do_sub_imm()
1405 ctx->null_cond = cond; in do_cmpclr()
1419 ctx->null_cond = do_log_cond(ctx, cf, d, dest); in do_log()
1427 if (a->cf) { in do_log_reg()
1430 tcg_r1 = load_gpr(ctx, a->r1); in do_log_reg()
1431 tcg_r2 = load_gpr(ctx, a->r2); in do_log_reg()
1432 do_log(ctx, a->t, tcg_r1, tcg_r2, a->cf, a->d, fn); in do_log_reg()
1444 /* Select which carry-out bits to test. */ in do_unit_addsub()
1446 case 4: /* NDC / SDC -- 4-bit carries */ in do_unit_addsub()
1449 case 5: /* NWC / SWC -- 32-bit carries */ in do_unit_addsub()
1453 cf &= 1; /* undefined -- map to never/always */ in do_unit_addsub()
1456 case 6: /* NBC / SBC -- 8-bit carries */ in do_unit_addsub()
1459 case 7: /* NHC / SHC -- 16-bit carries */ in do_unit_addsub()
1481 tcg_gen_add2_i64(dest, cb_msb, in1, ctx->zero, in2, ctx->zero); in do_unit_addsub()
1486 tcg_gen_sub2_i64(dest, cb_msb, in1, one, in2, ctx->zero); in do_unit_addsub()
1512 ctx->null_cond = cond; in do_unit_addsub()
1518 instructions that have a 3-bit space specifier, for which SR0 is
1534 if (ctx->tb_flags & TB_FLAG_SR_SAME) { in space_select()
1543 tcg_gen_shri_i64(tmp, base, (ctx->tb_flags & PSW_W ? 64 : 32) - 5); in space_select()
1579 gva_offset_mask(ctx->tb_flags)); in form_gva()
1588 * < 0 for pre-modify,
1589 * > 0 for post-modify,
1600 assert(ctx->null_cond.c == TCG_COND_NEVER); in do_load_32()
1604 tcg_gen_qemu_ld_i32(dest, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); in do_load_32()
1618 assert(ctx->null_cond.c == TCG_COND_NEVER); in do_load_64()
1622 tcg_gen_qemu_ld_i64(dest, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); in do_load_64()
1636 assert(ctx->null_cond.c == TCG_COND_NEVER); in do_store_32()
1640 tcg_gen_qemu_st_i32(src, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); in do_store_32()
1654 assert(ctx->null_cond.c == TCG_COND_NEVER); in do_store_64()
1658 tcg_gen_qemu_st_i64(src, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); in do_store_64()
1706 return do_floadw(ctx, a->t, a->b, a->x, a->scale ? 2 : 0, in trans_fldw()
1707 a->disp, a->sp, a->m); in trans_fldw()
1731 return do_floadd(ctx, a->t, a->b, a->x, a->scale ? 3 : 0, in trans_fldd()
1732 a->disp, a->sp, a->m); in trans_fldd()
1760 return do_fstorew(ctx, a->t, a->b, a->x, a->scale ? 2 : 0, in trans_fstw()
1761 a->disp, a->sp, a->m); in trans_fstw()
1780 return do_fstored(ctx, a->t, a->b, a->x, a->scale ? 3 : 0, in trans_fstd()
1781 a->disp, a->sp, a->m); in trans_fstd()
1881 ctx->iaq_j = iaqe_branchi(ctx, disp); in do_dbranch()
1883 if (ctx->null_cond.c == TCG_COND_NEVER && ctx->null_lab == NULL) { in do_dbranch()
1889 gen_goto_tb(ctx, 0, &ctx->iaq_j, NULL); in do_dbranch()
1890 ctx->base.is_jmp = DISAS_NORETURN; in do_dbranch()
1893 ctx->null_cond.c = TCG_COND_ALWAYS; in do_dbranch()
1895 ctx->iaq_n = &ctx->iaq_j; in do_dbranch()
1896 ctx->psw_b_next = true; in do_dbranch()
1904 gen_goto_tb(ctx, 0, &ctx->iaq_j, NULL); in do_dbranch()
1908 gen_goto_tb(ctx, 0, &ctx->iaq_b, &ctx->iaq_j); in do_dbranch()
1914 gen_goto_tb(ctx, 1, &ctx->iaq_b, NULL); in do_dbranch()
1915 ctx->base.is_jmp = DISAS_NORETURN; in do_dbranch()
1927 TCGCond c = cond->c; in do_cbranch()
1930 assert(ctx->null_cond.c == TCG_COND_NEVER); in do_cbranch()
1938 tcg_gen_brcond_i64(c, cond->a0, cond->a1, taken); in do_cbranch()
1945 next = iaqe_incr(&ctx->iaq_b, 4); in do_cbranch()
1948 if (!n && ctx->null_lab) { in do_cbranch()
1949 gen_set_label(ctx->null_lab); in do_cbranch()
1950 ctx->null_lab = NULL; in do_cbranch()
1954 gen_goto_tb(ctx, 0, &ctx->iaq_b, NULL); in do_cbranch()
1970 gen_goto_tb(ctx, 1, &ctx->iaq_b, &next); in do_cbranch()
1974 if (ctx->null_lab) { in do_cbranch()
1975 gen_set_label(ctx->null_lab); in do_cbranch()
1976 ctx->null_lab = NULL; in do_cbranch()
1977 ctx->base.is_jmp = DISAS_IAQ_N_STALE; in do_cbranch()
1979 ctx->base.is_jmp = DISAS_NORETURN; in do_cbranch()
1985 * Emit an unconditional branch to an indirect target, in ctx->iaq_j.
1991 if (ctx->null_cond.c == TCG_COND_NEVER && ctx->null_lab == NULL) { in do_ibranch()
1995 install_iaq_entries(ctx, &ctx->iaq_j, NULL); in do_ibranch()
1997 ctx->base.is_jmp = DISAS_IAQ_N_UPDATED; in do_ibranch()
2000 ctx->null_cond.c = TCG_COND_ALWAYS; in do_ibranch()
2002 ctx->iaq_n = &ctx->iaq_j; in do_ibranch()
2003 ctx->psw_b_next = true; in do_ibranch()
2011 install_iaq_entries(ctx, &ctx->iaq_j, NULL); in do_ibranch()
2015 install_iaq_entries(ctx, &ctx->iaq_b, &ctx->iaq_j); in do_ibranch()
2021 ctx->base.is_jmp = DISAS_NORETURN; in do_ibranch()
2035 switch (ctx->privilege) { in do_ibranch_priv()
2045 tcg_gen_andi_i64(dest, offset, -4); in do_ibranch_priv()
2046 tcg_gen_ori_i64(dest, dest, ctx->privilege); in do_ibranch_priv()
2063 assert(ctx->iaq_f.disp == 0); in do_page_zero()
2068 switch (ctx->null_cond.c) { in do_page_zero()
2076 TB, we should know the state of PSW[N] from TB->FLAGS. */ in do_page_zero()
2081 if (ctx->psw_xb & PSW_B) { in do_page_zero()
2085 switch (ctx->base.pc_first) { in do_page_zero()
2088 ctx->base.is_jmp = DISAS_NORETURN; in do_page_zero()
2093 ctx->base.is_jmp = DISAS_NORETURN; in do_page_zero()
2104 ctx->base.is_jmp = DISAS_IAQ_N_UPDATED; in do_page_zero()
2110 ctx->base.is_jmp = DISAS_NORETURN; in do_page_zero()
2116 ctx->base.is_jmp = DISAS_NORETURN; in do_page_zero()
2124 ctx->null_cond = cond_make_f(); in trans_nop()
2138 ctx->null_cond = cond_make_f(); in trans_sync()
2144 TCGv_i64 dest = dest_gpr(ctx, a->t); in trans_mfia()
2146 copy_iaoq_entry(ctx, dest, &ctx->iaq_f); in trans_mfia()
2147 tcg_gen_andi_i64(dest, dest, -4); in trans_mfia()
2149 save_gpr(ctx, a->t, dest); in trans_mfia()
2150 ctx->null_cond = cond_make_f(); in trans_mfia()
2156 unsigned rt = a->t; in trans_mfsp()
2157 unsigned rs = a->sp; in trans_mfsp()
2165 ctx->null_cond = cond_make_f(); in trans_mfsp()
2171 unsigned rt = a->t; in trans_mfctl()
2172 unsigned ctl = a->r; in trans_mfctl()
2177 if (a->e == 0) { in trans_mfctl()
2190 if (translator_io_start(&ctx->base)) { in trans_mfctl()
2191 ctx->base.is_jmp = DISAS_IAQ_N_STALE; in trans_mfctl()
2210 ctx->null_cond = cond_make_f(); in trans_mfctl()
2216 unsigned rr = a->r; in trans_mtsp()
2217 unsigned rs = a->sp; in trans_mtsp()
2230 ctx->tb_flags &= ~TB_FLAG_SR_SAME; in trans_mtsp()
2240 unsigned ctl = a->t; in trans_mtctl()
2245 reg = load_gpr(ctx, a->r); in trans_mtctl()
2247 tcg_gen_andi_i64(tmp, reg, ctx->is_pa20 ? 63 : 31); in trans_mtctl()
2250 ctx->null_cond = cond_make_f(); in trans_mtctl()
2254 /* All other control registers are privileged or read-only. */ in trans_mtctl()
2260 if (ctx->is_pa20) { in trans_mtctl()
2261 reg = load_gpr(ctx, a->r); in trans_mtctl()
2264 tcg_gen_ext32u_i64(reg, load_gpr(ctx, a->r)); in trans_mtctl()
2269 if (translator_io_start(&ctx->base)) { in trans_mtctl()
2270 ctx->base.is_jmp = DISAS_IAQ_N_STALE; in trans_mtctl()
2276 translator_io_start(&ctx->base); in trans_mtctl()
2278 /* Exit to re-evaluate interrupts in the main loop. */ in trans_mtctl()
2279 ctx->base.is_jmp = DISAS_IAQ_N_STALE_EXIT; in trans_mtctl()
2288 offsetof(CPUHPPAState, cr_back[ctl - CR_IIASQ])); in trans_mtctl()
2291 offsetof(CPUHPPAState, cr_back[ctl - CR_IIASQ])); in trans_mtctl()
2305 /* Exit to re-evaluate interrupts in the main loop. */ in trans_mtctl()
2306 ctx->base.is_jmp = DISAS_IAQ_N_STALE_EXIT; in trans_mtctl()
2320 tcg_gen_not_i64(tmp, load_gpr(ctx, a->r)); in trans_mtsarcm()
2321 tcg_gen_andi_i64(tmp, tmp, ctx->is_pa20 ? 63 : 31); in trans_mtsarcm()
2324 ctx->null_cond = cond_make_f(); in trans_mtsarcm()
2330 TCGv_i64 dest = dest_gpr(ctx, a->t); in trans_ldsid()
2336 tcg_gen_mov_i64(dest, space_select(ctx, a->sp, load_gpr(ctx, a->b))); in trans_ldsid()
2339 save_gpr(ctx, a->t, dest); in trans_ldsid()
2341 ctx->null_cond = cond_make_f(); in trans_ldsid()
2352 /* HP-UX 11i and HP ODE use rsm for read-access to PSW */ in trans_rsm()
2353 if (a->i) { in trans_rsm()
2361 tcg_gen_andi_i64(tmp, tmp, ~a->i); in trans_rsm()
2363 save_gpr(ctx, a->t, tmp); in trans_rsm()
2366 ctx->base.is_jmp = DISAS_IAQ_N_STALE_EXIT; in trans_rsm()
2381 tcg_gen_ori_i64(tmp, tmp, a->i); in trans_ssm()
2383 save_gpr(ctx, a->t, tmp); in trans_ssm()
2386 ctx->base.is_jmp = DISAS_IAQ_N_STALE_EXIT; in trans_ssm()
2398 reg = load_gpr(ctx, a->r); in trans_mtsm()
2403 ctx->base.is_jmp = DISAS_IAQ_N_STALE_EXIT; in trans_mtsm()
2421 ctx->base.is_jmp = DISAS_NORETURN; in do_rfi()
2444 ctx->base.is_jmp = DISAS_NORETURN; in trans_halt()
2456 ctx->base.is_jmp = DISAS_NORETURN; in trans_reset()
2496 if (a->m) { in trans_nop_addrx()
2497 TCGv_i64 dest = dest_gpr(ctx, a->b); in trans_nop_addrx()
2498 TCGv_i64 src1 = load_gpr(ctx, a->b); in trans_nop_addrx()
2499 TCGv_i64 src2 = load_gpr(ctx, a->x); in trans_nop_addrx()
2503 save_gpr(ctx, a->b, dest); in trans_nop_addrx()
2505 ctx->null_cond = cond_make_f(); in trans_nop_addrx()
2512 ctx->base.is_jmp = DISAS_IAQ_N_STALE; in trans_fic()
2524 dest = dest_gpr(ctx, a->t); in trans_probe()
2525 form_gva(ctx, &addr, &ofs, a->b, 0, 0, 0, a->sp, 0, false); in trans_probe()
2527 if (a->imm) { in trans_probe()
2528 level = tcg_constant_i32(a->ri & 3); in trans_probe()
2531 tcg_gen_extrl_i64_i32(level, load_gpr(ctx, a->ri)); in trans_probe()
2534 want = tcg_constant_i32(a->write ? PAGE_WRITE : PAGE_READ); in trans_probe()
2538 save_gpr(ctx, a->t, dest); in trans_probe()
2544 if (ctx->is_pa20) { in trans_ixtlbx()
2554 form_gva(ctx, &addr, &ofs, a->b, 0, 0, 0, a->sp, 0, false); in trans_ixtlbx()
2555 reg = load_gpr(ctx, a->r); in trans_ixtlbx()
2556 if (a->addr) { in trans_ixtlbx()
2563 if (ctx->tb_flags & PSW_C) { in trans_ixtlbx()
2564 ctx->base.is_jmp = DISAS_IAQ_N_STALE; in trans_ixtlbx()
2579 form_gva(ctx, &addr, &ofs, a->b, a->x, 0, 0, a->sp, a->m, false); in do_pxtlb()
2586 if (ctx->is_pa20) { in do_pxtlb()
2587 tcg_gen_deposit_i64(addr, addr, load_gpr(ctx, a->b), 0, 4); in do_pxtlb()
2596 if (a->m) { in do_pxtlb()
2597 save_gpr(ctx, a->b, ofs); in do_pxtlb()
2601 if (ctx->tb_flags & PSW_C) { in do_pxtlb()
2602 ctx->base.is_jmp = DISAS_IAQ_N_STALE; in do_pxtlb()
2615 return ctx->is_pa20 && do_pxtlb(ctx, a, true); in trans_pxtlb_l()
2628 if (ctx->tb_flags & PSW_C) { in trans_pxtlbe()
2629 ctx->base.is_jmp = DISAS_IAQ_N_STALE; in trans_pxtlbe()
2638 * https://parisc.wiki.kernel.org/images-parisc/a/a9/Pcxl2_ers.pdf
2639 * page 13-9 (195/206)
2643 if (ctx->is_pa20) { in trans_ixtlbxf()
2664 a->data ? offsetof(CPUHPPAState, cr[CR_ISR]) in trans_ixtlbxf()
2667 a->data ? offsetof(CPUHPPAState, cr[CR_IOR]) in trans_ixtlbxf()
2672 reg = load_gpr(ctx, a->r); in trans_ixtlbxf()
2673 if (a->addr) { in trans_ixtlbxf()
2680 if (ctx->tb_flags & PSW_C) { in trans_ixtlbxf()
2681 ctx->base.is_jmp = DISAS_IAQ_N_STALE; in trans_ixtlbxf()
2689 if (!ctx->is_pa20) { in trans_ixtlbt()
2696 TCGv_i64 src1 = load_gpr(ctx, a->r1); in trans_ixtlbt()
2697 TCGv_i64 src2 = load_gpr(ctx, a->r2); in trans_ixtlbt()
2699 if (a->data) { in trans_ixtlbt()
2706 if (ctx->tb_flags & PSW_C) { in trans_ixtlbt()
2707 ctx->base.is_jmp = DISAS_IAQ_N_STALE; in trans_ixtlbt()
2722 form_gva(ctx, &vaddr, &ofs, a->b, a->x, 0, 0, a->sp, a->m, false); in trans_lpa()
2728 if (a->m) { in trans_lpa()
2729 save_gpr(ctx, a->b, ofs); in trans_lpa()
2731 save_gpr(ctx, a->t, paddr); in trans_lpa()
2741 /* The Coherence Index is an implementation-defined function of the in trans_lci()
2745 save_gpr(ctx, a->t, ctx->zero); in trans_lci()
2747 ctx->null_cond = cond_make_f(); in trans_lci()
2818 if (a->cf == 0) { in trans_or()
2819 unsigned r2 = a->r2; in trans_or()
2820 unsigned r1 = a->r1; in trans_or()
2821 unsigned rt = a->t; in trans_or()
2824 ctx->null_cond = cond_make_f(); in trans_or()
2835 ctx->null_cond = cond_make_f(); in trans_or()
2841 * or %r10,%r10,%r10 -- idle loop; wait for interrupt in trans_or()
2842 * or %r31,%r31,%r31 -- death loop; offline cpu in trans_or()
2854 install_iaq_entries(ctx, &ctx->iaq_b, NULL); in trans_or()
2859 offsetof(CPUState, halted) - offsetof(HPPACPU, env)); in trans_or()
2861 ctx->base.is_jmp = DISAS_NORETURN; in trans_or()
2879 if (a->cf) { in trans_cmpclr()
2882 tcg_r1 = load_gpr(ctx, a->r1); in trans_cmpclr()
2883 tcg_r2 = load_gpr(ctx, a->r2); in trans_cmpclr()
2884 do_cmpclr(ctx, a->t, tcg_r1, tcg_r2, a->cf, a->d); in trans_cmpclr()
2892 if (a->cf) { in trans_uxor()
2896 tcg_r1 = load_gpr(ctx, a->r1); in trans_uxor()
2897 tcg_r2 = load_gpr(ctx, a->r2); in trans_uxor()
2898 dest = dest_gpr(ctx, a->t); in trans_uxor()
2901 save_gpr(ctx, a->t, dest); in trans_uxor()
2903 ctx->null_cond = do_unit_zero_cond(a->cf, a->d, dest); in trans_uxor()
2911 if (a->cf == 0) { in do_uaddcm()
2912 tcg_r2 = load_gpr(ctx, a->r2); in do_uaddcm()
2913 tmp = dest_gpr(ctx, a->t); in do_uaddcm()
2915 if (a->r1 == 0) { in do_uaddcm()
2920 * Recall that r1 - r2 == r1 + ~r2 + 1. in do_uaddcm()
2921 * Thus r1 + ~r2 == r1 - r2 - 1, in do_uaddcm()
2924 tcg_r1 = load_gpr(ctx, a->r1); in do_uaddcm()
2928 save_gpr(ctx, a->t, tmp); in do_uaddcm()
2929 ctx->null_cond = cond_make_f(); in do_uaddcm()
2934 tcg_r1 = load_gpr(ctx, a->r1); in do_uaddcm()
2935 tcg_r2 = load_gpr(ctx, a->r2); in do_uaddcm()
2938 do_unit_addsub(ctx, a->t, tcg_r1, tmp, a->cf, a->d, is_tc, true); in do_uaddcm()
2965 do_unit_addsub(ctx, a->t, load_gpr(ctx, a->r), tmp, in do_dcor()
2966 a->cf, a->d, false, is_i); in do_dcor()
2986 in1 = load_gpr(ctx, a->r1); in trans_ds()
2987 in2 = load_gpr(ctx, a->r2); in trans_ds()
3008 tcg_gen_add2_i64(dest, cpu_psw_cb_msb, add1, ctx->zero, add2, ctx->zero); in trans_ds()
3010 addc, ctx->zero); in trans_ds()
3013 save_gpr(ctx, a->t, dest); in trans_ds()
3028 if (a->cf) { in trans_ds()
3030 if (cond_need_sv(a->cf >> 1)) { in trans_ds()
3032 } else if (cond_need_cb(a->cf >> 1)) { in trans_ds()
3035 ctx->null_cond = do_cond(ctx, a->cf, false, dest, uv, sv); in trans_ds()
3075 if (a->cf) { in trans_cmpiclr()
3079 tcg_im = tcg_constant_i64(a->i); in trans_cmpiclr()
3080 tcg_r2 = load_gpr(ctx, a->r); in trans_cmpiclr()
3081 do_cmpclr(ctx, a->t, tcg_im, tcg_r2, a->cf, a->d); in trans_cmpiclr()
3091 if (!ctx->is_pa20) { in do_multimedia()
3097 r1 = load_gpr(ctx, a->r1); in do_multimedia()
3098 r2 = load_gpr(ctx, a->r2); in do_multimedia()
3099 dest = dest_gpr(ctx, a->t); in do_multimedia()
3102 save_gpr(ctx, a->t, dest); in do_multimedia()
3112 if (!ctx->is_pa20) { in do_multimedia_sh()
3118 r = load_gpr(ctx, a->r); in do_multimedia_sh()
3119 dest = dest_gpr(ctx, a->t); in do_multimedia_sh()
3121 fn(dest, r, a->i); in do_multimedia_sh()
3122 save_gpr(ctx, a->t, dest); in do_multimedia_sh()
3133 if (!ctx->is_pa20) { in do_multimedia_shadd()
3139 r1 = load_gpr(ctx, a->r1); in do_multimedia_shadd()
3140 r2 = load_gpr(ctx, a->r2); in do_multimedia_shadd()
3141 dest = dest_gpr(ctx, a->t); in do_multimedia_shadd()
3143 fn(dest, r1, r2, tcg_constant_i32(a->sh)); in do_multimedia_shadd()
3144 save_gpr(ctx, a->t, dest); in do_multimedia_shadd()
3268 if (!ctx->is_pa20) { in trans_permh()
3274 r = load_gpr(ctx, a->r1); in trans_permh()
3280 tcg_gen_extract_i64(t0, r, (3 - a->c0) * 16, 16); in trans_permh()
3281 tcg_gen_extract_i64(t1, r, (3 - a->c1) * 16, 16); in trans_permh()
3282 tcg_gen_extract_i64(t2, r, (3 - a->c2) * 16, 16); in trans_permh()
3283 tcg_gen_extract_i64(t3, r, (3 - a->c3) * 16, 16); in trans_permh()
3289 save_gpr(ctx, a->t, t0); in trans_permh()
3295 if (ctx->is_pa20) { in trans_ld()
3300 if (a->t == 0) { in trans_ld()
3303 } else if (a->size > MO_32) { in trans_ld()
3306 return do_load(ctx, a->t, a->b, a->x, a->scale ? a->size : 0, in trans_ld()
3307 a->disp, a->sp, a->m, a->size | MO_TE); in trans_ld()
3312 assert(a->x == 0 && a->scale == 0); in trans_st()
3313 if (!ctx->is_pa20 && a->size > MO_32) { in trans_st()
3316 return do_store(ctx, a->t, a->b, a->disp, a->sp, a->m, a->size | MO_TE); in trans_st()
3321 MemOp mop = MO_TE | MO_ALIGN | a->size; in trans_ldc()
3325 if (!ctx->is_pa20 && a->size > MO_32) { in trans_ldc()
3331 if (a->m) { in trans_ldc()
3336 dest = dest_gpr(ctx, a->t); in trans_ldc()
3339 form_gva(ctx, &addr, &ofs, a->b, a->x, a->scale ? 3 : 0, in trans_ldc()
3340 a->disp, a->sp, a->m, MMU_DISABLED(ctx)); in trans_ldc()
3347 * TODO: HPPA64 relaxes the over-alignment requirement in trans_ldc()
3352 tcg_gen_atomic_xchg_i64(dest, addr, ctx->zero, ctx->mmu_idx, mop); in trans_ldc()
3354 if (a->m) { in trans_ldc()
3355 save_gpr(ctx, a->b, ofs); in trans_ldc()
3357 save_gpr(ctx, a->t, dest); in trans_ldc()
3369 form_gva(ctx, &addr, &ofs, a->b, 0, 0, a->disp, a->sp, a->m, in trans_stby()
3371 val = load_gpr(ctx, a->r); in trans_stby()
3372 if (a->a) { in trans_stby()
3373 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { in trans_stby()
3379 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { in trans_stby()
3385 if (a->m) { in trans_stby()
3387 save_gpr(ctx, a->b, ofs); in trans_stby()
3398 if (!ctx->is_pa20) { in trans_stdby()
3403 form_gva(ctx, &addr, &ofs, a->b, 0, 0, a->disp, a->sp, a->m, in trans_stdby()
3405 val = load_gpr(ctx, a->r); in trans_stdby()
3406 if (a->a) { in trans_stdby()
3407 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { in trans_stdby()
3413 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { in trans_stdby()
3419 if (a->m) { in trans_stdby()
3421 save_gpr(ctx, a->b, ofs); in trans_stdby()
3429 int hold_mmu_idx = ctx->mmu_idx; in trans_lda()
3432 ctx->mmu_idx = ctx->tb_flags & PSW_W ? MMU_ABS_W_IDX : MMU_ABS_IDX; in trans_lda()
3434 ctx->mmu_idx = hold_mmu_idx; in trans_lda()
3440 int hold_mmu_idx = ctx->mmu_idx; in trans_sta()
3443 ctx->mmu_idx = ctx->tb_flags & PSW_W ? MMU_ABS_W_IDX : MMU_ABS_IDX; in trans_sta()
3445 ctx->mmu_idx = hold_mmu_idx; in trans_sta()
3451 TCGv_i64 tcg_rt = dest_gpr(ctx, a->t); in trans_ldil()
3453 tcg_gen_movi_i64(tcg_rt, a->i); in trans_ldil()
3454 save_gpr(ctx, a->t, tcg_rt); in trans_ldil()
3455 ctx->null_cond = cond_make_f(); in trans_ldil()
3461 TCGv_i64 tcg_rt = load_gpr(ctx, a->r); in trans_addil()
3464 tcg_gen_addi_i64(tcg_r1, tcg_rt, a->i); in trans_addil()
3466 ctx->null_cond = cond_make_f(); in trans_addil()
3472 TCGv_i64 tcg_rt = dest_gpr(ctx, a->t); in trans_ldo()
3474 /* Special case rb == 0, for the LDI pseudo-op. in trans_ldo()
3475 The COPY pseudo-op is handled for free within tcg_gen_addi_i64. */ in trans_ldo()
3476 if (a->b == 0) { in trans_ldo()
3477 tcg_gen_movi_i64(tcg_rt, a->i); in trans_ldo()
3479 tcg_gen_addi_i64(tcg_rt, cpu_gr[a->b], a->i); in trans_ldo()
3481 save_gpr(ctx, a->t, tcg_rt); in trans_ldo()
3482 ctx->null_cond = cond_make_f(); in trans_ldo()
3508 if (!ctx->is_pa20 && a->d) { in trans_cmpb()
3512 return do_cmpb(ctx, a->r2, load_gpr(ctx, a->r1), in trans_cmpb()
3513 a->c, a->f, a->d, a->n, a->disp); in trans_cmpb()
3518 if (!ctx->is_pa20 && a->d) { in trans_cmpbi()
3522 return do_cmpb(ctx, a->r, tcg_constant_i64(a->i), in trans_cmpbi()
3523 a->c, a->f, a->d, a->n, a->disp); in trans_cmpbi()
3535 * dropping ZNV, SV, OD in favor of double-word EQ, LT, LE. in do_addb()
3537 if (ctx->tb_flags & PSW_W) { in do_addb()
3573 return do_addb(ctx, a->r2, load_gpr(ctx, a->r1), a->c, a->f, a->n, a->disp); in trans_addb()
3579 return do_addb(ctx, a->r, tcg_constant_i64(a->i), a->c, a->f, a->n, a->disp); in trans_addbi()
3590 tcg_r = load_gpr(ctx, a->r); in trans_bb_sar()
3591 if (a->d) { in trans_bb_sar()
3599 cond = cond_make_ti(a->c ? TCG_COND_GE : TCG_COND_LT, tmp, 0); in trans_bb_sar()
3600 return do_cbranch(ctx, a->disp, a->n, &cond); in trans_bb_sar()
3606 int p = a->p | (a->d ? 0 : 32); in trans_bb_imm()
3609 cond = cond_make_vi(a->c ? TCG_COND_TSTEQ : TCG_COND_TSTNE, in trans_bb_imm()
3610 load_gpr(ctx, a->r), 1ull << (63 - p)); in trans_bb_imm()
3611 return do_cbranch(ctx, a->disp, a->n, &cond); in trans_bb_imm()
3621 dest = dest_gpr(ctx, a->r2); in trans_movb()
3622 if (a->r1 == 0) { in trans_movb()
3625 tcg_gen_mov_i64(dest, cpu_gr[a->r1]); in trans_movb()
3628 /* All MOVB conditions are 32-bit. */ in trans_movb()
3629 cond = do_sed_cond(ctx, a->c, false, dest); in trans_movb()
3630 return do_cbranch(ctx, a->disp, a->n, &cond); in trans_movb()
3640 dest = dest_gpr(ctx, a->r); in trans_movbi()
3641 tcg_gen_movi_i64(dest, a->i); in trans_movbi()
3643 /* All MOVBI conditions are 32-bit. */ in trans_movbi()
3644 cond = do_sed_cond(ctx, a->c, false, dest); in trans_movbi()
3645 return do_cbranch(ctx, a->disp, a->n, &cond); in trans_movbi()
3652 if (!ctx->is_pa20 && a->d) { in trans_shrp_sar()
3655 if (a->c) { in trans_shrp_sar()
3659 dest = dest_gpr(ctx, a->t); in trans_shrp_sar()
3660 src2 = load_gpr(ctx, a->r2); in trans_shrp_sar()
3661 if (a->r1 == 0) { in trans_shrp_sar()
3662 if (a->d) { in trans_shrp_sar()
3671 } else if (a->r1 == a->r2) { in trans_shrp_sar()
3672 if (a->d) { in trans_shrp_sar()
3685 TCGv_i64 src1 = load_gpr(ctx, a->r1); in trans_shrp_sar()
3687 if (a->d) { in trans_shrp_sar()
3705 save_gpr(ctx, a->t, dest); in trans_shrp_sar()
3708 ctx->null_cond = do_sed_cond(ctx, a->c, a->d, dest); in trans_shrp_sar()
3717 if (!ctx->is_pa20 && a->d) { in trans_shrp_imm()
3720 if (a->c) { in trans_shrp_imm()
3724 width = a->d ? 64 : 32; in trans_shrp_imm()
3725 sa = width - 1 - a->cpos; in trans_shrp_imm()
3727 dest = dest_gpr(ctx, a->t); in trans_shrp_imm()
3728 t2 = load_gpr(ctx, a->r2); in trans_shrp_imm()
3729 if (a->r1 == 0) { in trans_shrp_imm()
3730 tcg_gen_extract_i64(dest, t2, sa, width - sa); in trans_shrp_imm()
3732 tcg_gen_extract2_i64(dest, t2, cpu_gr[a->r1], sa); in trans_shrp_imm()
3734 assert(!a->d); in trans_shrp_imm()
3735 if (a->r1 == a->r2) { in trans_shrp_imm()
3741 tcg_gen_concat32_i64(dest, t2, cpu_gr[a->r1]); in trans_shrp_imm()
3745 save_gpr(ctx, a->t, dest); in trans_shrp_imm()
3748 ctx->null_cond = do_sed_cond(ctx, a->c, a->d, dest); in trans_shrp_imm()
3754 unsigned widthm1 = a->d ? 63 : 31; in trans_extr_sar()
3757 if (!ctx->is_pa20 && a->d) { in trans_extr_sar()
3760 if (a->c) { in trans_extr_sar()
3764 dest = dest_gpr(ctx, a->t); in trans_extr_sar()
3765 src = load_gpr(ctx, a->r); in trans_extr_sar()
3768 /* Recall that SAR is using big-endian bit numbering. */ in trans_extr_sar()
3772 if (a->se) { in trans_extr_sar()
3773 if (!a->d) { in trans_extr_sar()
3778 tcg_gen_sextract_i64(dest, dest, 0, a->len); in trans_extr_sar()
3780 if (!a->d) { in trans_extr_sar()
3785 tcg_gen_extract_i64(dest, dest, 0, a->len); in trans_extr_sar()
3787 save_gpr(ctx, a->t, dest); in trans_extr_sar()
3790 ctx->null_cond = do_sed_cond(ctx, a->c, a->d, dest); in trans_extr_sar()
3799 if (!ctx->is_pa20 && a->d) { in trans_extr_imm()
3802 if (a->c) { in trans_extr_imm()
3806 len = a->len; in trans_extr_imm()
3807 width = a->d ? 64 : 32; in trans_extr_imm()
3808 cpos = width - 1 - a->pos; in trans_extr_imm()
3810 len = width - cpos; in trans_extr_imm()
3813 dest = dest_gpr(ctx, a->t); in trans_extr_imm()
3814 src = load_gpr(ctx, a->r); in trans_extr_imm()
3815 if (a->se) { in trans_extr_imm()
3820 save_gpr(ctx, a->t, dest); in trans_extr_imm()
3823 ctx->null_cond = do_sed_cond(ctx, a->c, a->d, dest); in trans_extr_imm()
3833 if (!ctx->is_pa20 && a->d) { in trans_depi_imm()
3836 if (a->c) { in trans_depi_imm()
3840 len = a->len; in trans_depi_imm()
3841 width = a->d ? 64 : 32; in trans_depi_imm()
3842 if (a->cpos + len > width) { in trans_depi_imm()
3843 len = width - a->cpos; in trans_depi_imm()
3846 dest = dest_gpr(ctx, a->t); in trans_depi_imm()
3847 mask0 = deposit64(0, a->cpos, len, a->i); in trans_depi_imm()
3848 mask1 = deposit64(-1, a->cpos, len, a->i); in trans_depi_imm()
3850 if (a->nz) { in trans_depi_imm()
3851 TCGv_i64 src = load_gpr(ctx, a->t); in trans_depi_imm()
3857 save_gpr(ctx, a->t, dest); in trans_depi_imm()
3860 ctx->null_cond = do_sed_cond(ctx, a->c, a->d, dest); in trans_depi_imm()
3866 unsigned rs = a->nz ? a->t : 0; in trans_dep_imm()
3870 if (!ctx->is_pa20 && a->d) { in trans_dep_imm()
3873 if (a->c) { in trans_dep_imm()
3877 len = a->len; in trans_dep_imm()
3878 width = a->d ? 64 : 32; in trans_dep_imm()
3879 if (a->cpos + len > width) { in trans_dep_imm()
3880 len = width - a->cpos; in trans_dep_imm()
3883 dest = dest_gpr(ctx, a->t); in trans_dep_imm()
3884 val = load_gpr(ctx, a->r); in trans_dep_imm()
3886 tcg_gen_deposit_z_i64(dest, val, a->cpos, len); in trans_dep_imm()
3888 tcg_gen_deposit_i64(dest, cpu_gr[rs], val, a->cpos, len); in trans_dep_imm()
3890 save_gpr(ctx, a->t, dest); in trans_dep_imm()
3893 ctx->null_cond = do_sed_cond(ctx, a->c, a->d, dest); in trans_dep_imm()
3903 uint64_t msb = 1ULL << (len - 1); in do_dep_sar()
3909 /* Convert big-endian bit numbering in SAR to left-shift. */ in do_dep_sar()
3914 tcg_gen_movi_i64(mask, msb + (msb - 1)); in do_dep_sar()
3927 ctx->null_cond = do_sed_cond(ctx, c, d, dest); in do_dep_sar()
3933 if (!ctx->is_pa20 && a->d) { in trans_dep_sar()
3936 if (a->c) { in trans_dep_sar()
3939 return do_dep_sar(ctx, a->t, a->c, a->d, a->nz, a->len, in trans_dep_sar()
3940 load_gpr(ctx, a->r)); in trans_dep_sar()
3945 if (!ctx->is_pa20 && a->d) { in trans_depi_sar()
3948 if (a->c) { in trans_depi_sar()
3951 return do_dep_sar(ctx, a->t, a->c, a->d, a->nz, a->len, in trans_depi_sar()
3952 tcg_constant_i64(a->i)); in trans_depi_sar()
3958 ctx->iaq_j.space = tcg_temp_new_i64(); in trans_be()
3959 load_spr(ctx, ctx->iaq_j.space, a->sp); in trans_be()
3962 ctx->iaq_j.base = tcg_temp_new_i64(); in trans_be()
3963 ctx->iaq_j.disp = 0; in trans_be()
3965 tcg_gen_addi_i64(ctx->iaq_j.base, load_gpr(ctx, a->b), a->disp); in trans_be()
3966 ctx->iaq_j.base = do_ibranch_priv(ctx, ctx->iaq_j.base); in trans_be()
3968 return do_ibranch(ctx, a->l, true, a->n); in trans_be()
3973 return do_dbranch(ctx, a->disp, a->l, a->n); in trans_bl()
3978 int64_t disp = a->disp; in trans_b_gate()
3982 if (ctx->psw_xb & PSW_B) { in trans_b_gate()
3989 if (ctx->privilege == 0) { in trans_b_gate()
3991 } else if (!(ctx->tb_flags & PSW_C)) { in trans_b_gate()
3993 disp -= ctx->privilege; in trans_b_gate()
3998 copy_iaoq_entry(ctx, off, &ctx->iaq_f); in trans_b_gate()
4001 ctx->iaq_j.base = off; in trans_b_gate()
4002 ctx->iaq_j.disp = disp + 8; in trans_b_gate()
4007 if (a->l) { in trans_b_gate()
4008 TCGv_i64 tmp = dest_gpr(ctx, a->l); in trans_b_gate()
4009 if (ctx->privilege < 3) { in trans_b_gate()
4010 tcg_gen_andi_i64(tmp, tmp, -4); in trans_b_gate()
4012 tcg_gen_ori_i64(tmp, tmp, ctx->privilege); in trans_b_gate()
4013 save_gpr(ctx, a->l, tmp); in trans_b_gate()
4017 return do_ibranch(ctx, 0, false, a->n); in trans_b_gate()
4019 return do_dbranch(ctx, disp, 0, a->n); in trans_b_gate()
4024 if (a->x) { in trans_blr()
4025 DisasIAQE next = iaqe_incr(&ctx->iaq_f, 8); in trans_blr()
4031 tcg_gen_shli_i64(t1, load_gpr(ctx, a->x), 3); in trans_blr()
4034 ctx->iaq_j = iaqe_next_absv(ctx, t0); in trans_blr()
4035 return do_ibranch(ctx, a->l, false, a->n); in trans_blr()
4038 return do_dbranch(ctx, 0, a->l, a->n); in trans_blr()
4046 if (a->x == 0) { in trans_bv()
4047 dest = load_gpr(ctx, a->b); in trans_bv()
4050 tcg_gen_shli_i64(dest, load_gpr(ctx, a->x), 3); in trans_bv()
4051 tcg_gen_add_i64(dest, dest, load_gpr(ctx, a->b)); in trans_bv()
4054 ctx->iaq_j = iaqe_next_absv(ctx, dest); in trans_bv()
4056 return do_ibranch(ctx, 0, false, a->n); in trans_bv()
4061 TCGv_i64 b = load_gpr(ctx, a->b); in trans_bve()
4064 ctx->iaq_j.space = space_select(ctx, 0, b); in trans_bve()
4066 ctx->iaq_j.base = do_ibranch_priv(ctx, b); in trans_bve()
4067 ctx->iaq_j.disp = 0; in trans_bve()
4069 return do_ibranch(ctx, a->l, false, a->n); in trans_bve()
4075 return ctx->is_pa20; in trans_nopbts()
4091 if (ctx->is_pa20) { in trans_fid_f()
4092 ret = 0x13080000000000ULL; /* PA8700 (PCX-W2) */ in trans_fid_f()
4094 ret = 0x0f080000000000ULL; /* PA7300LC (PCX-L2) */ in trans_fid_f()
4104 return do_fop_wew(ctx, a->t, a->r, gen_fcpy_f); in trans_fcpy_f()
4114 return do_fop_ded(ctx, a->t, a->r, gen_fcpy_d); in trans_fcpy_d()
4124 return do_fop_wew(ctx, a->t, a->r, gen_fabs_f); in trans_fabs_f()
4134 return do_fop_ded(ctx, a->t, a->r, gen_fabs_d); in trans_fabs_d()
4139 return do_fop_wew(ctx, a->t, a->r, gen_helper_fsqrt_s); in trans_fsqrt_f()
4144 return do_fop_ded(ctx, a->t, a->r, gen_helper_fsqrt_d); in trans_fsqrt_d()
4149 return do_fop_wew(ctx, a->t, a->r, gen_helper_frnd_s); in trans_frnd_f()
4154 return do_fop_ded(ctx, a->t, a->r, gen_helper_frnd_d); in trans_frnd_d()
4164 return do_fop_wew(ctx, a->t, a->r, gen_fneg_f); in trans_fneg_f()
4174 return do_fop_ded(ctx, a->t, a->r, gen_fneg_d); in trans_fneg_d()
4184 return do_fop_wew(ctx, a->t, a->r, gen_fnegabs_f); in trans_fnegabs_f()
4194 return do_fop_ded(ctx, a->t, a->r, gen_fnegabs_d); in trans_fnegabs_d()
4203 return do_fop_wed(ctx, a->t, a->r, gen_helper_fcnv_d_s); in trans_fcnv_d_f()
4208 return do_fop_dew(ctx, a->t, a->r, gen_helper_fcnv_s_d); in trans_fcnv_f_d()
4213 return do_fop_wew(ctx, a->t, a->r, gen_helper_fcnv_w_s); in trans_fcnv_w_f()
4218 return do_fop_wed(ctx, a->t, a->r, gen_helper_fcnv_dw_s); in trans_fcnv_q_f()
4223 return do_fop_dew(ctx, a->t, a->r, gen_helper_fcnv_w_d); in trans_fcnv_w_d()
4228 return do_fop_ded(ctx, a->t, a->r, gen_helper_fcnv_dw_d); in trans_fcnv_q_d()
4233 return do_fop_wew(ctx, a->t, a->r, gen_helper_fcnv_s_w); in trans_fcnv_f_w()
4238 return do_fop_wed(ctx, a->t, a->r, gen_helper_fcnv_d_w); in trans_fcnv_d_w()
4243 return do_fop_dew(ctx, a->t, a->r, gen_helper_fcnv_s_dw); in trans_fcnv_f_q()
4248 return do_fop_ded(ctx, a->t, a->r, gen_helper_fcnv_d_dw); in trans_fcnv_d_q()
4253 return do_fop_wew(ctx, a->t, a->r, gen_helper_fcnv_t_s_w); in trans_fcnv_t_f_w()
4258 return do_fop_wed(ctx, a->t, a->r, gen_helper_fcnv_t_d_w); in trans_fcnv_t_d_w()
4263 return do_fop_dew(ctx, a->t, a->r, gen_helper_fcnv_t_s_dw); in trans_fcnv_t_f_q()
4268 return do_fop_ded(ctx, a->t, a->r, gen_helper_fcnv_t_d_dw); in trans_fcnv_t_d_q()
4273 return do_fop_wew(ctx, a->t, a->r, gen_helper_fcnv_uw_s); in trans_fcnv_uw_f()
4278 return do_fop_wed(ctx, a->t, a->r, gen_helper_fcnv_udw_s); in trans_fcnv_uq_f()
4283 return do_fop_dew(ctx, a->t, a->r, gen_helper_fcnv_uw_d); in trans_fcnv_uw_d()
4288 return do_fop_ded(ctx, a->t, a->r, gen_helper_fcnv_udw_d); in trans_fcnv_uq_d()
4293 return do_fop_wew(ctx, a->t, a->r, gen_helper_fcnv_s_uw); in trans_fcnv_f_uw()
4298 return do_fop_wed(ctx, a->t, a->r, gen_helper_fcnv_d_uw); in trans_fcnv_d_uw()
4303 return do_fop_dew(ctx, a->t, a->r, gen_helper_fcnv_s_udw); in trans_fcnv_f_uq()
4308 return do_fop_ded(ctx, a->t, a->r, gen_helper_fcnv_d_udw); in trans_fcnv_d_uq()
4313 return do_fop_wew(ctx, a->t, a->r, gen_helper_fcnv_t_s_uw); in trans_fcnv_t_f_uw()
4318 return do_fop_wed(ctx, a->t, a->r, gen_helper_fcnv_t_d_uw); in trans_fcnv_t_d_uw()
4323 return do_fop_dew(ctx, a->t, a->r, gen_helper_fcnv_t_s_udw); in trans_fcnv_t_f_uq()
4328 return do_fop_ded(ctx, a->t, a->r, gen_helper_fcnv_t_d_udw); in trans_fcnv_t_d_uq()
4341 ta = load_frw0_i32(a->r1); in trans_fcmp_f()
4342 tb = load_frw0_i32(a->r2); in trans_fcmp_f()
4343 ty = tcg_constant_i32(a->y); in trans_fcmp_f()
4344 tc = tcg_constant_i32(a->c); in trans_fcmp_f()
4358 ta = load_frd0(a->r1); in trans_fcmp_d()
4359 tb = load_frd0(a->r2); in trans_fcmp_d()
4360 ty = tcg_constant_i32(a->y); in trans_fcmp_d()
4361 tc = tcg_constant_i32(a->c); in trans_fcmp_d()
4379 if (a->y == 1) { in trans_ftest()
4380 switch (a->c) { in trans_ftest()
4410 unsigned cbit = (a->y ^ 1) - 1; in trans_ftest()
4414 ctx->null_cond = cond_make_ti(tc, t, mask); in trans_ftest()
4424 return do_fop_weww(ctx, a->t, a->r1, a->r2, gen_helper_fadd_s); in trans_fadd_f()
4429 return do_fop_dedd(ctx, a->t, a->r1, a->r2, gen_helper_fadd_d); in trans_fadd_d()
4434 return do_fop_weww(ctx, a->t, a->r1, a->r2, gen_helper_fsub_s); in trans_fsub_f()
4439 return do_fop_dedd(ctx, a->t, a->r1, a->r2, gen_helper_fsub_d); in trans_fsub_d()
4444 return do_fop_weww(ctx, a->t, a->r1, a->r2, gen_helper_fmpy_s); in trans_fmpy_f()
4449 return do_fop_dedd(ctx, a->t, a->r1, a->r2, gen_helper_fmpy_d); in trans_fmpy_d()
4454 return do_fop_weww(ctx, a->t, a->r1, a->r2, gen_helper_fdiv_s); in trans_fdiv_f()
4459 return do_fop_dedd(ctx, a->t, a->r1, a->r2, gen_helper_fdiv_d); in trans_fdiv_d()
4468 x = load_frw0_i64(a->r1); in trans_xmpyu()
4469 y = load_frw0_i64(a->r2); in trans_xmpyu()
4471 save_frd(a->t, x); in trans_xmpyu()
4476 /* Convert the fmpyadd single-precision register encodings to standard. */
4484 int tm = fmpyadd_s_reg(a->tm); in do_fmpyadd_s()
4485 int ra = fmpyadd_s_reg(a->ra); in do_fmpyadd_s()
4486 int ta = fmpyadd_s_reg(a->ta); in do_fmpyadd_s()
4487 int rm2 = fmpyadd_s_reg(a->rm2); in do_fmpyadd_s()
4488 int rm1 = fmpyadd_s_reg(a->rm1); in do_fmpyadd_s()
4513 do_fop_dedd(ctx, a->tm, a->rm1, a->rm2, gen_helper_fmpy_d); in do_fmpyadd_d()
4514 do_fop_dedd(ctx, a->ta, a->ta, a->ra, in do_fmpyadd_d()
4535 x = load_frw0_i32(a->rm1); in trans_fmpyfadd_f()
4536 y = load_frw0_i32(a->rm2); in trans_fmpyfadd_f()
4537 z = load_frw0_i32(a->ra3); in trans_fmpyfadd_f()
4539 if (a->neg) { in trans_fmpyfadd_f()
4545 save_frw_i32(a->t, x); in trans_fmpyfadd_f()
4554 x = load_frd0(a->rm1); in trans_fmpyfadd_d()
4555 y = load_frd0(a->rm2); in trans_fmpyfadd_d()
4556 z = load_frd0(a->ra3); in trans_fmpyfadd_d()
4558 if (a->neg) { in trans_fmpyfadd_d()
4564 save_frd(a->t, x); in trans_fmpyfadd_d()
4568 /* Emulate PDC BTLB, called by SeaBIOS-hppa */
4579 /* Print char in %r26 to first serial console, used by SeaBIOS-hppa */
4592 return !ctx->is_pa20 && do_getshadowregs(ctx); in trans_diag_getshadowregs_pa1()
4597 return ctx->is_pa20 && do_getshadowregs(ctx); in trans_diag_getshadowregs_pa2()
4602 return !ctx->is_pa20 && do_putshadowregs(ctx); in trans_diag_putshadowregs_pa1()
4607 return ctx->is_pa20 && do_putshadowregs(ctx); in trans_diag_putshadowregs_pa2()
4613 qemu_log_mask(LOG_UNIMP, "DIAG opcode 0x%04x ignored\n", a->i); in trans_diag_unimp()
4623 ctx->cs = cs; in hppa_tr_init_disas_context()
4624 ctx->tb_flags = ctx->base.tb->flags; in hppa_tr_init_disas_context()
4625 ctx->is_pa20 = hppa_is_pa20(cpu_env(cs)); in hppa_tr_init_disas_context()
4626 ctx->psw_xb = ctx->tb_flags & (PSW_X | PSW_B); in hppa_tr_init_disas_context()
4629 ctx->privilege = PRIV_USER; in hppa_tr_init_disas_context()
4630 ctx->mmu_idx = MMU_USER_IDX; in hppa_tr_init_disas_context()
4631 ctx->unalign = (ctx->tb_flags & TB_FLAG_UNALIGN ? MO_UNALN : MO_ALIGN); in hppa_tr_init_disas_context()
4633 ctx->privilege = (ctx->tb_flags >> TB_FLAG_PRIV_SHIFT) & 3; in hppa_tr_init_disas_context()
4634 ctx->mmu_idx = (ctx->tb_flags & PSW_D in hppa_tr_init_disas_context()
4635 ? PRIV_P_TO_MMU_IDX(ctx->privilege, ctx->tb_flags & PSW_P) in hppa_tr_init_disas_context()
4636 : ctx->tb_flags & PSW_W ? MMU_ABS_W_IDX : MMU_ABS_IDX); in hppa_tr_init_disas_context()
4639 cs_base = ctx->base.tb->cs_base; in hppa_tr_init_disas_context()
4640 ctx->iaoq_first = ctx->base.pc_first + ctx->privilege; in hppa_tr_init_disas_context()
4643 ctx->iaq_b.space = cpu_iasq_b; in hppa_tr_init_disas_context()
4644 ctx->iaq_b.base = cpu_iaoq_b; in hppa_tr_init_disas_context()
4646 ctx->iaq_b.base = cpu_iaoq_b; in hppa_tr_init_disas_context()
4648 uint64_t iaoq_f_pgofs = ctx->iaoq_first & ~TARGET_PAGE_MASK; in hppa_tr_init_disas_context()
4650 ctx->iaq_b.disp = iaoq_b_pgofs - iaoq_f_pgofs; in hppa_tr_init_disas_context()
4653 ctx->zero = tcg_constant_i64(0); in hppa_tr_init_disas_context()
4656 bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; in hppa_tr_init_disas_context()
4657 ctx->base.max_insns = MIN(ctx->base.max_insns, bound); in hppa_tr_init_disas_context()
4664 /* Seed the nullification status from PSW[N], as saved in TB->FLAGS. */ in hppa_tr_tb_start()
4665 ctx->null_cond = cond_make_f(); in hppa_tr_tb_start()
4666 ctx->psw_n_nonzero = false; in hppa_tr_tb_start()
4667 if (ctx->tb_flags & PSW_N) { in hppa_tr_tb_start()
4668 ctx->null_cond.c = TCG_COND_ALWAYS; in hppa_tr_tb_start()
4669 ctx->psw_n_nonzero = true; in hppa_tr_tb_start()
4671 ctx->null_lab = NULL; in hppa_tr_tb_start()
4680 tcg_debug_assert(!iaqe_variable(&ctx->iaq_f)); in hppa_tr_insn_start()
4682 iaoq_f = ctx->iaoq_first + ctx->iaq_f.disp; in hppa_tr_insn_start()
4683 if (iaqe_variable(&ctx->iaq_b)) { in hppa_tr_insn_start()
4686 iaoq_b = ctx->iaoq_first + ctx->iaq_b.disp; in hppa_tr_insn_start()
4687 diff = iaoq_b - iaoq_f; in hppa_tr_insn_start()
4688 /* Direct branches can only produce a 24-bit displacement. */ in hppa_tr_insn_start()
4694 ctx->insn_start_updated = false; in hppa_tr_insn_start()
4705 if (ctx->base.pc_next < TARGET_PAGE_SIZE) { in hppa_tr_translate_insn()
4707 ret = ctx->base.is_jmp; in hppa_tr_translate_insn()
4714 uint32_t insn = translator_ldl(env, &ctx->base, ctx->base.pc_next); in hppa_tr_translate_insn()
4720 ctx->iaq_n = NULL; in hppa_tr_translate_insn()
4721 memset(&ctx->iaq_j, 0, sizeof(ctx->iaq_j)); in hppa_tr_translate_insn()
4722 ctx->psw_b_next = false; in hppa_tr_translate_insn()
4724 if (unlikely(ctx->null_cond.c == TCG_COND_ALWAYS)) { in hppa_tr_translate_insn()
4725 ctx->null_cond.c = TCG_COND_NEVER; in hppa_tr_translate_insn()
4728 ctx->insn = insn; in hppa_tr_translate_insn()
4732 ret = ctx->base.is_jmp; in hppa_tr_translate_insn()
4733 assert(ctx->null_lab == NULL); in hppa_tr_translate_insn()
4737 set_psw_xb(ctx, ctx->psw_b_next ? PSW_B : 0); in hppa_tr_translate_insn()
4742 ctx->base.pc_next += 4; in hppa_tr_translate_insn()
4747 if (iaqe_variable(&ctx->iaq_b) in hppa_tr_translate_insn()
4748 || ctx->iaq_b.disp != ctx->iaq_f.disp + 4) { in hppa_tr_translate_insn()
4749 ctx->base.is_jmp = DISAS_IAQ_N_STALE; in hppa_tr_translate_insn()
4757 ctx->iaq_f.disp = ctx->iaq_b.disp; in hppa_tr_translate_insn()
4758 if (!ctx->iaq_n) { in hppa_tr_translate_insn()
4759 ctx->iaq_b.disp += 4; in hppa_tr_translate_insn()
4766 if (ctx->iaq_n->base) { in hppa_tr_translate_insn()
4767 copy_iaoq_entry(ctx, cpu_iaoq_b, ctx->iaq_n); in hppa_tr_translate_insn()
4768 ctx->iaq_b.base = cpu_iaoq_b; in hppa_tr_translate_insn()
4769 ctx->iaq_b.disp = 0; in hppa_tr_translate_insn()
4771 ctx->iaq_b.disp = ctx->iaq_n->disp; in hppa_tr_translate_insn()
4773 if (ctx->iaq_n->space) { in hppa_tr_translate_insn()
4774 tcg_gen_mov_i64(cpu_iasq_b, ctx->iaq_n->space); in hppa_tr_translate_insn()
4775 ctx->iaq_b.space = cpu_iasq_b; in hppa_tr_translate_insn()
4782 DisasJumpType is_jmp = ctx->base.is_jmp; in hppa_tr_tb_stop()
4784 DisasIAQE *f = &ctx->iaq_b; in hppa_tr_tb_stop()
4785 DisasIAQE *b = ctx->iaq_n; in hppa_tr_tb_stop()
4792 f = &ctx->iaq_f; in hppa_tr_tb_stop()
4793 b = &ctx->iaq_b; in hppa_tr_tb_stop()
4797 && (ctx->null_cond.c == TCG_COND_NEVER in hppa_tr_tb_stop()
4798 || ctx->null_cond.c == TCG_COND_ALWAYS)) { in hppa_tr_tb_stop()
4799 nullify_set(ctx, ctx->null_cond.c == TCG_COND_ALWAYS); in hppa_tr_tb_stop()
4822 for (DisasDelayException *e = ctx->delay_excp_list; e ; e = e->next) { in hppa_tr_tb_stop()
4823 gen_set_label(e->lab); in hppa_tr_tb_stop()
4824 if (e->set_n >= 0) { in hppa_tr_tb_stop()
4825 tcg_gen_movi_i64(cpu_psw_n, e->set_n); in hppa_tr_tb_stop()
4827 if (e->set_iir) { in hppa_tr_tb_stop()
4828 tcg_gen_st_i64(tcg_constant_i64(e->insn), tcg_env, in hppa_tr_tb_stop()
4831 install_iaq_entries(ctx, &e->iaq_f, &e->iaq_b); in hppa_tr_tb_stop()
4832 gen_excp_1(e->excp); in hppa_tr_tb_stop()
4840 target_ulong pc = dcbase->pc_first; in hppa_tr_disas_log()
4847 fprintf(logfile, "IN:\n0x000000b0: light-weight-syscall\n"); in hppa_tr_disas_log()
4850 fprintf(logfile, "IN:\n0x000000e0: set-thread-pointer-syscall\n"); in hppa_tr_disas_log()