Lines Matching full:semantics

22         This has all the instruction and packet semantics
25         *.idef                  Instruction semantics definition
63     Instruction semantics  "{ RdV=RsV+RtV;}"
101 when the packet commits (see "Packet Semantics" below).
106     C semantics (aka short code)
117 The instruction semantics C code relies heavily on macros.  In cases where the
118 C semantics are specified only with macros, we can override the default with
119 the short semantics option and #define the macros to generate TCG code.  One
123     Instruction semantics  "{ fEA_REG(RsV); fLOAD_LOCKED(1,4,u,EA,RdV) }"
159 the instruction.  This makes it easy to override the instruction semantics with
187 semantics can be short-circuited.  If not, we initialize the result register for each
190 In addition to instruction semantics, we use a generator to create the decode
214 The Hexagon arch lib relies heavily on macros for the instruction semantics.
226     gen_start_packet - initialize the data structures for packet semantics
243 *** Packet Semantics ***
245 VLIW packet semantics differ from serial semantics in that all input operands
251 Packet semantics dictate that we defer any changes of state until the entire