Lines Matching +full:hot +full:- +full:plug
41 PCIE_DPRINTF("%s:%x "fmt, (dev)->name, (dev)->devfn, ## __VA_ARGS__)
73 uint8_t *exp_cap = dev->config + dev->exp.exp_cap; in pcie_cap_v1_fill()
74 uint8_t *cmask = dev->cmask + dev->exp.exp_cap; in pcie_cap_v1_fill()
83 * table 7-12: in pcie_cap_v1_fill()
91 if (dev->cap_present & QEMU_PCIE_EXT_TAG) { in pcie_cap_v1_fill()
166 uint8_t *exp_cap = dev->config + dev->exp.exp_cap; in pcie_cap_fill_link_ep_usp()
184 uint8_t *exp_cap = dev->config + dev->exp.exp_cap; in pcie_cap_fill_slot_lnk()
196 if (s->width > QEMU_PCI_EXP_LNK_X1 || in pcie_cap_fill_slot_lnk()
197 s->speed > QEMU_PCI_EXP_LNK_2_5GT) { in pcie_cap_fill_slot_lnk()
202 if (s->speed > QEMU_PCI_EXP_LNK_2_5GT) { in pcie_cap_fill_slot_lnk()
204 * Hot-plug capable downstream ports and downstream ports supporting in pcie_cap_fill_slot_lnk()
207 * we also hardwire to 1b here. 2.5GT/s hot-plug slots should also in pcie_cap_fill_slot_lnk()
215 pcie_cap_fill_lnk(exp_cap, s->width, s->speed); in pcie_cap_fill_slot_lnk()
233 dev->exp.exp_cap = pos; in pcie_cap_init()
234 exp_cap = dev->config + pos; in pcie_cap_init()
246 pci_set_word(dev->wmask + pos + PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_EETLPPB); in pcie_cap_init()
248 if (dev->cap_present & QEMU_PCIE_EXTCAP_INIT) { in pcie_cap_init()
249 /* read-only to behave like a 'NULL' Extended Capability Header */ in pcie_cap_init()
250 pci_set_long(dev->wmask + PCI_CONFIG_SPACE_SIZE, 0); in pcie_cap_init()
271 dev->exp.exp_cap = pos; in pcie_cap_v1_init()
330 uint32_t pos = dev->exp.exp_cap; in pcie_cap_get_type()
332 return (pci_get_word(dev->config + pos + PCI_EXP_FLAGS) & in pcie_cap_get_type()
338 uint32_t pos = dev->exp.exp_cap; in pcie_cap_get_version()
340 return pci_get_word(dev->config + pos + PCI_EXP_FLAGS) & PCI_EXP_FLAGS_VERS; in pcie_cap_get_version()
343 /* MSI/MSI-X */
348 uint8_t *exp_cap = dev->config + dev->exp.exp_cap; in pcie_cap_flags_set_vector()
357 return (pci_get_word(dev->config + dev->exp.exp_cap + PCI_EXP_FLAGS) & in pcie_cap_flags_get_vector()
363 uint32_t pos = dev->exp.exp_cap; in pcie_cap_deverr_init()
364 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP, in pcie_cap_deverr_init()
366 pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL, in pcie_cap_deverr_init()
369 pci_long_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_DEVSTA, in pcie_cap_deverr_init()
376 uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL; in pcie_cap_deverr_reset()
384 uint32_t pos = dev->exp.exp_cap; in pcie_cap_lnkctl_init()
385 pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_LNKCTL, in pcie_cap_lnkctl_init()
391 uint8_t *lnkctl = dev->config + dev->exp.exp_cap + PCI_EXP_LNKCTL; in pcie_cap_lnkctl_reset()
398 uint32_t pos = dev->exp.exp_cap; in hotplug_event_update_event_status()
399 uint8_t *exp_cap = dev->config + pos; in hotplug_event_update_event_status()
403 dev->exp.hpev_notified = (sltctl & PCI_EXP_SLTCTL_HPIE) && in hotplug_event_update_event_status()
409 bool prev = dev->exp.hpev_notified; in hotplug_event_notify()
413 if (prev == dev->exp.hpev_notified) { in hotplug_event_notify()
420 * The Port may optionally send an MSI when there are hot-plug events that in hotplug_event_notify()
427 } else if (pci_intx(dev) != -1) { in hotplug_event_notify()
428 pci_set_irq(dev, dev->exp.hpev_notified); in hotplug_event_notify()
435 if (!msix_enabled(dev) && !msi_enabled(dev) && pci_intx(dev) != -1 && in hotplug_event_clear()
436 !dev->exp.hpev_notified) { in hotplug_event_clear()
443 uint8_t *exp_cap = dev->config + dev->exp.exp_cap; in pcie_cap_slot_enable_power()
461 uint8_t *exp_cap = hotplug_dev->config + hotplug_dev->exp.exp_cap; in pcie_cap_update_power()
477 * A PCI Express Hot-Plug Event has occurred, so update slot status register
480 * 6.7.3 PCI Express Hot-Plug Events
481 * 6.7.3.4 Software Notification of Hot-Plug Events
485 /* Minor optimization: if nothing changed - no event is needed. */ in pcie_cap_slot_event()
486 if (pci_word_test_and_set_mask(dev->config + dev->exp.exp_cap + in pcie_cap_slot_event()
496 uint8_t *exp_cap = hotplug_dev->config + hotplug_dev->exp.exp_cap; in pcie_cap_slot_plug_common()
512 uint8_t *exp_cap = hotplug_pdev->config + hotplug_pdev->exp.exp_cap; in pcie_cap_slot_pre_plug_cb()
515 /* Check if hot-plug is disabled on the slot */ in pcie_cap_slot_pre_plug_cb()
516 if (dev->hotplugged && (sltcap & PCI_EXP_SLTCAP_HPC) == 0) { in pcie_cap_slot_pre_plug_cb()
517 error_setg(errp, "Hot-plug failed: unsupported by the port device '%s'", in pcie_cap_slot_pre_plug_cb()
518 DEVICE(hotplug_pdev)->id); in pcie_cap_slot_pre_plug_cb()
529 uint8_t *exp_cap = hotplug_pdev->config + hotplug_pdev->exp.exp_cap; in pcie_cap_slot_plug_cb()
541 if (!dev->hotplugged) { in pcie_cap_slot_plug_cb()
544 if (pci_dev->cap_present & QEMU_PCIE_LNKSTA_DLLLA || in pcie_cap_slot_plug_cb()
553 /* To enable multifunction hot-plug, we just ensure the function in pcie_cap_slot_plug_cb()
560 if (pci_dev->cap_present & QEMU_PCIE_LNKSTA_DLLLA || in pcie_cap_slot_plug_cb()
581 if (dev->partially_hotplugged) { in pcie_unplug_device()
582 dev->qdev.pending_deleted_event = false; in pcie_unplug_device()
592 uint8_t *exp_cap = dev->config + dev->exp.exp_cap; in pcie_cap_slot_do_unplug()
599 if (dev->cap_present & QEMU_PCIE_LNKSTA_DLLLA || in pcie_cap_slot_do_unplug()
615 uint8_t *exp_cap = hotplug_pdev->config + hotplug_pdev->exp.exp_cap; in pcie_cap_slot_unplug_request_cb()
619 /* Check if hot-unplug is disabled on the slot */ in pcie_cap_slot_unplug_request_cb()
621 error_setg(errp, "Hot-unplug failed: " in pcie_cap_slot_unplug_request_cb()
623 DEVICE(hotplug_pdev)->id); in pcie_cap_slot_unplug_request_cb()
634 error_setg(errp, "Hot-unplug failed: " in pcie_cap_slot_unplug_request_cb()
639 dev->pending_deleted_event = true; in pcie_cap_slot_unplug_request_cb()
640 dev->pending_deleted_expires_ms = in pcie_cap_slot_unplug_request_cb()
643 /* In case user cancel the operation of multi-function hot-add, in pcie_cap_slot_unplug_request_cb()
647 if (pci_dev->devfn && in pcie_cap_slot_unplug_request_cb()
648 !bus->devices[0]) { in pcie_cap_slot_unplug_request_cb()
655 /* slot is powered off -> unplug without round-trip to the guest */ in pcie_cap_slot_unplug_request_cb()
670 uint32_t pos = dev->exp.exp_cap; in pcie_cap_slot_init()
672 pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_FLAGS, in pcie_cap_slot_init()
675 pci_long_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCAP, in pcie_cap_slot_init()
677 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP, in pcie_cap_slot_init()
678 (s->slot << PCI_EXP_SLTCAP_PSN_SHIFT) | in pcie_cap_slot_init()
685 * Expose native hot-plug on all bridges if hot-plug is enabled on the slot. in pcie_cap_slot_init()
688 if (s->hotplug && in pcie_cap_slot_init()
689 (!s->hide_native_hotplug_cap || DEVICE(dev)->hotplugged)) { in pcie_cap_slot_init()
690 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP, in pcie_cap_slot_init()
695 if (dev->cap_present & QEMU_PCIE_SLTCAP_PCP) { in pcie_cap_slot_init()
696 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP, in pcie_cap_slot_init()
698 pci_word_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCTL, in pcie_cap_slot_init()
700 pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL, in pcie_cap_slot_init()
704 pci_word_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCTL, in pcie_cap_slot_init()
707 pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCTL, in pcie_cap_slot_init()
710 pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL, in pcie_cap_slot_init()
719 * pcie_cap_slot_write_config() test-and-clear the bit, so in pcie_cap_slot_init()
722 pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL, in pcie_cap_slot_init()
725 pci_word_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_SLTSTA, in pcie_cap_slot_init()
728 /* Avoid migration abortion when this device hot-removed by guest */ in pcie_cap_slot_init()
729 pci_word_test_and_clear_mask(dev->cmask + pos + PCI_EXP_SLTSTA, in pcie_cap_slot_init()
732 dev->exp.hpev_notified = false; in pcie_cap_slot_init()
740 uint8_t *exp_cap = dev->config + dev->exp.exp_cap; in pcie_cap_slot_reset()
760 if (dev->cap_present & QEMU_PCIE_SLTCAP_PCP) { in pcie_cap_slot_reset()
762 bool populated = pci_bridge_get_sec_bus(PCI_BRIDGE(dev))->devices[0]; in pcie_cap_slot_reset()
791 uint32_t pos = dev->exp.exp_cap; in pcie_cap_slot_get()
792 uint8_t *exp_cap = dev->config + pos; in pcie_cap_slot_get()
823 uint32_t pos = dev->exp.exp_cap; in pcie_cap_slot_write_config()
824 uint8_t *exp_cap = dev->config + pos; in pcie_cap_slot_write_config()
832 * As a work-around, detect this and revert status to what it was in pcie_cap_slot_write_config()
859 "sltsta -> 0x%02"PRIx16"\n", in pcie_cap_slot_write_config()
868 parent->canonical_path, in pcie_cap_slot_write_config()
869 child ? child->canonical_path : "no-child", in pcie_cap_slot_write_config()
899 * Software issues a command to a hot-plug capable Downstream Port by in pcie_cap_slot_write_config()
931 pci_set_word(dev->wmask + dev->exp.exp_cap + PCI_EXP_RTCTL, in pcie_cap_root_init()
938 pci_set_word(dev->config + dev->exp.exp_cap + PCI_EXP_RTCTL, 0); in pcie_cap_root_reset()
944 pci_long_test_and_set_mask(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCAP, in pcie_cap_flr_init()
949 * pcie_cap_flr_write_config() test-and-clear the bit, so in pcie_cap_flr_init()
952 pci_word_test_and_set_mask(dev->wmask + dev->exp.exp_cap + PCI_EXP_DEVCTL, in pcie_cap_flr_init()
959 uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL; in pcie_cap_flr_write_config()
968 /* Alternative Routing-ID Interpretation (ARI)
973 uint32_t pos = dev->exp.exp_cap; in pcie_cap_arifwd_init()
974 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP2, in pcie_cap_arifwd_init()
976 pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL2, in pcie_cap_arifwd_init()
982 uint8_t *devctl2 = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2; in pcie_cap_arifwd_reset()
991 if (!dev->exp.exp_cap) { in pcie_cap_is_arifwd_enabled()
995 return pci_get_long(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2) & in pcie_cap_is_arifwd_enabled()
1013 uint32_t header = pci_get_long(dev->config + PCI_CONFIG_SPACE_SIZE); in pcie_find_capability_list()
1024 assert(next <= PCIE_CONFIG_SPACE_SIZE - 8); in pcie_find_capability_list()
1026 header = pci_get_long(dev->config + next); in pcie_find_capability_list()
1046 uint32_t header = pci_get_long(dev->config + pos); in pcie_ext_cap_set_next()
1047 assert(!(next & (PCI_EXT_CAP_ALIGN - 1))); in pcie_ext_cap_set_next()
1050 pci_set_long(dev->config + pos, header); in pcie_ext_cap_set_next()
1079 pci_set_long(dev->config + offset, PCI_EXT_CAP(cap_id, cap_ver, 0)); in pcie_add_capability()
1081 /* Make capability read-only by default */ in pcie_add_capability()
1082 memset(dev->wmask + offset, 0, size); in pcie_add_capability()
1083 memset(dev->w1cmask + offset, 0, size); in pcie_add_capability()
1085 memset(dev->cmask + offset, 0xFF, size); in pcie_add_capability()
1090 * downstream device. If downstream device is not present, re-write with the
1102 PCIDevice *target = bus->devices[0]; in pcie_sync_bridge_lnk()
1103 uint8_t *exp_cap = bridge_dev->config + bridge_dev->exp.exp_cap; in pcie_sync_bridge_lnk()
1106 if (!target || !target->exp.exp_cap) { in pcie_sync_bridge_lnk()
1109 lnksta = target->config_read(target, in pcie_sync_bridge_lnk()
1110 target->exp.exp_cap + PCI_EXP_LNKSTA, in pcie_sync_bridge_lnk()
1141 uint16_t nextfn = dev->cap_present & QEMU_PCIE_ARI_NEXTFN_1 ? 1 : 0; in pcie_ari_init()
1145 pci_set_long(dev->config + offset + PCI_ARI_CAP, (nextfn & 0xff) << 8); in pcie_ari_init()
1155 pci_set_quad(dev->config + offset + pci_dsn_cap, ser_num); in pcie_dev_ser_num_init()
1163 dev->exp.ats_cap = offset; in pcie_ats_init()
1167 pci_set_word(dev->config + offset + PCI_ATS_CAP, in pcie_ats_init()
1171 pci_set_word(dev->config + offset + PCI_ATS_CTRL, 0); in pcie_ats_init()
1173 pci_set_word(dev->wmask + dev->exp.ats_cap + PCI_ATS_CTRL, 0x800f); in pcie_ats_init()
1184 (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) || in pcie_acs_init()
1185 PCI_FUNC(dev->devfn)); in pcie_acs_init()
1189 dev->exp.acs_cap = offset; in pcie_acs_init()
1197 * peer-to-peer between functions and thus omitted here. in pcie_acs_init()
1203 pci_set_word(dev->config + offset + PCI_ACS_CAP, cap_bits); in pcie_acs_init()
1204 pci_set_word(dev->wmask + offset + PCI_ACS_CTRL, cap_bits); in pcie_acs_init()
1209 if (dev->exp.acs_cap) { in pcie_acs_reset()
1210 pci_set_word(dev->config + dev->exp.acs_cap + PCI_ACS_CTRL, 0); in pcie_acs_reset()