Lines Matching refs:d

68 static void cxl_dsp_config_write(PCIDevice *d, uint32_t address,  in cxl_dsp_config_write()  argument
73 pcie_cap_slot_get(d, &slt_ctl, &slt_sta); in cxl_dsp_config_write()
74 pci_bridge_write_config(d, address, val, len); in cxl_dsp_config_write()
75 pcie_cap_flr_write_config(d, address, val, len); in cxl_dsp_config_write()
76 pcie_cap_slot_write_config(d, slt_ctl, slt_sta, address, val, len); in cxl_dsp_config_write()
77 pcie_aer_write_config(d, address, val, len); in cxl_dsp_config_write()
79 cxl_dsp_dvsec_write_config(d, address, val, len); in cxl_dsp_config_write()
84 PCIDevice *d = PCI_DEVICE(qdev); in cxl_dsp_reset() local
87 pcie_cap_deverr_reset(d); in cxl_dsp_reset()
88 pcie_cap_slot_reset(d); in cxl_dsp_reset()
89 pcie_cap_arifwd_reset(d); in cxl_dsp_reset()
135 static void cxl_dsp_realize(PCIDevice *d, Error **errp) in cxl_dsp_realize() argument
137 PCIEPort *p = PCIE_PORT(d); in cxl_dsp_realize()
138 PCIESlot *s = PCIE_SLOT(d); in cxl_dsp_realize()
139 CXLDownstreamPort *dsp = CXL_DSP(d); in cxl_dsp_realize()
145 pci_bridge_initfn(d, TYPE_PCIE_BUS); in cxl_dsp_realize()
146 pcie_port_init_reg(d); in cxl_dsp_realize()
148 rc = msi_init(d, CXL_DOWNSTREAM_PORT_MSI_OFFSET, in cxl_dsp_realize()
156 rc = pcie_cap_init(d, CXL_DOWNSTREAM_PORT_EXP_OFFSET, in cxl_dsp_realize()
163 pcie_cap_flr_init(d); in cxl_dsp_realize()
164 pcie_cap_deverr_init(d); in cxl_dsp_realize()
165 pcie_cap_slot_init(d, s); in cxl_dsp_realize()
166 pcie_cap_arifwd_init(d); in cxl_dsp_realize()
175 rc = pcie_aer_init(d, PCI_ERR_VER, CXL_DOWNSTREAM_PORT_AER_OFFSET, in cxl_dsp_realize()
182 cxl_cstate->pdev = d; in cxl_dsp_realize()
184 cxl_component_register_block_init(OBJECT(d), cxl_cstate, TYPE_CXL_DSP); in cxl_dsp_realize()
185 pci_register_bar(d, CXL_COMPONENT_REG_BAR_IDX, in cxl_dsp_realize()
195 pcie_cap_exit(d); in cxl_dsp_realize()
197 msi_uninit(d); in cxl_dsp_realize()
199 pci_bridge_exitfn(d); in cxl_dsp_realize()
202 static void cxl_dsp_exitfn(PCIDevice *d) in cxl_dsp_exitfn() argument
204 PCIESlot *s = PCIE_SLOT(d); in cxl_dsp_exitfn()
206 pcie_aer_exit(d); in cxl_dsp_exitfn()
208 pcie_cap_exit(d); in cxl_dsp_exitfn()
209 msi_uninit(d); in cxl_dsp_exitfn()
210 pci_bridge_exitfn(d); in cxl_dsp_exitfn()