8  * SPDX-License-Identifier: GPL-2.0-or-later
16 #include "hw/qdev-properties.h"
17 #include "hw/qdev-properties-system.h"
36 static void latch_registers(CXLDownstreamPort *dsp)  in latch_registers()  argument
38     uint32_t *reg_state = dsp->cxl_cstate.crb.cache_mem_registers;  in latch_registers()
39     uint32_t *write_msk = dsp->cxl_cstate.crb.cache_mem_regs_write_mask;  in latch_registers()
49     CXLDownstreamPort *dsp = CXL_DSP(dev);  in cxl_dsp_dvsec_write_config()  local
50     CXLComponentState *cxl_cstate = &dsp->cxl_cstate;  in cxl_dsp_dvsec_write_config()
52     if (range_contains(&cxl_cstate->dvsecs[EXTENSIONS_PORT_DVSEC], addr)) {  in cxl_dsp_dvsec_write_config()
53         uint8_t *reg = &dev->config[addr];  in cxl_dsp_dvsec_write_config()
54         addr -= cxl_cstate->dvsecs[EXTENSIONS_PORT_DVSEC].lob;  in cxl_dsp_dvsec_write_config()
87     CXLDownstreamPort *dsp = CXL_DSP(qdev);  in cxl_dsp_reset()  local
94     latch_registers(dsp);  in cxl_dsp_reset()
108         .cap                     = 0x27, /* Cache, IO, Mem, non-MLD */  in build_dvsecs()
109         .ctrl                    = 0x02, /* IO always enabled */  in build_dvsecs()
141     CXLDownstreamPort *dsp = CXL_DSP(d);  in cxl_dsp_realize()  local
142     CXLComponentState *cxl_cstate = &dsp->cxl_cstate;  in cxl_dsp_realize()
143     ComponentRegisters *cregs = &cxl_cstate->crb;  in cxl_dsp_realize()
144     MemoryRegion *component_bar = &cregs->component_registers;  in cxl_dsp_realize()
154         assert(rc == -ENOTSUP);  in cxl_dsp_realize()
159                        PCI_EXP_TYPE_DOWNSTREAM, p->port,  in cxl_dsp_realize()
170     pcie_chassis_create(s->chassis);  in cxl_dsp_realize()
183     cxl_cstate->dvsec_offset = CXL_DOWNSTREAM_PORT_DVSEC_OFFSET;  in cxl_dsp_realize()
184     cxl_cstate->pdev = d;  in cxl_dsp_realize()
216     DEFINE_PROP_PCIE_LINK_SPEED("x-speed", PCIESlot,
218     DEFINE_PROP_PCIE_LINK_WIDTH("x-width", PCIESlot,
229     k->config_write = cxl_dsp_config_write;  in cxl_dsp_class_init()
230     k->realize = cxl_dsp_realize;  in cxl_dsp_class_init()
231     k->exit = cxl_dsp_exitfn;  in cxl_dsp_class_init()
232     k->vendor_id = 0x19e5; /* Huawei */  in cxl_dsp_class_init()
233     k->device_id = 0xa129; /* Emulated CXL Switch Downstream Port */  in cxl_dsp_class_init()
234     k->revision = 0;  in cxl_dsp_class_init()
235     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);  in cxl_dsp_class_init()
236     dc->desc = "CXL Switch Downstream Port";  in cxl_dsp_class_init()