36 #define FLASH_BASE_ADDRESS 0x08000000
37 #define SRAM1_BASE_ADDRESS 0x20000000
39 #define SRAM2_BASE_ADDRESS 0x10000000
42 #define EXTI_ADDR 0x40010400
43 #define SYSCFG_ADDR 0x40010000
53     6,                      /* GPIO[0]                 */
81 #define RCC_BASE_ADDRESS 0x40021000
114     { 0x48000000, 0xABFFFFFF, 0x0C000000, 0x64000000 },
115     { 0x48000400, 0xFFFFFEBF, 0x00000000, 0x00000100 },
116     { 0x48000800, 0xFFFFFFFF, 0x00000000, 0x00000000 },
117     { 0x48000C00, 0xFFFFFFFF, 0x00000000, 0x00000000 },
118     { 0x48001000, 0xFFFFFFFF, 0x00000000, 0x00000000 },
119     { 0x48001400, 0xFFFFFFFF, 0x00000000, 0x00000000 },
120     { 0x48001800, 0xFFFFFFFF, 0x00000000, 0x00000000 },
121     { 0x48001C00, 0x0000000F, 0x00000000, 0x00000000 },
125     0x40013800, /* "USART1", 0x400 */
126     0x40004400, /* "USART2", 0x400 */
127     0x40004800, /* "USART3", 0x400 */
130     0x40004C00, /* "UART4" , 0x400 */
131     0x40005000  /* "UART5" , 0x400 */
134 #define LPUART_BASE_ADDRESS 0x40008000
141     for (unsigned i = 0; i < NUM_EXTI_OR_GATES; i++) {  in stm32l4x5_soc_initfn()
148     for (unsigned i = 0; i < NUM_GPIOS; i++) {  in stm32l4x5_soc_initfn()
153     for (int i = 0; i < STM_NUM_USARTS; i++) {  in stm32l4x5_soc_initfn()
158     for (int i = 0; i < STM_NUM_UARTS; i++) {  in stm32l4x5_soc_initfn()
181                              "flash_boot_alias", &s->flash, 0,  in stm32l4x5_soc_realize()
185     memory_region_add_subregion(system_memory, 0, &s->flash_alias);  in stm32l4x5_soc_realize()
216     for (unsigned i = 0; i < NUM_GPIOS; i++) {  in stm32l4x5_soc_realize()
234         sysbus_mmio_map(busdev, 0, stm32l4x5_gpio_cfg[i].addr);  in stm32l4x5_soc_realize()
244     sysbus_mmio_map(busdev, 0, SYSCFG_ADDR);  in stm32l4x5_soc_realize()
246     for (unsigned i = 0; i < NUM_GPIOS; i++) {  in stm32l4x5_soc_realize()
247         for (unsigned j = 0; j < GPIO_NUM_PINS; j++) {  in stm32l4x5_soc_realize()
262     sysbus_mmio_map(busdev, 0, EXTI_ADDR);  in stm32l4x5_soc_realize()
265     for (unsigned i = 0; i < NUM_EXTI_OR_GATES; i++) {  in stm32l4x5_soc_realize()
274         qdev_connect_gpio_out(DEVICE(&s->exti_or_gates[i]), 0,  in stm32l4x5_soc_realize()
279             for (unsigned j = 0; j < exti_or_gates_num_lines_in[i]; j++) {  in stm32l4x5_soc_realize()
286             for (unsigned j = 0; j < EXTI_OR_GATE1_NUM_LINES_IN; j++) {  in stm32l4x5_soc_realize()
295     for (unsigned i = 0; i < NUM_EXTI_IRQ; i++) {  in stm32l4x5_soc_realize()
303     for (unsigned i = 0; i < GPIO_NUM_PINS; i++) {  in stm32l4x5_soc_realize()
313     sysbus_mmio_map(busdev, 0, RCC_BASE_ADDRESS);  in stm32l4x5_soc_realize()
314     sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, RCC_IRQ));  in stm32l4x5_soc_realize()
317     for (int i = 0; i < STM_NUM_USARTS; i++) {  in stm32l4x5_soc_realize()
327         sysbus_mmio_map(busdev, 0, usart_addr[i]);  in stm32l4x5_soc_realize()
328         sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(&s->exti),  in stm32l4x5_soc_realize()
333     for (int i = 0; i < STM_NUM_UARTS; i++) {  in stm32l4x5_soc_realize()
343         sysbus_mmio_map(busdev, 0, uart_addr[i]);  in stm32l4x5_soc_realize()
344         sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(&s->exti),  in stm32l4x5_soc_realize()
357     sysbus_mmio_map(busdev, 0, LPUART_BASE_ADDRESS);  in stm32l4x5_soc_realize()
358     sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(&s->exti),  in stm32l4x5_soc_realize()
362     create_unimplemented_device("TIM2",      0x40000000, 0x400);  in stm32l4x5_soc_realize()
363     create_unimplemented_device("TIM3",      0x40000400, 0x400);  in stm32l4x5_soc_realize()
364     create_unimplemented_device("TIM4",      0x40000800, 0x400);  in stm32l4x5_soc_realize()
365     create_unimplemented_device("TIM5",      0x40000C00, 0x400);  in stm32l4x5_soc_realize()
366     create_unimplemented_device("TIM6",      0x40001000, 0x400);  in stm32l4x5_soc_realize()
367     create_unimplemented_device("TIM7",      0x40001400, 0x400);  in stm32l4x5_soc_realize()
368     /* RESERVED:    0x40001800, 0x1000 */  in stm32l4x5_soc_realize()
369     create_unimplemented_device("RTC",       0x40002800, 0x400);  in stm32l4x5_soc_realize()
370     create_unimplemented_device("WWDG",      0x40002C00, 0x400);  in stm32l4x5_soc_realize()
371     create_unimplemented_device("IWDG",      0x40003000, 0x400);  in stm32l4x5_soc_realize()
372     /* RESERVED:    0x40001800, 0x400 */  in stm32l4x5_soc_realize()
373     create_unimplemented_device("SPI2",      0x40003800, 0x400);  in stm32l4x5_soc_realize()
374     create_unimplemented_device("SPI3",      0x40003C00, 0x400);  in stm32l4x5_soc_realize()
375     /* RESERVED:    0x40004000, 0x400 */  in stm32l4x5_soc_realize()
376     create_unimplemented_device("I2C1",      0x40005400, 0x400);  in stm32l4x5_soc_realize()
377     create_unimplemented_device("I2C2",      0x40005800, 0x400);  in stm32l4x5_soc_realize()
378     create_unimplemented_device("I2C3",      0x40005C00, 0x400);  in stm32l4x5_soc_realize()
379     /* RESERVED:    0x40006000, 0x400 */  in stm32l4x5_soc_realize()
380     create_unimplemented_device("CAN1",      0x40006400, 0x400);  in stm32l4x5_soc_realize()
381     /* RESERVED:    0x40006800, 0x400 */  in stm32l4x5_soc_realize()
382     create_unimplemented_device("PWR",       0x40007000, 0x400);  in stm32l4x5_soc_realize()
383     create_unimplemented_device("DAC1",      0x40007400, 0x400);  in stm32l4x5_soc_realize()
384     create_unimplemented_device("OPAMP",     0x40007800, 0x400);  in stm32l4x5_soc_realize()
385     create_unimplemented_device("LPTIM1",    0x40007C00, 0x400);  in stm32l4x5_soc_realize()
386     /* RESERVED:    0x40008400, 0x400 */  in stm32l4x5_soc_realize()
387     create_unimplemented_device("SWPMI1",    0x40008800, 0x400);  in stm32l4x5_soc_realize()
388     /* RESERVED:    0x40008C00, 0x800 */  in stm32l4x5_soc_realize()
389     create_unimplemented_device("LPTIM2",    0x40009400, 0x400);  in stm32l4x5_soc_realize()
390     /* RESERVED:    0x40009800, 0x6800 */  in stm32l4x5_soc_realize()
393     create_unimplemented_device("VREFBUF",   0x40010030, 0x1D0);  in stm32l4x5_soc_realize()
394     create_unimplemented_device("COMP",      0x40010200, 0x200);  in stm32l4x5_soc_realize()
395     /* RESERVED:    0x40010800, 0x1400 */  in stm32l4x5_soc_realize()
396     create_unimplemented_device("FIREWALL",  0x40011C00, 0x400);  in stm32l4x5_soc_realize()
397     /* RESERVED:    0x40012000, 0x800 */  in stm32l4x5_soc_realize()
398     create_unimplemented_device("SDMMC1",    0x40012800, 0x400);  in stm32l4x5_soc_realize()
399     create_unimplemented_device("TIM1",      0x40012C00, 0x400);  in stm32l4x5_soc_realize()
400     create_unimplemented_device("SPI1",      0x40013000, 0x400);  in stm32l4x5_soc_realize()
401     create_unimplemented_device("TIM8",      0x40013400, 0x400);  in stm32l4x5_soc_realize()
402     /* RESERVED:    0x40013C00, 0x400 */  in stm32l4x5_soc_realize()
403     create_unimplemented_device("TIM15",     0x40014000, 0x400);  in stm32l4x5_soc_realize()
404     create_unimplemented_device("TIM16",     0x40014400, 0x400);  in stm32l4x5_soc_realize()
405     create_unimplemented_device("TIM17",     0x40014800, 0x400);  in stm32l4x5_soc_realize()
406     /* RESERVED:    0x40014C00, 0x800 */  in stm32l4x5_soc_realize()
407     create_unimplemented_device("SAI1",      0x40015400, 0x400);  in stm32l4x5_soc_realize()
408     create_unimplemented_device("SAI2",      0x40015800, 0x400);  in stm32l4x5_soc_realize()
409     /* RESERVED:    0x40015C00, 0x400 */  in stm32l4x5_soc_realize()
410     create_unimplemented_device("DFSDM1",    0x40016000, 0x400);  in stm32l4x5_soc_realize()
411     /* RESERVED:    0x40016400, 0x9C00 */  in stm32l4x5_soc_realize()
414     create_unimplemented_device("DMA1",      0x40020000, 0x400);  in stm32l4x5_soc_realize()
415     create_unimplemented_device("DMA2",      0x40020400, 0x400);  in stm32l4x5_soc_realize()
416     /* RESERVED:    0x40020800, 0x800 */  in stm32l4x5_soc_realize()
417     /* RESERVED:    0x40021400, 0xC00 */  in stm32l4x5_soc_realize()
418     create_unimplemented_device("FLASH",     0x40022000, 0x400);  in stm32l4x5_soc_realize()
419     /* RESERVED:    0x40022400, 0xC00 */  in stm32l4x5_soc_realize()
420     create_unimplemented_device("CRC",       0x40023000, 0x400);  in stm32l4x5_soc_realize()
421     /* RESERVED:    0x40023400, 0x400 */  in stm32l4x5_soc_realize()
422     create_unimplemented_device("TSC",       0x40024000, 0x400);  in stm32l4x5_soc_realize()
424     /* RESERVED:    0x40024400, 0x7FDBC00 */  in stm32l4x5_soc_realize()
427     /* RESERVED:    0x48002000, 0x7FDBC00 */  in stm32l4x5_soc_realize()
428     create_unimplemented_device("OTG_FS",    0x50000000, 0x40000);  in stm32l4x5_soc_realize()
429     create_unimplemented_device("ADC",       0x50040000, 0x400);  in stm32l4x5_soc_realize()
430     /* RESERVED:    0x50040400, 0x20400 */  in stm32l4x5_soc_realize()
431     create_unimplemented_device("RNG",       0x50060800, 0x400);  in stm32l4x5_soc_realize()
434     create_unimplemented_device("FMC",       0xA0000000, 0x1000);  in stm32l4x5_soc_realize()
435     create_unimplemented_device("QUADSPI",   0xA0001000, 0x400);  in stm32l4x5_soc_realize()