Lines Matching +full:throttle +full:- +full:period +full:- +full:us
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2014 - 2018, NVIDIA CORPORATION. All rights reserved.
34 #include <dt-bindings/thermal/tegra124-soctherm.h>
197 #define REG_GET_MASK(r, m) (((r) & (m)) >> (ffs(m) - 1))
200 (((v) & (m >> (ffs(m) - 1))) << (ffs(m) - 1)))
203 #define THROT_DEPTH_DIVIDEND(depth) ((256 * (100 - (depth)) / 100) - 1)
205 /* gk20a nv_therm interface N:3 Mapping. Levels defined in tegra124-soctherm.h
212 #define THROT_LEVEL_TO_DEPTH(level) ((0x1 << (level)) - 1)
229 (ALARM_OFFSET * (throt - THROTTLE_OC1)))
232 (ALARM_OFFSET * (throt - THROTTLE_OC1)))
235 (ALARM_OFFSET * (throt - THROTTLE_OC1)))
238 (ALARM_OFFSET * (throt - THROTTLE_OC1)))
241 (ALARM_OFFSET * (throt - THROTTLE_OC1)))
244 (4 * (throt - THROTTLE_OC1)))
260 static const int min_low_temp = -127000;
361 * ccroc_writel() - writes a value to a CCROC register
370 writel(value, (ts->ccroc_regs + reg)); in ccroc_writel()
374 * ccroc_readl() - reads specified register from CCROC IP block
382 return readl(ts->ccroc_regs + reg); in ccroc_readl()
387 const struct tegra_tsensor *sensor = &tegra->soc->tsensors[i]; in enable_tsensor()
388 void __iomem *base = tegra->regs + sensor->base; in enable_tsensor()
391 val = sensor->config->tall << SENSOR_CONFIG0_TALL_SHIFT; in enable_tsensor()
394 val = (sensor->config->tsample - 1) << SENSOR_CONFIG1_TSAMPLE_SHIFT; in enable_tsensor()
395 val |= sensor->config->tiddq_en << SENSOR_CONFIG1_TIDDQ_EN_SHIFT; in enable_tsensor()
396 val |= sensor->config->ten_count << SENSOR_CONFIG1_TEN_COUNT_SHIFT; in enable_tsensor()
400 writel(tegra->calib[i], base + SENSOR_CONFIG2); in enable_tsensor()
419 t *= -1; in translate_temp()
429 val = readl(zone->reg); in tegra_thermctl_get_temp()
430 val = REG_GET_MASK(val, zone->sg->sensor_temp_mask); in tegra_thermctl_get_temp()
437 * enforce_temp_range() - check and enforce temperature range [min, max]
459 * thermtrip_program() - Configures the hardware to shut down the
472 * Return: 0 upon success, or %-EINVAL upon failure.
482 if (!sg || !sg->thermtrip_threshold_mask) in thermtrip_program()
483 return -EINVAL; in thermtrip_program()
485 temp = enforce_temp_range(dev, trip_temp) / ts->soc->thresh_grain; in thermtrip_program()
487 r = readl(ts->regs + THERMCTL_THERMTRIP_CTL); in thermtrip_program()
488 r = REG_SET_MASK(r, sg->thermtrip_threshold_mask, temp); in thermtrip_program()
489 r = REG_SET_MASK(r, sg->thermtrip_enable_mask, 1); in thermtrip_program()
490 r = REG_SET_MASK(r, sg->thermtrip_any_en_mask, 0); in thermtrip_program()
491 writel(r, ts->regs + THERMCTL_THERMTRIP_CTL); in thermtrip_program()
497 * throttrip_program() - Configures the hardware to throttle the
501 * @stc: pointer to the throttle need to be triggered
504 * Sets the thermal trip threshold and throttle event of the given sensor
506 * throttle.
511 * Return: 0 upon success, or %-EINVAL upon failure.
523 if (!sg || !stc || !stc->init) in throttrip_program()
524 return -EINVAL; in throttrip_program()
526 temp = enforce_temp_range(dev, trip_temp) / ts->soc->thresh_grain; in throttrip_program()
529 throt = stc->id; in throttrip_program()
530 reg_off = THERMCTL_LVL_REG(sg->thermctl_lvl0_offset, throt + 1); in throttrip_program()
540 "invalid throt id %d - assuming HEAVY", in throttrip_program()
544 r = readl(ts->regs + reg_off); in throttrip_program()
545 r = REG_SET_MASK(r, sg->thermctl_lvl0_up_thresh_mask, temp); in throttrip_program()
546 r = REG_SET_MASK(r, sg->thermctl_lvl0_dn_thresh_mask, temp); in throttrip_program()
550 writel(r, ts->regs + reg_off); in throttrip_program()
560 for (i = 0; ts->throt_cfgs[i].name; i++) in find_throttle_cfg_by_name()
561 if (!strcmp(ts->throt_cfgs[i].name, name)) in find_throttle_cfg_by_name()
562 return &ts->throt_cfgs[i]; in find_throttle_cfg_by_name()
570 struct tsensor_group_thermtrips *tt = ts->soc->thermtrips; in tsensor_group_thermtrip_get()
576 for (i = 0; i < ts->soc->num_ttgs; i++) { in tsensor_group_thermtrip_get()
588 struct tegra_soctherm *ts = zone->ts; in tegra_thermctl_set_trip_temp()
590 const struct tegra_tsensor_group *sg = zone->sg; in tegra_thermctl_set_trip_temp()
591 struct device *dev = zone->dev; in tegra_thermctl_set_trip_temp()
595 return -EINVAL; in tegra_thermctl_set_trip_temp()
607 if (min_low_temp == tsensor_group_thermtrip_get(ts, sg->id)) in tegra_thermctl_set_trip_temp()
619 if (!ts->throt_cfgs[i].init) in tegra_thermctl_set_trip_temp()
622 cdev = ts->throt_cfgs[i].cdev; in tegra_thermctl_set_trip_temp()
624 stc = find_throttle_cfg_by_name(ts, cdev->type); in tegra_thermctl_set_trip_temp()
640 mutex_lock(&zn->ts->thermctl_lock); in thermal_irq_enable()
641 r = readl(zn->ts->regs + THERMCTL_INTR_ENABLE); in thermal_irq_enable()
642 r = REG_SET_MASK(r, zn->sg->thermctl_isr_mask, TH_INTR_UP_DN_EN); in thermal_irq_enable()
643 writel(r, zn->ts->regs + THERMCTL_INTR_ENABLE); in thermal_irq_enable()
644 mutex_unlock(&zn->ts->thermctl_lock); in thermal_irq_enable()
652 mutex_lock(&zn->ts->thermctl_lock); in thermal_irq_disable()
653 r = readl(zn->ts->regs + THERMCTL_INTR_DISABLE); in thermal_irq_disable()
654 r = REG_SET_MASK(r, zn->sg->thermctl_isr_mask, 0); in thermal_irq_disable()
655 writel(r, zn->ts->regs + THERMCTL_INTR_DISABLE); in thermal_irq_disable()
656 mutex_unlock(&zn->ts->thermctl_lock); in thermal_irq_disable()
666 r = readl(zone->ts->regs + zone->sg->thermctl_lvl0_offset); in tegra_thermctl_set_trips()
668 writel(r, zone->ts->regs + zone->sg->thermctl_lvl0_offset); in tegra_thermctl_set_trips()
670 lo = enforce_temp_range(zone->dev, lo) / zone->ts->soc->thresh_grain; in tegra_thermctl_set_trips()
671 hi = enforce_temp_range(zone->dev, hi) / zone->ts->soc->thresh_grain; in tegra_thermctl_set_trips()
672 dev_dbg(zone->dev, "%s hi:%d, lo:%d\n", __func__, hi, lo); in tegra_thermctl_set_trips()
674 r = REG_SET_MASK(r, zone->sg->thermctl_lvl0_up_thresh_mask, hi); in tegra_thermctl_set_trips()
675 r = REG_SET_MASK(r, zone->sg->thermctl_lvl0_dn_thresh_mask, lo); in tegra_thermctl_set_trips()
677 writel(r, zone->ts->regs + zone->sg->thermctl_lvl0_offset); in tegra_thermctl_set_trips()
699 return -EINVAL; in get_hot_temp()
707 return -EINVAL; in get_hot_temp()
711 * tegra_soctherm_set_hwtrips() - set HW trip point from DT data
717 * "THROTTLE" trip points , using "thermtrips", "critical" or "hot"
720 * After they have been configured, THERMTRIP or THROTTLE will take
730 * THROTTLE has been enabled successfully when a message similar to
732 * ""throttrip: will throttle when sensor group XXX reaches YYYYYY mC"
743 temperature = tsensor_group_thermtrip_get(ts, sg->id); in tegra_soctherm_set_hwtrips()
750 dev_err(dev, "thermtrip: %s: error during enable\n", sg->name); in tegra_soctherm_set_hwtrips()
755 sg->name, temperature); in tegra_soctherm_set_hwtrips()
760 sg->name); in tegra_soctherm_set_hwtrips()
767 if (!ts->throt_cfgs[i].init) in tegra_soctherm_set_hwtrips()
770 cdev = ts->throt_cfgs[i].cdev; in tegra_soctherm_set_hwtrips()
772 stc = find_throttle_cfg_by_name(ts, cdev->type); in tegra_soctherm_set_hwtrips()
779 sg->name); in tegra_soctherm_set_hwtrips()
784 "throttrip: will throttle when %s reaches %d mC\n", in tegra_soctherm_set_hwtrips()
785 sg->name, temperature); in tegra_soctherm_set_hwtrips()
790 dev_info(dev, "throttrip: %s: missing throttle cdev\n", in tegra_soctherm_set_hwtrips()
791 sg->name); in tegra_soctherm_set_hwtrips()
807 * cause a new interrupt but this is taken care of by the re-reading of in soctherm_thermal_isr()
810 r = readl(ts->regs + THERMCTL_INTR_STATUS); in soctherm_thermal_isr()
811 writel(r, ts->regs + THERMCTL_INTR_DISABLE); in soctherm_thermal_isr()
817 * soctherm_thermal_isr_thread() - Handles a thermal interrupt request
828 * Disabled interrupts are re-enabled.
839 st = readl(ts->regs + THERMCTL_INTR_STATUS); in soctherm_thermal_isr_thread()
856 writel(ex, ts->regs + THERMCTL_INTR_STATUS); in soctherm_thermal_isr_thread()
860 tz = ts->thermctl_tzs[TEGRA124_SOCTHERM_SENSOR_CPU]; in soctherm_thermal_isr_thread()
866 tz = ts->thermctl_tzs[TEGRA124_SOCTHERM_SENSOR_GPU]; in soctherm_thermal_isr_thread()
872 tz = ts->thermctl_tzs[TEGRA124_SOCTHERM_SENSOR_PLLX]; in soctherm_thermal_isr_thread()
878 tz = ts->thermctl_tzs[TEGRA124_SOCTHERM_SENSOR_MEM]; in soctherm_thermal_isr_thread()
891 writel(st, ts->regs + THERMCTL_INTR_STATUS); in soctherm_thermal_isr_thread()
898 * soctherm_oc_intr_enable() - Enables the soctherm over-current interrupt
900 * @alarm: The soctherm throttle id
901 * @enable: Flag indicating enable the soctherm over-current
904 * Enables a specific over-current pins @alarm to raise an interrupt if the flag
916 r = readl(ts->regs + OC_INTR_ENABLE); in soctherm_oc_intr_enable()
934 writel(r, ts->regs + OC_INTR_ENABLE); in soctherm_oc_intr_enable()
938 * soctherm_handle_alarm() - Handles soctherm alarms
939 * @alarm: The soctherm throttle id
941 * "Handles" over-current alarms (OC1, OC2, OC3, and OC4) by printing
944 * Return: -EINVAL for @alarm = THROTTLE_OC3, otherwise 0 (success).
948 int rv = -EINVAL; in soctherm_handle_alarm()
983 * soctherm_edp_isr_thread() - log an over-current interrupt request
987 * Over-current events are handled in hardware. This function is called to log
989 * over-current interrupt registers for registers are set but
1000 st = readl(ts->regs + OC_INTR_STATUS); in soctherm_edp_isr_thread()
1011 writel(st, ts->regs + OC_INTR_STATUS); in soctherm_edp_isr_thread()
1045 writel(st, ts->regs + OC_INTR_STATUS); in soctherm_edp_isr_thread()
1052 * soctherm_edp_isr() - Disables any active interrupts
1059 * handle asserted interrupts and subsequently unmask/re-enable them.
1074 r = readl(ts->regs + OC_INTR_STATUS); in soctherm_edp_isr()
1075 writel(r, ts->regs + OC_INTR_DISABLE); in soctherm_edp_isr()
1081 * soctherm_oc_irq_lock() - locks the over-current interrupt request
1085 * a particular over-current interrupt request.
1091 mutex_lock(&d->irq_lock); in soctherm_oc_irq_lock()
1095 * soctherm_oc_irq_sync_unlock() - Unlocks the OC interrupt request
1099 * with a particular over-current interrupt request.
1105 mutex_unlock(&d->irq_lock); in soctherm_oc_irq_sync_unlock()
1109 * soctherm_oc_irq_enable() - Enables the SOC_THERM over-current interrupt queue
1113 * to respond to over-current interrupts.
1120 d->irq_enable |= BIT(data->hwirq); in soctherm_oc_irq_enable()
1124 * soctherm_oc_irq_disable() - Disables overcurrent interrupt requests
1136 d->irq_enable &= ~BIT(data->hwirq); in soctherm_oc_irq_disable()
1145 * soctherm_oc_irq_map() - SOC_THERM interrupt request domain mapper
1164 struct soctherm_oc_irq_chip_data *data = h->host_data; in soctherm_oc_irq_map()
1167 irq_set_chip(virq, &data->irq_chip); in soctherm_oc_irq_map()
1173 * soctherm_irq_domain_xlate_twocell() - xlate for soctherm interrupts
1193 return -EINVAL; in soctherm_irq_domain_xlate_twocell()
1199 *out_hwirq = intspec[0] - 1; in soctherm_irq_domain_xlate_twocell()
1210 * soctherm_oc_int_init() - Initial enabling of the over
1218 * -ENOMEM (out of memory), or irq_base if the function failed to
1246 return -ENOMEM; in soctherm_oc_int_init()
1256 struct platform_device *pdev = s->private; in regs_show()
1258 const struct tegra_tsensor *tsensors = ts->soc->tsensors; in regs_show()
1259 const struct tegra_tsensor_group **ttgs = ts->soc->ttgs; in regs_show()
1263 seq_puts(s, "-----TSENSE (convert HW)-----\n"); in regs_show()
1265 for (i = 0; i < ts->soc->num_tsensors; i++) { in regs_show()
1266 r = readl(ts->regs + tsensors[i].base + SENSOR_CONFIG1); in regs_show()
1284 r = readl(ts->regs + tsensors[i].base + SENSOR_STATUS1); in regs_show()
1290 r = readl(ts->regs + tsensors[i].base + SENSOR_STATUS0); in regs_show()
1296 r = readl(ts->regs + tsensors[i].base + SENSOR_CONFIG0); in regs_show()
1308 r = readl(ts->regs + tsensors[i].base + SENSOR_CONFIG2); in regs_show()
1315 r = readl(ts->regs + SENSOR_PDIV); in regs_show()
1318 r = readl(ts->regs + SENSOR_HOTSPOT_OFF); in regs_show()
1322 seq_puts(s, "-----SOC_THERM-----\n"); in regs_show()
1324 r = readl(ts->regs + SENSOR_TEMP1); in regs_show()
1329 r = readl(ts->regs + SENSOR_TEMP2); in regs_show()
1335 for (i = 0; i < ts->soc->num_ttgs; i++) { in regs_show()
1336 seq_printf(s, "%s:\n", ttgs[i]->name); in regs_show()
1340 u16 off = ttgs[i]->thermctl_lvl0_offset; in regs_show()
1342 r = readl(ts->regs + THERMCTL_LVL_REG(off, level)); in regs_show()
1344 mask = ttgs[i]->thermctl_lvl0_up_thresh_mask; in regs_show()
1346 v = sign_extend32(state, ts->soc->bptt - 1); in regs_show()
1347 v *= ts->soc->thresh_grain; in regs_show()
1350 mask = ttgs[i]->thermctl_lvl0_dn_thresh_mask; in regs_show()
1352 v = sign_extend32(state, ts->soc->bptt - 1); in regs_show()
1353 v *= ts->soc->thresh_grain; in regs_show()
1393 r = readl(ts->regs + THERMCTL_STATS_CTL); in regs_show()
1395 r & STATS_CTL_EN_UP ? "En" : "--", in regs_show()
1396 r & STATS_CTL_EN_DN ? "En" : "--"); in regs_show()
1402 r = readl(ts->regs + THERMCTL_LVL_REG(off, level)); in regs_show()
1406 r = readl(ts->regs + THERMCTL_LVL_REG(off, level)); in regs_show()
1410 r = readl(ts->regs + THERMCTL_THERMTRIP_CTL); in regs_show()
1411 state = REG_GET_MASK(r, ttgs[0]->thermtrip_any_en_mask); in regs_show()
1413 for (i = 0; i < ts->soc->num_ttgs; i++) { in regs_show()
1414 state = REG_GET_MASK(r, ttgs[i]->thermtrip_enable_mask); in regs_show()
1415 seq_printf(s, " %s En(%d) ", ttgs[i]->name, state); in regs_show()
1416 state = REG_GET_MASK(r, ttgs[i]->thermtrip_threshold_mask); in regs_show()
1417 state *= ts->soc->thresh_grain; in regs_show()
1421 r = readl(ts->regs + THROT_GLOBAL_CFG); in regs_show()
1423 seq_printf(s, "GLOBAL THROTTLE CONFIG: 0x%08x\n", r); in regs_show()
1425 seq_puts(s, "---------------------------------------------------\n"); in regs_show()
1426 r = readl(ts->regs + THROT_STATUS); in regs_show()
1434 r = readl(ts->regs + CPU_PSKIP_STATUS); in regs_show()
1435 if (ts->soc->use_ccroc) { in regs_show()
1459 tegra->debugfs_dir = root; in soctherm_debug_init()
1472 if (!tegra->clock_soctherm || !tegra->clock_tsensor) in soctherm_clk_enable()
1473 return -EINVAL; in soctherm_clk_enable()
1475 reset_control_assert(tegra->reset); in soctherm_clk_enable()
1478 err = clk_prepare_enable(tegra->clock_soctherm); in soctherm_clk_enable()
1480 reset_control_deassert(tegra->reset); in soctherm_clk_enable()
1484 err = clk_prepare_enable(tegra->clock_tsensor); in soctherm_clk_enable()
1486 clk_disable_unprepare(tegra->clock_soctherm); in soctherm_clk_enable()
1487 reset_control_deassert(tegra->reset); in soctherm_clk_enable()
1491 clk_disable_unprepare(tegra->clock_tsensor); in soctherm_clk_enable()
1492 clk_disable_unprepare(tegra->clock_soctherm); in soctherm_clk_enable()
1495 reset_control_deassert(tegra->reset); in soctherm_clk_enable()
1510 struct tegra_soctherm *ts = cdev->devdata; in throt_get_cdev_cur_state()
1513 r = readl(ts->regs + THROT_STATUS); in throt_get_cdev_cur_state()
1536 struct device *dev = &pdev->dev; in soctherm_thermtrips_parse()
1538 struct tsensor_group_thermtrips *tt = ts->soc->thermtrips; in soctherm_thermtrips_parse()
1539 const int max_num_prop = ts->soc->num_ttgs * 2; in soctherm_thermtrips_parse()
1544 return -ENOMEM; in soctherm_thermtrips_parse()
1546 n = of_property_count_u32_elems(dev->of_node, "nvidia,thermtrips"); in soctherm_thermtrips_parse()
1555 tlb = devm_kcalloc(&pdev->dev, max_num_prop, sizeof(u32), GFP_KERNEL); in soctherm_thermtrips_parse()
1557 return -ENOMEM; in soctherm_thermtrips_parse()
1558 ret = of_property_read_u32_array(dev->of_node, "nvidia,thermtrips", in soctherm_thermtrips_parse()
1584 if (of_property_read_bool(np_oc, "nvidia,polarity-active-low")) in soctherm_oc_cfg_parse()
1585 stc->oc_cfg.active_low = 1; in soctherm_oc_cfg_parse()
1587 stc->oc_cfg.active_low = 0; in soctherm_oc_cfg_parse()
1589 if (!of_property_read_u32(np_oc, "nvidia,count-threshold", &val)) { in soctherm_oc_cfg_parse()
1590 stc->oc_cfg.intr_en = 1; in soctherm_oc_cfg_parse()
1591 stc->oc_cfg.alarm_cnt_thresh = val; in soctherm_oc_cfg_parse()
1594 if (!of_property_read_u32(np_oc, "nvidia,throttle-period-us", &val)) in soctherm_oc_cfg_parse()
1595 stc->oc_cfg.throt_period = val; in soctherm_oc_cfg_parse()
1597 if (!of_property_read_u32(np_oc, "nvidia,alarm-filter", &val)) in soctherm_oc_cfg_parse()
1598 stc->oc_cfg.alarm_filter = val; in soctherm_oc_cfg_parse()
1601 stc->oc_cfg.mode = OC_THROTTLE_MODE_BRIEF; in soctherm_oc_cfg_parse()
1614 dev_err(dev, "throttle-cfg: %s: invalid priority\n", stc->name); in soctherm_throt_cfg_parse()
1615 return -EINVAL; in soctherm_throt_cfg_parse()
1617 stc->priority = val; in soctherm_throt_cfg_parse()
1619 ret = of_property_read_u32(np, ts->soc->use_ccroc ? in soctherm_throt_cfg_parse()
1620 "nvidia,cpu-throt-level" : in soctherm_throt_cfg_parse()
1621 "nvidia,cpu-throt-percent", &val); in soctherm_throt_cfg_parse()
1623 if (ts->soc->use_ccroc && in soctherm_throt_cfg_parse()
1625 stc->cpu_throt_level = val; in soctherm_throt_cfg_parse()
1626 else if (!ts->soc->use_ccroc && val <= 100) in soctherm_throt_cfg_parse()
1627 stc->cpu_throt_depth = val; in soctherm_throt_cfg_parse()
1634 ret = of_property_read_u32(np, "nvidia,gpu-throt-level", &val); in soctherm_throt_cfg_parse()
1636 stc->gpu_throt_level = val; in soctherm_throt_cfg_parse()
1643 dev_err(dev, "throttle-cfg: %s: no throt prop or invalid prop\n", in soctherm_throt_cfg_parse()
1644 stc->name); in soctherm_throt_cfg_parse()
1645 return -EINVAL; in soctherm_throt_cfg_parse()
1649 * soctherm_init_hw_throt_cdev() - Parse the HW throttle configurations
1655 struct device *dev = &pdev->dev; in soctherm_init_hw_throt_cdev()
1662 ts->throt_cfgs[i].name = throt_names[i]; in soctherm_init_hw_throt_cdev()
1663 ts->throt_cfgs[i].id = i; in soctherm_init_hw_throt_cdev()
1664 ts->throt_cfgs[i].init = false; in soctherm_init_hw_throt_cdev()
1667 np_stc = of_get_child_by_name(dev->of_node, "throttle-cfgs"); in soctherm_init_hw_throt_cdev()
1670 "throttle-cfg: no throttle-cfgs - not enabling\n"); in soctherm_init_hw_throt_cdev()
1679 name = np_stcc->name; in soctherm_init_hw_throt_cdev()
1683 "throttle-cfg: could not find %s\n", name); in soctherm_init_hw_throt_cdev()
1687 if (stc->init) { in soctherm_init_hw_throt_cdev()
1688 dev_err(dev, "throttle-cfg: %s: redefined!\n", name); in soctherm_init_hw_throt_cdev()
1697 if (stc->id >= THROTTLE_OC1) { in soctherm_init_hw_throt_cdev()
1699 stc->init = true; in soctherm_init_hw_throt_cdev()
1707 "throttle-cfg: %s: failed to register cooling device\n", in soctherm_init_hw_throt_cdev()
1711 stc->cdev = tcd; in soctherm_init_hw_throt_cdev()
1712 stc->init = true; in soctherm_init_hw_throt_cdev()
1721 * throttlectl_cpu_level_cfg() - programs CCROC NV_THERM level config
1725 * It's necessary to set up the CPU-local CCROC NV_THERM instance with
1728 * This function pre-programs the CCROC NV_THERM levels in terms of
1729 * pre-configured "Low", "Medium" or "Heavy" throttle levels which are
1769 * throttlectl_cpu_level_select() - program CPU pulse skipper config
1771 * @throt: the LIGHT/HEAVY of throttle event id
1773 * Pulse skippers are used to throttle clock frequencies. This
1775 * data. This function is used on SoCs which have CPU-local pulse
1786 switch (ts->throt_cfgs[throt].cpu_throt_level) { in throttlectl_cpu_level_select()
1801 r = readl(ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_CPU)); in throttlectl_cpu_level_select()
1805 writel(r, ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_CPU)); in throttlectl_cpu_level_select()
1809 writel(r, ts->regs + THROT_PSKIP_RAMP(throt, THROTTLE_DEV_CPU)); in throttlectl_cpu_level_select()
1813 * throttlectl_cpu_mn() - program CPU pulse skipper configuration
1815 * @throt: the LIGHT/HEAVY of throttle event id
1817 * Pulse skippers are used to throttle clock frequencies. This
1831 depth = ts->throt_cfgs[throt].cpu_throt_depth; in throttlectl_cpu_mn()
1834 r = readl(ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_CPU)); in throttlectl_cpu_mn()
1838 writel(r, ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_CPU)); in throttlectl_cpu_mn()
1840 r = readl(ts->regs + THROT_PSKIP_RAMP(throt, THROTTLE_DEV_CPU)); in throttlectl_cpu_mn()
1843 writel(r, ts->regs + THROT_PSKIP_RAMP(throt, THROTTLE_DEV_CPU)); in throttlectl_cpu_mn()
1847 * throttlectl_gpu_level_select() - selects throttling level for GPU
1849 * @throt: the LIGHT/HEAVY of throttle event id
1852 * pre-configured "Low", "Medium" or "Heavy" throttle levels.
1861 level = ts->throt_cfgs[throt].gpu_throt_level; in throttlectl_gpu_level_select()
1863 r = readl(ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_GPU)); in throttlectl_gpu_level_select()
1866 writel(r, ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_GPU)); in throttlectl_gpu_level_select()
1873 struct soctherm_oc_cfg *oc = &ts->throt_cfgs[throt].oc_cfg; in soctherm_oc_cfg_program()
1875 if (oc->mode == OC_THROTTLE_MODE_DISABLED) in soctherm_oc_cfg_program()
1876 return -EINVAL; in soctherm_oc_cfg_program()
1879 r = REG_SET_MASK(r, OC1_CFG_THROTTLE_MODE_MASK, oc->mode); in soctherm_oc_cfg_program()
1880 r = REG_SET_MASK(r, OC1_CFG_ALARM_POLARITY_MASK, oc->active_low); in soctherm_oc_cfg_program()
1882 writel(r, ts->regs + ALARM_CFG(throt)); in soctherm_oc_cfg_program()
1883 writel(oc->throt_period, ts->regs + ALARM_THROTTLE_PERIOD(throt)); in soctherm_oc_cfg_program()
1884 writel(oc->alarm_cnt_thresh, ts->regs + ALARM_CNT_THRESHOLD(throt)); in soctherm_oc_cfg_program()
1885 writel(oc->alarm_filter, ts->regs + ALARM_FILTER(throt)); in soctherm_oc_cfg_program()
1886 soctherm_oc_intr_enable(ts, throt, oc->intr_en); in soctherm_oc_cfg_program()
1892 * soctherm_throttle_program() - programs pulse skippers' configuration
1894 * @throt: the LIGHT/HEAVY of the throttle event id.
1896 * Pulse skippers are used to throttle clock frequencies.
1903 struct soctherm_throt_cfg stc = ts->throt_cfgs[throt]; in soctherm_throttle_program()
1912 if (ts->soc->use_ccroc) in soctherm_throttle_program()
1920 writel(r, ts->regs + THROT_PRIORITY_CTRL(throt)); in soctherm_throttle_program()
1923 writel(r, ts->regs + THROT_DELAY_CTRL(throt)); in soctherm_throttle_program()
1925 r = readl(ts->regs + THROT_PRIORITY_LOCK); in soctherm_throttle_program()
1931 writel(r, ts->regs + THROT_PRIORITY_LOCK); in soctherm_throttle_program()
1941 if (ts->soc->use_ccroc) { in tegra_soctherm_throttle()
1947 /* Thermal HW throttle programming */ in tegra_soctherm_throttle()
1952 if (ts->soc->use_ccroc) { in tegra_soctherm_throttle()
1959 writel(v, ts->regs + THROT_GLOBAL_CFG); in tegra_soctherm_throttle()
1961 v = readl(ts->clk_regs + CAR_SUPER_CCLKG_DIVIDER); in tegra_soctherm_throttle()
1963 writel(v, ts->clk_regs + CAR_SUPER_CCLKG_DIVIDER); in tegra_soctherm_throttle()
1969 writel(v, ts->regs + THERMCTL_STATS_CTL); in tegra_soctherm_throttle()
1975 struct device_node *np = pdev->dev.of_node; in soctherm_interrupts_init()
1980 dev_err(&pdev->dev, "soctherm_oc_int_init failed\n"); in soctherm_interrupts_init()
1984 tegra->thermal_irq = platform_get_irq(pdev, 0); in soctherm_interrupts_init()
1985 if (tegra->thermal_irq < 0) { in soctherm_interrupts_init()
1986 dev_dbg(&pdev->dev, "get 'thermal_irq' failed.\n"); in soctherm_interrupts_init()
1990 tegra->edp_irq = platform_get_irq(pdev, 1); in soctherm_interrupts_init()
1991 if (tegra->edp_irq < 0) { in soctherm_interrupts_init()
1992 dev_dbg(&pdev->dev, "get 'edp_irq' failed.\n"); in soctherm_interrupts_init()
1996 ret = devm_request_threaded_irq(&pdev->dev, in soctherm_interrupts_init()
1997 tegra->thermal_irq, in soctherm_interrupts_init()
2001 dev_name(&pdev->dev), in soctherm_interrupts_init()
2004 dev_err(&pdev->dev, "request_irq 'thermal_irq' failed.\n"); in soctherm_interrupts_init()
2008 ret = devm_request_threaded_irq(&pdev->dev, in soctherm_interrupts_init()
2009 tegra->edp_irq, in soctherm_interrupts_init()
2016 dev_err(&pdev->dev, "request_irq 'edp_irq' failed.\n"); in soctherm_interrupts_init()
2026 const struct tegra_tsensor_group **ttgs = tegra->soc->ttgs; in soctherm_init()
2031 for (i = 0; i < tegra->soc->num_tsensors; ++i) in soctherm_init()
2035 pdiv = readl(tegra->regs + SENSOR_PDIV); in soctherm_init()
2036 hotspot = readl(tegra->regs + SENSOR_HOTSPOT_OFF); in soctherm_init()
2037 for (i = 0; i < tegra->soc->num_ttgs; ++i) { in soctherm_init()
2038 pdiv = REG_SET_MASK(pdiv, ttgs[i]->pdiv_mask, in soctherm_init()
2039 ttgs[i]->pdiv); in soctherm_init()
2041 if (ttgs[i]->id == TEGRA124_SOCTHERM_SENSOR_PLLX) in soctherm_init()
2044 ttgs[i]->pllx_hotspot_mask, in soctherm_init()
2045 ttgs[i]->pllx_hotspot_diff); in soctherm_init()
2047 writel(pdiv, tegra->regs + SENSOR_PDIV); in soctherm_init()
2048 writel(hotspot, tegra->regs + SENSOR_HOTSPOT_OFF); in soctherm_init()
2050 /* Configure hw throttle */ in soctherm_init()
2051 tegra_soctherm_throttle(&pdev->dev); in soctherm_init()
2057 .compatible = "nvidia,tegra124-soctherm",
2063 .compatible = "nvidia,tegra132-soctherm",
2069 .compatible = "nvidia,tegra210-soctherm",
2087 match = of_match_node(tegra_soctherm_of_match, pdev->dev.of_node); in tegra_soctherm_probe()
2089 return -ENODEV; in tegra_soctherm_probe()
2091 soc = (struct tegra_soctherm_soc *)match->data; in tegra_soctherm_probe()
2092 if (soc->num_ttgs > TEGRA124_SOCTHERM_SENSOR_NUM) in tegra_soctherm_probe()
2093 return -EINVAL; in tegra_soctherm_probe()
2095 tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL); in tegra_soctherm_probe()
2097 return -ENOMEM; in tegra_soctherm_probe()
2099 mutex_init(&tegra->thermctl_lock); in tegra_soctherm_probe()
2100 dev_set_drvdata(&pdev->dev, tegra); in tegra_soctherm_probe()
2102 tegra->soc = soc; in tegra_soctherm_probe()
2104 tegra->regs = devm_platform_ioremap_resource_byname(pdev, "soctherm-reg"); in tegra_soctherm_probe()
2105 if (IS_ERR(tegra->regs)) { in tegra_soctherm_probe()
2106 dev_err(&pdev->dev, "can't get soctherm registers"); in tegra_soctherm_probe()
2107 return PTR_ERR(tegra->regs); in tegra_soctherm_probe()
2110 if (!tegra->soc->use_ccroc) { in tegra_soctherm_probe()
2111 tegra->clk_regs = devm_platform_ioremap_resource_byname(pdev, "car-reg"); in tegra_soctherm_probe()
2112 if (IS_ERR(tegra->clk_regs)) { in tegra_soctherm_probe()
2113 dev_err(&pdev->dev, "can't get car clk registers"); in tegra_soctherm_probe()
2114 return PTR_ERR(tegra->clk_regs); in tegra_soctherm_probe()
2117 tegra->ccroc_regs = devm_platform_ioremap_resource_byname(pdev, "ccroc-reg"); in tegra_soctherm_probe()
2118 if (IS_ERR(tegra->ccroc_regs)) { in tegra_soctherm_probe()
2119 dev_err(&pdev->dev, "can't get ccroc registers"); in tegra_soctherm_probe()
2120 return PTR_ERR(tegra->ccroc_regs); in tegra_soctherm_probe()
2124 tegra->reset = devm_reset_control_get(&pdev->dev, "soctherm"); in tegra_soctherm_probe()
2125 if (IS_ERR(tegra->reset)) { in tegra_soctherm_probe()
2126 dev_err(&pdev->dev, "can't get soctherm reset\n"); in tegra_soctherm_probe()
2127 return PTR_ERR(tegra->reset); in tegra_soctherm_probe()
2130 tegra->clock_tsensor = devm_clk_get(&pdev->dev, "tsensor"); in tegra_soctherm_probe()
2131 if (IS_ERR(tegra->clock_tsensor)) { in tegra_soctherm_probe()
2132 dev_err(&pdev->dev, "can't get tsensor clock\n"); in tegra_soctherm_probe()
2133 return PTR_ERR(tegra->clock_tsensor); in tegra_soctherm_probe()
2136 tegra->clock_soctherm = devm_clk_get(&pdev->dev, "soctherm"); in tegra_soctherm_probe()
2137 if (IS_ERR(tegra->clock_soctherm)) { in tegra_soctherm_probe()
2138 dev_err(&pdev->dev, "can't get soctherm clock\n"); in tegra_soctherm_probe()
2139 return PTR_ERR(tegra->clock_soctherm); in tegra_soctherm_probe()
2142 tegra->calib = devm_kcalloc(&pdev->dev, in tegra_soctherm_probe()
2143 soc->num_tsensors, sizeof(u32), in tegra_soctherm_probe()
2145 if (!tegra->calib) in tegra_soctherm_probe()
2146 return -ENOMEM; in tegra_soctherm_probe()
2149 err = tegra_calc_shared_calib(soc->tfuse, &shared_calib); in tegra_soctherm_probe()
2154 for (i = 0; i < soc->num_tsensors; ++i) { in tegra_soctherm_probe()
2155 err = tegra_calc_tsensor_calib(&soc->tsensors[i], in tegra_soctherm_probe()
2157 &tegra->calib[i]); in tegra_soctherm_probe()
2162 tegra->thermctl_tzs = devm_kcalloc(&pdev->dev, in tegra_soctherm_probe()
2163 soc->num_ttgs, sizeof(z), in tegra_soctherm_probe()
2165 if (!tegra->thermctl_tzs) in tegra_soctherm_probe()
2166 return -ENOMEM; in tegra_soctherm_probe()
2178 for (i = 0; i < soc->num_ttgs; ++i) { in tegra_soctherm_probe()
2180 devm_kzalloc(&pdev->dev, sizeof(*zone), GFP_KERNEL); in tegra_soctherm_probe()
2182 err = -ENOMEM; in tegra_soctherm_probe()
2186 zone->reg = tegra->regs + soc->ttgs[i]->sensor_temp_offset; in tegra_soctherm_probe()
2187 zone->dev = &pdev->dev; in tegra_soctherm_probe()
2188 zone->sg = soc->ttgs[i]; in tegra_soctherm_probe()
2189 zone->ts = tegra; in tegra_soctherm_probe()
2191 z = devm_thermal_of_zone_register(&pdev->dev, in tegra_soctherm_probe()
2192 soc->ttgs[i]->id, zone, in tegra_soctherm_probe()
2196 dev_err(&pdev->dev, "failed to register sensor: %d\n", in tegra_soctherm_probe()
2201 zone->tz = z; in tegra_soctherm_probe()
2202 tegra->thermctl_tzs[soc->ttgs[i]->id] = z; in tegra_soctherm_probe()
2205 err = tegra_soctherm_set_hwtrips(&pdev->dev, soc->ttgs[i], z); in tegra_soctherm_probe()
2226 debugfs_remove_recursive(tegra->debugfs_dir); in tegra_soctherm_remove()
2246 struct tegra_soctherm_soc *soc = tegra->soc; in soctherm_resume()
2251 dev_err(&pdev->dev, in soctherm_resume()
2258 for (i = 0; i < soc->num_ttgs; ++i) { in soctherm_resume()
2261 tz = tegra->thermctl_tzs[soc->ttgs[i]->id]; in soctherm_resume()
2262 err = tegra_soctherm_set_hwtrips(dev, soc->ttgs[i], tz); in soctherm_resume()
2264 dev_err(&pdev->dev, in soctherm_resume()