41 	unsigned long duty;  member
85 	tmp = readl_relaxed(pc->base + pc->data->regs.duty);  in rockchip_pwm_get_state()
107 	unsigned long period, duty;  in rockchip_pwm_config()  local
114 	 * Since period and duty cycle registers have a width of 32  in rockchip_pwm_config()
123 	duty = DIV_ROUND_CLOSEST_ULL(div, pc->data->prescaler * NSEC_PER_SEC);  in rockchip_pwm_config()
126 	 * Lock the period and duty of previous configuration, then  in rockchip_pwm_config()
127 	 * change the duty and period, that would not be effective.  in rockchip_pwm_config()
136 	writel(duty, pc->base + pc->data->regs.duty);  in rockchip_pwm_config()
148 	 * the configuration of duty, period and polarity  in rockchip_pwm_config()
236 		.duty = 0x04,
249 		.duty = 0x08,
263 		.duty = 0x08,
277 		.duty = 0x08,