Lines Matching +full:gpo +full:- +full:config +full:- +full:2
1 // SPDX-License-Identifier: GPL-2.0
16 #include <linux/pinctrl/pinconf-generic.h>
123 raw_spin_lock_irqsave(&gc->bgpio_lock, flags); in npcm_gpio_set()
125 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); in npcm_gpio_set()
133 raw_spin_lock_irqsave(&gc->bgpio_lock, flags); in npcm_gpio_clr()
135 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); in npcm_gpio_clr()
143 ioread32(bank->base + NPCM8XX_GP_N_DIN), in npcmgpio_dbg_show()
144 ioread32(bank->base + NPCM8XX_GP_N_DOUT), in npcmgpio_dbg_show()
145 ioread32(bank->base + NPCM8XX_GP_N_IEM), in npcmgpio_dbg_show()
146 ioread32(bank->base + NPCM8XX_GP_N_OE)); in npcmgpio_dbg_show()
148 ioread32(bank->base + NPCM8XX_GP_N_PU), in npcmgpio_dbg_show()
149 ioread32(bank->base + NPCM8XX_GP_N_PD), in npcmgpio_dbg_show()
150 ioread32(bank->base + NPCM8XX_GP_N_DBNC), in npcmgpio_dbg_show()
151 ioread32(bank->base + NPCM8XX_GP_N_POL)); in npcmgpio_dbg_show()
153 ioread32(bank->base + NPCM8XX_GP_N_EVTYP), in npcmgpio_dbg_show()
154 ioread32(bank->base + NPCM8XX_GP_N_EVBE), in npcmgpio_dbg_show()
155 ioread32(bank->base + NPCM8XX_GP_N_EVEN), in npcmgpio_dbg_show()
156 ioread32(bank->base + NPCM8XX_GP_N_EVST)); in npcmgpio_dbg_show()
158 ioread32(bank->base + NPCM8XX_GP_N_OTYP), in npcmgpio_dbg_show()
159 ioread32(bank->base + NPCM8XX_GP_N_OSRC), in npcmgpio_dbg_show()
160 ioread32(bank->base + NPCM8XX_GP_N_ODSC)); in npcmgpio_dbg_show()
162 ioread32(bank->base + NPCM8XX_GP_N_OBL0), in npcmgpio_dbg_show()
163 ioread32(bank->base + NPCM8XX_GP_N_OBL1), in npcmgpio_dbg_show()
164 ioread32(bank->base + NPCM8XX_GP_N_OBL2), in npcmgpio_dbg_show()
165 ioread32(bank->base + NPCM8XX_GP_N_OBL3)); in npcmgpio_dbg_show()
167 ioread32(bank->base + NPCM8XX_GP_N_SPLCK), in npcmgpio_dbg_show()
168 ioread32(bank->base + NPCM8XX_GP_N_MPLCK)); in npcmgpio_dbg_show()
176 ret = pinctrl_gpio_direction_input(offset + chip->base); in npcmgpio_direction_input()
180 return bank->direction_input(chip, offset); in npcmgpio_direction_input()
189 ret = pinctrl_gpio_direction_output(offset + chip->base); in npcmgpio_direction_output()
193 return bank->direction_output(chip, offset, value); in npcmgpio_direction_output()
201 ret = pinctrl_gpio_request(offset + chip->base); in npcmgpio_gpio_request()
205 return bank->request(chip, offset); in npcmgpio_gpio_request()
210 pinctrl_gpio_free(offset + chip->base); in npcmgpio_gpio_free()
225 sts = ioread32(bank->base + NPCM8XX_GP_N_EVST); in npcmgpio_irq_handler()
226 en = ioread32(bank->base + NPCM8XX_GP_N_EVEN); in npcmgpio_irq_handler()
229 generic_handle_domain_irq(gc->irq.domain, bit); in npcmgpio_irq_handler()
241 npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_EVBE, gpio); in npcmgpio_set_irq_type()
242 npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_POL, gpio); in npcmgpio_set_irq_type()
245 npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_EVBE, gpio); in npcmgpio_set_irq_type()
246 npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_POL, gpio); in npcmgpio_set_irq_type()
249 npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_POL, gpio); in npcmgpio_set_irq_type()
250 npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_EVBE, gpio); in npcmgpio_set_irq_type()
253 npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_POL, gpio); in npcmgpio_set_irq_type()
256 npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_POL, gpio); in npcmgpio_set_irq_type()
259 return -EINVAL; in npcmgpio_set_irq_type()
263 npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_EVTYP, gpio); in npcmgpio_set_irq_type()
266 npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_EVTYP, gpio); in npcmgpio_set_irq_type()
279 iowrite32(BIT(gpio), bank->base + NPCM8XX_GP_N_EVST); in npcmgpio_irq_ack()
288 iowrite32(BIT(gpio), bank->base + NPCM8XX_GP_N_EVENC); in npcmgpio_irq_mask()
297 iowrite32(BIT(gpio), bank->base + NPCM8XX_GP_N_EVENS); in npcmgpio_irq_unmask()
305 /* active-high, input, clear interrupt, enable interrupt */ in npcmgpio_irq_startup()
314 .name = "NPCM8XX-GPIO-IRQ",
453 static const int smb6b_pins[] = { 2, 3 };
473 static const int smb17_pins[] = { 3, 2 };
525 static const int iox1_pins[] = { 0, 1, 2, 3 };
1315 #define GPI BIT(0) /* Not GPO */
1316 #define GPO BIT(1) /* Not GPI */ macro
1317 #define SLEW BIT(2) /* Has Slew Control, NPCM8XX_GP_N_OSRC */
1330 /* PIN FUNCTION 1 FUNCTION 2 FUNCTION 3 FUNCTION 4 FUNCTION 5 FLAGS */
1333 …NPCM8XX_PINCFG(2, iox1, MFSEL1, 30, smb6b, I2CSEGSEL, 24, smb17, MFSEL5, 25, none, NONE, 0, none,…
1357 …NPCM8XX_PINCFG(26, smb5, MFSEL1, 2, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0,…
1358 …NPCM8XX_PINCFG(27, smb5, MFSEL1, 2, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0,…
1373 …, MFSEL1, 9, cp1utxd, MFSEL6, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(2, 4) | GPO),
1374 …(43, uart1, MFSEL1, 10, bmcuart1, MFSEL3, 24, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1375 …b, MFSEL1, 28, nbu1crts, MFSEL6, 15, jtag2, MFSEL4, 0, tp_jtag3, MFSEL7, 13, j2j3, MFSEL5, 2, GPO),
1376 …45, hsi1c, MFSEL1, 4, jtag2, MFSEL4, 0, j2j3, MFSEL5, 2, tp_jtag3, MFSEL7, 13, none, NONE, 0, GPO…
1377 …46, hsi1c, MFSEL1, 4, jtag2, MFSEL4, 0, j2j3, MFSEL5, 2, tp_jtag3, MFSEL7, 13, none, NONE, 0, GPO…
1378 …(47, hsi1c, MFSEL1, 4, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(2, 8)),
1379 …(48, hsi2a, MFSEL1, 11, bmcuart0b, MFSEL4, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1380 …(49, hsi2a, MFSEL1, 11, bmcuart0b, MFSEL4, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1381 …(50, hsi2b, MFSEL1, 29, bu6, MFSEL5, 6, tp_uart, MFSEL7, 12, none, NONE, 0, none, NONE, 0, GPO),
1382 …(51, hsi2b, MFSEL1, 29, bu6, MFSEL5, 6, tp_uart, MFSEL7, 12, none, NONE, 0, none, NONE, 0, GPO),
1383 …PINCFG(52, hsi2c, MFSEL1, 5, bu5, MFSEL5, 7, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1384 …PINCFG(53, hsi2c, MFSEL1, 5, bu5, MFSEL5, 7, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1385 …PINCFG(54, hsi2c, MFSEL1, 5, bu4, MFSEL5, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1386 …PINCFG(55, hsi2c, MFSEL1, 5, bu4, MFSEL5, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1387 …NCFG(56, r1err, MFSEL1, 12, r1oen, MFSEL5, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1388 …1md, MFSEL1, 13, tpgpio4b, MFSEL5, 20, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(2, 4)),
1389 …1md, MFSEL1, 13, tpgpio5b, MFSEL5, 22, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(2, 4)),
1392 …_PINCFG(61, hsi1c, MFSEL1, 4, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1393 …hsi1b, MFSEL1, 28, jtag2, MFSEL4, 0, j2j3, MFSEL5, 2, nbu1crts, MFSEL6, 15, tp_jtag3, MFSEL7, 13, …
1394 …(63, hsi1a, MFSEL1, 10, bmcuart1, MFSEL3, 24, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1395 …PINCFG(64, fanin0, MFSEL2, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1396 …PINCFG(65, fanin1, MFSEL2, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1397 …NPCM8XX_PINCFG(66, fanin2, MFSEL2, 2, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, …
1398 …PINCFG(67, fanin3, MFSEL2, 3, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1399 …PINCFG(68, fanin4, MFSEL2, 4, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1400 …PINCFG(69, fanin5, MFSEL2, 5, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1401 …PINCFG(70, fanin6, MFSEL2, 6, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1402 …PINCFG(71, fanin7, MFSEL2, 7, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1403 …PINCFG(72, fanin8, MFSEL2, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1404 …PINCFG(73, fanin9, MFSEL2, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1405 …NCFG(74, fanin10, MFSEL2, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1406 …NCFG(75, fanin11, MFSEL2, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1407 …NCFG(76, fanin12, MFSEL2, 12, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1408 …NCFG(77, fanin13, MFSEL2, 13, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1409 …NCFG(78, fanin14, MFSEL2, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1410 …NCFG(79, fanin15, MFSEL2, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1418 …X_PINCFG(87, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1419 …X_PINCFG(88, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1420 …X_PINCFG(89, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1421 …CFG(90, r2err, MFSEL1, 15, r2oen, MFSEL5, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1422 … MFSEL1, 16, cp1gpio6, MFSEL6, 8, tp_gpio0, MFSEL7, 0, none, NONE, 0, none, NONE, 0, DSTR(2, 4)),
1423 … MFSEL1, 16, cp1gpio7, MFSEL6, 9, tp_gpio1, MFSEL7, 1, none, NONE, 0, none, NONE, 0, DSTR(2, 4)),
1432 …NPCM8XX_PINCFG(101, bu5b, MFSEL5, 12, cp1gpio2c, MFSEL6, 29, tp_gpio2, MFSEL7, 2, none, NONE, 0, …
1504 …NPCM8XX_PINCFG(173, smb7, MFSEL3, 2, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0…
1505 …NPCM8XX_PINCFG(174, smb7, MFSEL3, 2, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0…
1512 …X_PINCFG(181, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1513 …X_PINCFG(182, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1521 …nprd_smi, FLOCKR1, 20, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(2, 4)),
1529 …NPCM8XX_PINCFG(198, smb0d, I2CSEGSEL, 2, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NO…
1530 …NPCM8XX_PINCFG(199, smb0d, I2CSEGSEL, 2, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NO…
1531 …_PINCFG(200, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1532 …X_PINCFG(201, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1553 … NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO | DSTR(8, 12) | SLE…
1556 …SEL4, 27, fm2, MFSEL6, 18, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO | DSTR(8, 12) | SLE…
1557 …SEL4, 27, fm2, MFSEL6, 18, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO | DSTR(8, 12) | SLE…
1581 PINCTRL_PIN(2, "GPIO2/IOX1_CK/SMB6B_SDA/SMB17_SDA"),
1831 if (mode == fn_gpio || cfg->fn0 == mode || cfg->fn1 == mode || in npcm8xx_setfunc()
1832 cfg->fn2 == mode || cfg->fn3 == mode || cfg->fn4 == mode) { in npcm8xx_setfunc()
1833 if (cfg->reg0) in npcm8xx_setfunc()
1834 regmap_update_bits(gcr_regmap, cfg->reg0, in npcm8xx_setfunc()
1835 BIT(cfg->bit0), in npcm8xx_setfunc()
1836 (cfg->fn0 == mode) ? in npcm8xx_setfunc()
1837 BIT(cfg->bit0) : 0); in npcm8xx_setfunc()
1838 if (cfg->reg1) in npcm8xx_setfunc()
1839 regmap_update_bits(gcr_regmap, cfg->reg1, in npcm8xx_setfunc()
1840 BIT(cfg->bit1), in npcm8xx_setfunc()
1841 (cfg->fn1 == mode) ? in npcm8xx_setfunc()
1842 BIT(cfg->bit1) : 0); in npcm8xx_setfunc()
1843 if (cfg->reg2) in npcm8xx_setfunc()
1844 regmap_update_bits(gcr_regmap, cfg->reg2, in npcm8xx_setfunc()
1845 BIT(cfg->bit2), in npcm8xx_setfunc()
1846 (cfg->fn2 == mode) ? in npcm8xx_setfunc()
1847 BIT(cfg->bit2) : 0); in npcm8xx_setfunc()
1848 if (cfg->reg3) in npcm8xx_setfunc()
1849 regmap_update_bits(gcr_regmap, cfg->reg3, in npcm8xx_setfunc()
1850 BIT(cfg->bit3), in npcm8xx_setfunc()
1851 (cfg->fn3 == mode) ? in npcm8xx_setfunc()
1852 BIT(cfg->bit3) : 0); in npcm8xx_setfunc()
1853 if (cfg->reg4) in npcm8xx_setfunc()
1854 regmap_update_bits(gcr_regmap, cfg->reg4, in npcm8xx_setfunc()
1855 BIT(cfg->bit4), in npcm8xx_setfunc()
1856 (cfg->fn4 == mode) ? in npcm8xx_setfunc()
1857 BIT(cfg->bit4) : 0); in npcm8xx_setfunc()
1865 int gpio = pin % bank->gc.ngpio; in npcm8xx_get_slew_rate()
1870 return ioread32(bank->base + NPCM8XX_GP_N_OSRC) & pinmask; in npcm8xx_get_slew_rate()
1877 return -EINVAL; in npcm8xx_get_slew_rate()
1884 void __iomem *OSRC_Offset = bank->base + NPCM8XX_GP_N_OSRC; in npcm8xx_set_slew_rate()
1885 int gpio = BIT(pin % bank->gc.ngpio); in npcm8xx_set_slew_rate()
1890 npcm_gpio_clr(&bank->gc, OSRC_Offset, gpio); in npcm8xx_set_slew_rate()
1893 npcm_gpio_set(&bank->gc, OSRC_Offset, gpio); in npcm8xx_set_slew_rate()
1896 return -EINVAL; in npcm8xx_set_slew_rate()
1901 return -EINVAL; in npcm8xx_set_slew_rate()
1913 return -EINVAL; in npcm8xx_set_slew_rate()
1924 &npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK]; in npcm8xx_get_drive_strength()
1925 int gpio = pin % bank->gc.ngpio; in npcm8xx_get_drive_strength()
1932 return -EINVAL; in npcm8xx_get_drive_strength()
1934 val = ioread32(bank->base + NPCM8XX_GP_N_ODSC) & pinmask; in npcm8xx_get_drive_strength()
1936 dev_dbg(bank->gc.parent, "pin %d strength %d = %d\n", pin, val, ds); in npcm8xx_get_drive_strength()
1945 &npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK]; in npcm8xx_set_drive_strength()
1946 int gpio = BIT(pin % bank->gc.ngpio); in npcm8xx_set_drive_strength()
1952 npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_ODSC, gpio); in npcm8xx_set_drive_strength()
1954 npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_ODSC, gpio); in npcm8xx_set_drive_strength()
1956 return -ENOTSUPP; in npcm8xx_set_drive_strength()
2036 npcm8xx_setfunc(npcm->gcr_regmap, npcm8xx_pingroups[group].pins, in npcm8xx_pinmux_set_mux()
2053 npcm8xx_setfunc(npcm->gcr_regmap, &offset, 1, mode); in npcm8xx_gpio_request_enable()
2065 virq = irq_find_mapping(npcm->domain, offset); in npcm8xx_gpio_request_free()
2076 &npcm->gpio_bank[offset / NPCM8XX_GPIO_PER_BANK]; in npcm_gpio_set_direction()
2077 int gpio = BIT(offset % bank->gc.ngpio); in npcm_gpio_set_direction()
2080 iowrite32(gpio, bank->base + NPCM8XX_GP_N_OEC); in npcm_gpio_set_direction()
2082 iowrite32(gpio, bank->base + NPCM8XX_GP_N_OES); in npcm_gpio_set_direction()
2100 void __iomem *DBNCS_offset = bank->base + NPCM8XX_GP_N_DBNCS0 + (gpio / 4); in debounce_timing_setting()
2101 int gpio_debounce = (gpio % 16) * 2, debounce_select, i; in debounce_timing_setting()
2105 if (bank->debounce.set_val[i]) { in debounce_timing_setting()
2106 if (bank->debounce.nanosec_val[i] == nanosecs) { in debounce_timing_setting()
2108 npcm_gpio_set(&bank->gc, DBNCS_offset, in debounce_timing_setting()
2113 bank->debounce.set_val[i] = true; in debounce_timing_setting()
2114 bank->debounce.nanosec_val[i] = nanosecs; in debounce_timing_setting()
2116 npcm_gpio_set(&bank->gc, DBNCS_offset, debounce_select); in debounce_timing_setting()
2119 iowrite32(0, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4)); in debounce_timing_setting()
2122 iowrite32(0x10, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4)); in debounce_timing_setting()
2125 iowrite32(0x20, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4)); in debounce_timing_setting()
2128 iowrite32(0x30, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4)); in debounce_timing_setting()
2131 iowrite32(0x40, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4)); in debounce_timing_setting()
2134 iowrite32(0x50, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4)); in debounce_timing_setting()
2137 iowrite32(0x60, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4)); in debounce_timing_setting()
2140 iowrite32(0x70, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4)); in debounce_timing_setting()
2145 return -ENOTSUPP; in debounce_timing_setting()
2147 if (dbncp_val_mod > GENMASK(2, 0)) in debounce_timing_setting()
2150 bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4)); in debounce_timing_setting()
2158 return -ENOTSUPP; in debounce_timing_setting()
2167 &npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK]; in npcm_set_debounce()
2168 int gpio = BIT(pin % bank->gc.ngpio); in npcm_set_debounce()
2172 ret = debounce_timing_setting(bank, pin % bank->gc.ngpio, in npcm_set_debounce()
2175 …dev_err(npcm->dev, "Pin %d, All four debounce timing values are used, please use one of exist debo… in npcm_set_debounce()
2177 npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_DBNC, in npcm_set_debounce()
2182 npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_DBNC, gpio); in npcm_set_debounce()
2189 unsigned long *config) in npcm8xx_config_get() argument
2191 enum pin_config_param param = pinconf_to_config_param(*config); in npcm8xx_config_get()
2194 &npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK]; in npcm8xx_config_get()
2195 int gpio = pin % bank->gc.ngpio; in npcm8xx_config_get()
2204 pu = ioread32(bank->base + NPCM8XX_GP_N_PU) & pinmask; in npcm8xx_config_get()
2205 pd = ioread32(bank->base + NPCM8XX_GP_N_PD) & pinmask; in npcm8xx_config_get()
2215 ie = ioread32(bank->base + NPCM8XX_GP_N_IEM) & pinmask; in npcm8xx_config_get()
2216 oe = ioread32(bank->base + NPCM8XX_GP_N_OE) & pinmask; in npcm8xx_config_get()
2223 rc = !(ioread32(bank->base + NPCM8XX_GP_N_OTYP) & pinmask); in npcm8xx_config_get()
2226 rc = ioread32(bank->base + NPCM8XX_GP_N_OTYP) & pinmask; in npcm8xx_config_get()
2229 rc = ioread32(bank->base + NPCM8XX_GP_N_DBNC) & pinmask; in npcm8xx_config_get()
2234 *config = pinconf_to_config_packed(param, rc); in npcm8xx_config_get()
2237 rc = npcm8xx_get_slew_rate(bank, npcm->gcr_regmap, pin); in npcm8xx_config_get()
2239 *config = pinconf_to_config_packed(param, rc); in npcm8xx_config_get()
2242 return -ENOTSUPP; in npcm8xx_config_get()
2246 return -EINVAL; in npcm8xx_config_get()
2252 unsigned int pin, unsigned long config) in npcm8xx_config_set_one() argument
2254 enum pin_config_param param = pinconf_to_config_param(config); in npcm8xx_config_set_one()
2256 &npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK]; in npcm8xx_config_set_one()
2257 u32 arg = pinconf_to_config_argument(config); in npcm8xx_config_set_one()
2258 int gpio = BIT(pin % bank->gc.ngpio); in npcm8xx_config_set_one()
2262 npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_PU, gpio); in npcm8xx_config_set_one()
2263 npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_PD, gpio); in npcm8xx_config_set_one()
2266 npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_PU, gpio); in npcm8xx_config_set_one()
2267 npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_PD, gpio); in npcm8xx_config_set_one()
2270 npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_PD, gpio); in npcm8xx_config_set_one()
2271 npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_PU, gpio); in npcm8xx_config_set_one()
2274 iowrite32(gpio, bank->base + NPCM8XX_GP_N_OEC); in npcm8xx_config_set_one()
2275 bank->direction_input(&bank->gc, pin % bank->gc.ngpio); in npcm8xx_config_set_one()
2278 bank->direction_output(&bank->gc, pin % bank->gc.ngpio, arg); in npcm8xx_config_set_one()
2279 iowrite32(gpio, bank->base + NPCM8XX_GP_N_OES); in npcm8xx_config_set_one()
2282 npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_OTYP, gpio); in npcm8xx_config_set_one()
2285 npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_OTYP, gpio); in npcm8xx_config_set_one()
2290 return npcm8xx_set_slew_rate(bank, npcm->gcr_regmap, pin, arg); in npcm8xx_config_set_one()
2294 return -ENOTSUPP; in npcm8xx_config_set_one()
2306 while (num_configs--) { in npcm8xx_config_set()
2323 .name = "npcm8xx-pinctrl",
2336 return gpiochip_add_pin_range(&bank->gc, dev_name(chip->parent), in npcmgpio_add_pin_ranges()
2337 bank->pinctrl_id, bank->gc.base, in npcmgpio_add_pin_ranges()
2338 bank->gc.ngpio); in npcmgpio_add_pin_ranges()
2344 struct device *dev = pctrl->dev; in npcm8xx_gpio_fw()
2346 int ret = -ENXIO; in npcm8xx_gpio_fw()
2350 pctrl->gpio_bank[id].base = fwnode_iomap(child, 0); in npcm8xx_gpio_fw()
2351 if (!pctrl->gpio_bank[id].base) in npcm8xx_gpio_fw()
2352 return dev_err_probe(dev, -ENXIO, "fwnode_iomap id %d failed\n", id); in npcm8xx_gpio_fw()
2354 ret = bgpio_init(&pctrl->gpio_bank[id].gc, dev, 4, in npcm8xx_gpio_fw()
2355 pctrl->gpio_bank[id].base + NPCM8XX_GP_N_DIN, in npcm8xx_gpio_fw()
2356 pctrl->gpio_bank[id].base + NPCM8XX_GP_N_DOUT, in npcm8xx_gpio_fw()
2359 pctrl->gpio_bank[id].base + NPCM8XX_GP_N_IEM, in npcm8xx_gpio_fw()
2364 ret = fwnode_property_get_reference_args(child, "gpio-ranges", NULL, 3, 0, &args); in npcm8xx_gpio_fw()
2366 return dev_err_probe(dev, ret, "gpio-ranges fail for GPIO bank %u\n", id); in npcm8xx_gpio_fw()
2372 pctrl->gpio_bank[id].irq = ret; in npcm8xx_gpio_fw()
2373 pctrl->gpio_bank[id].irq_chip = npcmgpio_irqchip; in npcm8xx_gpio_fw()
2374 pctrl->gpio_bank[id].irqbase = id * NPCM8XX_GPIO_PER_BANK; in npcm8xx_gpio_fw()
2375 pctrl->gpio_bank[id].pinctrl_id = args.args[0]; in npcm8xx_gpio_fw()
2376 pctrl->gpio_bank[id].gc.base = -1; in npcm8xx_gpio_fw()
2377 pctrl->gpio_bank[id].gc.ngpio = args.args[2]; in npcm8xx_gpio_fw()
2378 pctrl->gpio_bank[id].gc.owner = THIS_MODULE; in npcm8xx_gpio_fw()
2379 pctrl->gpio_bank[id].gc.parent = dev; in npcm8xx_gpio_fw()
2380 pctrl->gpio_bank[id].gc.fwnode = child; in npcm8xx_gpio_fw()
2381 pctrl->gpio_bank[id].gc.label = devm_kasprintf(dev, GFP_KERNEL, "%pfw", child); in npcm8xx_gpio_fw()
2382 pctrl->gpio_bank[id].gc.dbg_show = npcmgpio_dbg_show; in npcm8xx_gpio_fw()
2383 pctrl->gpio_bank[id].direction_input = pctrl->gpio_bank[id].gc.direction_input; in npcm8xx_gpio_fw()
2384 pctrl->gpio_bank[id].gc.direction_input = npcmgpio_direction_input; in npcm8xx_gpio_fw()
2385 pctrl->gpio_bank[id].direction_output = pctrl->gpio_bank[id].gc.direction_output; in npcm8xx_gpio_fw()
2386 pctrl->gpio_bank[id].gc.direction_output = npcmgpio_direction_output; in npcm8xx_gpio_fw()
2387 pctrl->gpio_bank[id].request = pctrl->gpio_bank[id].gc.request; in npcm8xx_gpio_fw()
2388 pctrl->gpio_bank[id].gc.request = npcmgpio_gpio_request; in npcm8xx_gpio_fw()
2389 pctrl->gpio_bank[id].gc.free = npcmgpio_gpio_free; in npcm8xx_gpio_fw()
2391 pctrl->gpio_bank[id].debounce.set_val[i] = false; in npcm8xx_gpio_fw()
2392 pctrl->gpio_bank[id].gc.add_pin_ranges = npcmgpio_add_pin_ranges; in npcm8xx_gpio_fw()
2396 pctrl->bank_num = id; in npcm8xx_gpio_fw()
2404 for (id = 0 ; id < pctrl->bank_num ; id++) { in npcm8xx_gpio_register()
2407 girq = &pctrl->gpio_bank[id].gc.irq; in npcm8xx_gpio_register()
2408 girq->chip = &pctrl->gpio_bank[id].irq_chip; in npcm8xx_gpio_register()
2409 girq->parent_handler = npcmgpio_irq_handler; in npcm8xx_gpio_register()
2410 girq->num_parents = 1; in npcm8xx_gpio_register()
2411 girq->parents = devm_kcalloc(pctrl->dev, girq->num_parents, in npcm8xx_gpio_register()
2412 sizeof(*girq->parents), in npcm8xx_gpio_register()
2414 if (!girq->parents) in npcm8xx_gpio_register()
2415 return -ENOMEM; in npcm8xx_gpio_register()
2417 girq->parents[0] = pctrl->gpio_bank[id].irq; in npcm8xx_gpio_register()
2418 girq->default_type = IRQ_TYPE_NONE; in npcm8xx_gpio_register()
2419 girq->handler = handle_level_irq; in npcm8xx_gpio_register()
2420 ret = devm_gpiochip_add_data(pctrl->dev, in npcm8xx_gpio_register()
2421 &pctrl->gpio_bank[id].gc, in npcm8xx_gpio_register()
2422 &pctrl->gpio_bank[id]); in npcm8xx_gpio_register()
2424 return dev_err_probe(pctrl->dev, ret, "Failed to add GPIO chip %u\n", id); in npcm8xx_gpio_register()
2432 struct device *dev = &pdev->dev; in npcm8xx_pinctrl_probe()
2438 return -ENOMEM; in npcm8xx_pinctrl_probe()
2440 pctrl->dev = dev; in npcm8xx_pinctrl_probe()
2443 pctrl->gcr_regmap = in npcm8xx_pinctrl_probe()
2444 syscon_regmap_lookup_by_phandle(dev->of_node, "nuvoton,sysgcr"); in npcm8xx_pinctrl_probe()
2445 if (IS_ERR(pctrl->gcr_regmap)) in npcm8xx_pinctrl_probe()
2446 return dev_err_probe(dev, PTR_ERR(pctrl->gcr_regmap), in npcm8xx_pinctrl_probe()
2452 "Failed to gpio dt-binding\n"); in npcm8xx_pinctrl_probe()
2454 pctrl->pctldev = devm_pinctrl_register(dev, &npcm8xx_pinctrl_desc, pctrl); in npcm8xx_pinctrl_probe()
2455 if (IS_ERR(pctrl->pctldev)) in npcm8xx_pinctrl_probe()
2456 return dev_err_probe(dev, PTR_ERR(pctrl->pctldev), in npcm8xx_pinctrl_probe()
2467 { .compatible = "nuvoton,npcm845-pinctrl" },
2475 .name = "npcm8xx-pinctrl",