21 static bool riscv_perf_user_access(struct perf_event *event)  in riscv_perf_user_access()  argument
23 	return ((event->attr.type == PERF_TYPE_HARDWARE) ||  in riscv_perf_user_access()
24 		(event->attr.type == PERF_TYPE_HW_CACHE) ||  in riscv_perf_user_access()
25 		(event->attr.type == PERF_TYPE_RAW)) &&  in riscv_perf_user_access()
26 		!!(event->hw.flags & PERF_EVENT_FLAG_USER_READ_CNT) &&  in riscv_perf_user_access()
27 		(event->hw.idx != -1);  in riscv_perf_user_access()
30 void arch_perf_update_userpage(struct perf_event *event,  in arch_perf_update_userpage()  argument
40 	userpg->cap_user_rdpmc = riscv_perf_user_access(event);  in arch_perf_update_userpage()
49 		userpg->pmc_width = to_riscv_pmu(event->pmu)->ctr_get_width(event->hw.idx) + 1;  in arch_perf_update_userpage()
147 u64 riscv_pmu_ctr_get_width_mask(struct perf_event *event)  in riscv_pmu_ctr_get_width_mask()  argument
150 	struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);  in riscv_pmu_ctr_get_width_mask()
151 	struct hw_perf_event *hwc = &event->hw;  in riscv_pmu_ctr_get_width_mask()
162 u64 riscv_pmu_event_update(struct perf_event *event)  in riscv_pmu_event_update()  argument
164 	struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);  in riscv_pmu_event_update()
165 	struct hw_perf_event *hwc = &event->hw;  in riscv_pmu_event_update()
173 	cmask = riscv_pmu_ctr_get_width_mask(event);  in riscv_pmu_event_update()
177 		new_raw_count = rvpmu->ctr_read(event);  in riscv_pmu_event_update()
183 	local64_add(delta, &event->count);  in riscv_pmu_event_update()
189 void riscv_pmu_stop(struct perf_event *event, int flags)  in riscv_pmu_stop()  argument
191 	struct hw_perf_event *hwc = &event->hw;  in riscv_pmu_stop()
192 	struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);  in riscv_pmu_stop()
198 			rvpmu->ctr_stop(event, 0);  in riscv_pmu_stop()
201 		riscv_pmu_event_update(event);  in riscv_pmu_stop()
206 int riscv_pmu_event_set_period(struct perf_event *event)  in riscv_pmu_event_set_period()  argument
208 	struct hw_perf_event *hwc = &event->hw;  in riscv_pmu_event_set_period()
212 	uint64_t max_period = riscv_pmu_ctr_get_width_mask(event);  in riscv_pmu_event_set_period()
239 	perf_event_update_userpage(event);  in riscv_pmu_event_set_period()
244 void riscv_pmu_start(struct perf_event *event, int flags)  in riscv_pmu_start()  argument
246 	struct hw_perf_event *hwc = &event->hw;  in riscv_pmu_start()
247 	struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);  in riscv_pmu_start()
248 	uint64_t max_period = riscv_pmu_ctr_get_width_mask(event);  in riscv_pmu_start()
252 		WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));  in riscv_pmu_start()
255 	riscv_pmu_event_set_period(event);  in riscv_pmu_start()
257 	rvpmu->ctr_start(event, init_val);  in riscv_pmu_start()
258 	perf_event_update_userpage(event);  in riscv_pmu_start()
261 static int riscv_pmu_add(struct perf_event *event, int flags)  in riscv_pmu_add()  argument
263 	struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);  in riscv_pmu_add()
265 	struct hw_perf_event *hwc = &event->hw;  in riscv_pmu_add()
268 	idx = rvpmu->ctr_get_idx(event);  in riscv_pmu_add()
273 	cpuc->events[idx] = event;  in riscv_pmu_add()
277 		riscv_pmu_start(event, PERF_EF_RELOAD);  in riscv_pmu_add()
280 	perf_event_update_userpage(event);  in riscv_pmu_add()
285 static void riscv_pmu_del(struct perf_event *event, int flags)  in riscv_pmu_del()  argument
287 	struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);  in riscv_pmu_del()
289 	struct hw_perf_event *hwc = &event->hw;  in riscv_pmu_del()
291 	riscv_pmu_stop(event, PERF_EF_UPDATE);  in riscv_pmu_del()
295 		rvpmu->ctr_stop(event, RISCV_PMU_STOP_FLAG_RESET);  in riscv_pmu_del()
298 		rvpmu->ctr_clear_idx(event);  in riscv_pmu_del()
299 	perf_event_update_userpage(event);  in riscv_pmu_del()
303 static void riscv_pmu_read(struct perf_event *event)  in riscv_pmu_read()  argument
305 	riscv_pmu_event_update(event);  in riscv_pmu_read()
308 static int riscv_pmu_event_init(struct perf_event *event)  in riscv_pmu_event_init()  argument
310 	struct hw_perf_event *hwc = &event->hw;  in riscv_pmu_event_init()
311 	struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);  in riscv_pmu_event_init()
317 	if (has_branch_stack(event))  in riscv_pmu_event_init()
321 	mapped_event = rvpmu->event_map(event, &event_config);  in riscv_pmu_event_init()
323 		pr_debug("event %x:%llx not supported\n", event->attr.type,  in riscv_pmu_event_init()
324 			 event->attr.config);  in riscv_pmu_event_init()
339 		rvpmu->event_init(event);  in riscv_pmu_event_init()
341 	if (!is_sampling_event(event)) {  in riscv_pmu_event_init()
348 		cmask = riscv_pmu_ctr_get_width_mask(event);  in riscv_pmu_event_init()
357 static int riscv_pmu_event_idx(struct perf_event *event)  in riscv_pmu_event_idx()  argument
359 	struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);  in riscv_pmu_event_idx()
361 	if (!(event->hw.flags & PERF_EVENT_FLAG_USER_READ_CNT))  in riscv_pmu_event_idx()
365 		return rvpmu->csr_index(event) + 1;  in riscv_pmu_event_idx()
370 static void riscv_pmu_event_mapped(struct perf_event *event, struct mm_struct *mm)  in riscv_pmu_event_mapped()  argument
372 	struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);  in riscv_pmu_event_mapped()
375 		rvpmu->event_mapped(event, mm);  in riscv_pmu_event_mapped()
376 		perf_event_update_userpage(event);  in riscv_pmu_event_mapped()
380 static void riscv_pmu_event_unmapped(struct perf_event *event, struct mm_struct *mm)  in riscv_pmu_event_unmapped()  argument
382 	struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);  in riscv_pmu_event_unmapped()
385 		rvpmu->event_unmapped(event, mm);  in riscv_pmu_event_unmapped()
386 		perf_event_update_userpage(event);  in riscv_pmu_event_unmapped()