22 #define DP83867_DEVADDR		0x1f  macro
198 	val_rxcfg = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG);  in dp83867_set_wol()
212 			phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD1,  in dp83867_set_wol()
214 			phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD2,  in dp83867_set_wol()
216 			phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD3,  in dp83867_set_wol()
225 			phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1,  in dp83867_set_wol()
227 			phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP2,  in dp83867_set_wol()
229 			phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP3,  in dp83867_set_wol()
251 	phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG, val_rxcfg);  in dp83867_set_wol()
266 	value = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG);  in dp83867_get_wol()
278 		sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,  in dp83867_get_wol()
283 		sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,  in dp83867_get_wol()
288 		sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,  in dp83867_get_wol()
483 		phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,  in dp83867_config_port_mirroring()
486 		phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,  in dp83867_config_port_mirroring()
499 		const u16 val = phy_read_mmd(phydev, DP83867_DEVADDR,  in dp83867_verify_rgmii_cfg()
682 	delay = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL);  in dp83867_of_init()
760 		phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,  in dp83867_config_init()
763 	bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS2);  in dp83867_config_init()
769 		ret = phy_modify_mmd(phydev, DP83867_DEVADDR,  in dp83867_config_init()
813 		bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1);  in dp83867_config_init()
828 		val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL);  in dp83867_config_init()
840 		phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);  in dp83867_config_init()
849 		phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL,  in dp83867_config_init()
855 		phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,  in dp83867_config_init()
866 		ret = phy_modify_mmd(phydev, DP83867_DEVADDR,  in dp83867_config_init()
877 		ret = phy_modify_mmd(phydev, DP83867_DEVADDR,  in dp83867_config_init()
885 		val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL);  in dp83867_config_init()
894 		phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL, val);  in dp83867_config_init()
901 			phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,  in dp83867_config_init()
928 		phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,  in dp83867_config_init()
954 	err = phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_DSP_FFE_CFG,  in dp83867_phy_reset()