Lines Matching +full:enet +full:- +full:phy +full:- +full:lane +full:- +full:no +full:- +full:swap
1 // SPDX-License-Identifier: GPL-2.0
2 /* Driver for the Texas Instruments DP83867 PHY
12 #include <linux/phy.h>
17 #include <linux/nvmem-consumer.h>
19 #include <dt-bindings/net/ti-dp83867.h>
102 /* PHY CTRL bits */
127 /* PHY STS bits */
194 struct net_device *ndev = phydev->attached_dev; in dp83867_set_wol()
201 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST | in dp83867_set_wol()
206 if (wol->wolopts & WAKE_MAGIC) { in dp83867_set_wol()
207 mac = (const u8 *)ndev->dev_addr; in dp83867_set_wol()
210 return -EINVAL; in dp83867_set_wol()
224 if (wol->wolopts & WAKE_MAGICSECURE) { in dp83867_set_wol()
226 (wol->sopass[1] << 8) | wol->sopass[0]); in dp83867_set_wol()
228 (wol->sopass[3] << 8) | wol->sopass[2]); in dp83867_set_wol()
230 (wol->sopass[5] << 8) | wol->sopass[4]); in dp83867_set_wol()
237 if (wol->wolopts & WAKE_UCAST) in dp83867_set_wol()
242 if (wol->wolopts & WAKE_BCAST) in dp83867_set_wol()
262 wol->supported = (WAKE_UCAST | WAKE_BCAST | WAKE_MAGIC | in dp83867_get_wol()
264 wol->wolopts = 0; in dp83867_get_wol()
269 wol->wolopts |= WAKE_UCAST; in dp83867_get_wol()
272 wol->wolopts |= WAKE_BCAST; in dp83867_get_wol()
275 wol->wolopts |= WAKE_MAGIC; in dp83867_get_wol()
280 wol->sopass[0] = (sopass_val & 0xff); in dp83867_get_wol()
281 wol->sopass[1] = (sopass_val >> 8); in dp83867_get_wol()
285 wol->sopass[2] = (sopass_val & 0xff); in dp83867_get_wol()
286 wol->sopass[3] = (sopass_val >> 8); in dp83867_get_wol()
290 wol->sopass[4] = (sopass_val & 0xff); in dp83867_get_wol()
291 wol->sopass[5] = (sopass_val >> 8); in dp83867_get_wol()
293 wol->wolopts |= WAKE_MAGICSECURE; in dp83867_get_wol()
297 wol->wolopts = 0; in dp83867_get_wol()
304 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in dp83867_config_intr()
371 phydev->duplex = DUPLEX_FULL; in dp83867_read_status()
373 phydev->duplex = DUPLEX_HALF; in dp83867_read_status()
376 phydev->speed = SPEED_1000; in dp83867_read_status()
378 phydev->speed = SPEED_100; in dp83867_read_status()
380 phydev->speed = SPEED_10; in dp83867_read_status()
410 return -EINVAL; in dp83867_get_downshift()
423 return -E2BIG; in dp83867_set_downshift()
445 return -EINVAL; in dp83867_set_downshift()
459 switch (tuna->id) { in dp83867_get_tunable()
463 return -EOPNOTSUPP; in dp83867_get_tunable()
470 switch (tuna->id) { in dp83867_set_tunable()
474 return -EOPNOTSUPP; in dp83867_set_tunable()
480 struct dp83867_private *dp83867 = phydev->priv; in dp83867_config_port_mirroring()
482 if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN) in dp83867_config_port_mirroring()
493 struct dp83867_private *dp83867 = phydev->priv; in dp83867_verify_rgmii_cfg()
496 * mode, but rgmii should have meant no delay. Warn existing users. in dp83867_verify_rgmii_cfg()
498 if (phydev->interface == PHY_INTERFACE_MODE_RGMII) { in dp83867_verify_rgmii_cfg()
509 "PHY has delays via pin strapping, but phy-mode = 'rgmii'\n" in dp83867_verify_rgmii_cfg()
510 "Should be 'rgmii-id' to use internal delays txskew:%x rxskew:%x\n", in dp83867_verify_rgmii_cfg()
515 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || in dp83867_verify_rgmii_cfg()
516 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) && in dp83867_verify_rgmii_cfg()
517 dp83867->rx_id_delay == DP83867_RGMII_RX_CLK_DELAY_INV) { in dp83867_verify_rgmii_cfg()
518 phydev_err(phydev, "ti,rx-internal-delay must be specified\n"); in dp83867_verify_rgmii_cfg()
519 return -EINVAL; in dp83867_verify_rgmii_cfg()
523 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || in dp83867_verify_rgmii_cfg()
524 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) && in dp83867_verify_rgmii_cfg()
525 dp83867->tx_id_delay == DP83867_RGMII_TX_CLK_DELAY_INV) { in dp83867_verify_rgmii_cfg()
526 phydev_err(phydev, "ti,tx-internal-delay must be specified\n"); in dp83867_verify_rgmii_cfg()
527 return -EINVAL; in dp83867_verify_rgmii_cfg()
536 struct dp83867_private *dp83867 = phydev->priv; in dp83867_of_init_io_impedance()
537 struct device *dev = &phydev->mdio.dev; in dp83867_of_init_io_impedance()
538 struct device_node *of_node = dev->of_node; in dp83867_of_init_io_impedance()
546 if (ret != -ENOENT && ret != -EOPNOTSUPP) in dp83867_of_init_io_impedance()
550 /* If no nvmem cell, check for the boolean properties. */ in dp83867_of_init_io_impedance()
551 if (of_property_read_bool(of_node, "ti,max-output-impedance")) in dp83867_of_init_io_impedance()
552 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX; in dp83867_of_init_io_impedance()
553 else if (of_property_read_bool(of_node, "ti,min-output-impedance")) in dp83867_of_init_io_impedance()
554 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN; in dp83867_of_init_io_impedance()
556 dp83867->io_impedance = -1; /* leave at default */ in dp83867_of_init_io_impedance()
572 return -ERANGE; in dp83867_of_init_io_impedance()
574 dp83867->io_impedance = val; in dp83867_of_init_io_impedance()
581 struct dp83867_private *dp83867 = phydev->priv; in dp83867_of_init()
582 struct device *dev = &phydev->mdio.dev; in dp83867_of_init()
583 struct device_node *of_node = dev->of_node; in dp83867_of_init()
587 return -ENODEV; in dp83867_of_init()
590 ret = of_property_read_u32(of_node, "ti,clk-output-sel", in dp83867_of_init()
591 &dp83867->clk_output_sel); in dp83867_of_init()
594 dp83867->set_clk_output = true; in dp83867_of_init()
598 if (dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK && in dp83867_of_init()
599 dp83867->clk_output_sel != DP83867_CLK_O_SEL_OFF) { in dp83867_of_init()
600 phydev_err(phydev, "ti,clk-output-sel value %u out of range\n", in dp83867_of_init()
601 dp83867->clk_output_sel); in dp83867_of_init()
602 return -EINVAL; in dp83867_of_init()
610 dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node, in dp83867_of_init()
611 "ti,dp83867-rxctrl-strap-quirk"); in dp83867_of_init()
613 dp83867->sgmii_ref_clk_en = of_property_read_bool(of_node, in dp83867_of_init()
614 "ti,sgmii-ref-clock-output-enable"); in dp83867_of_init()
616 dp83867->rx_id_delay = DP83867_RGMII_RX_CLK_DELAY_INV; in dp83867_of_init()
617 ret = of_property_read_u32(of_node, "ti,rx-internal-delay", in dp83867_of_init()
618 &dp83867->rx_id_delay); in dp83867_of_init()
619 if (!ret && dp83867->rx_id_delay > DP83867_RGMII_RX_CLK_DELAY_MAX) { in dp83867_of_init()
621 "ti,rx-internal-delay value of %u out of range\n", in dp83867_of_init()
622 dp83867->rx_id_delay); in dp83867_of_init()
623 return -EINVAL; in dp83867_of_init()
626 dp83867->tx_id_delay = DP83867_RGMII_TX_CLK_DELAY_INV; in dp83867_of_init()
627 ret = of_property_read_u32(of_node, "ti,tx-internal-delay", in dp83867_of_init()
628 &dp83867->tx_id_delay); in dp83867_of_init()
629 if (!ret && dp83867->tx_id_delay > DP83867_RGMII_TX_CLK_DELAY_MAX) { in dp83867_of_init()
631 "ti,tx-internal-delay value of %u out of range\n", in dp83867_of_init()
632 dp83867->tx_id_delay); in dp83867_of_init()
633 return -EINVAL; in dp83867_of_init()
636 if (of_property_read_bool(of_node, "enet-phy-lane-swap")) in dp83867_of_init()
637 dp83867->port_mirroring = DP83867_PORT_MIRROING_EN; in dp83867_of_init()
639 if (of_property_read_bool(of_node, "enet-phy-lane-no-swap")) in dp83867_of_init()
640 dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS; in dp83867_of_init()
642 ret = of_property_read_u32(of_node, "ti,fifo-depth", in dp83867_of_init()
643 &dp83867->tx_fifo_depth); in dp83867_of_init()
645 ret = of_property_read_u32(of_node, "tx-fifo-depth", in dp83867_of_init()
646 &dp83867->tx_fifo_depth); in dp83867_of_init()
648 dp83867->tx_fifo_depth = in dp83867_of_init()
652 if (dp83867->tx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) { in dp83867_of_init()
653 phydev_err(phydev, "tx-fifo-depth value %u out of range\n", in dp83867_of_init()
654 dp83867->tx_fifo_depth); in dp83867_of_init()
655 return -EINVAL; in dp83867_of_init()
658 ret = of_property_read_u32(of_node, "rx-fifo-depth", in dp83867_of_init()
659 &dp83867->rx_fifo_depth); in dp83867_of_init()
661 dp83867->rx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB; in dp83867_of_init()
663 if (dp83867->rx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) { in dp83867_of_init()
664 phydev_err(phydev, "rx-fifo-depth value %u out of range\n", in dp83867_of_init()
665 dp83867->rx_fifo_depth); in dp83867_of_init()
666 return -EINVAL; in dp83867_of_init()
674 struct dp83867_private *dp83867 = phydev->priv; in dp83867_of_init()
677 /* For non-OF device, the RX and TX ID values are either strapped in dp83867_of_init()
683 dp83867->rx_id_delay = delay & DP83867_RGMII_RX_CLK_DELAY_MAX; in dp83867_of_init()
684 dp83867->tx_id_delay = (delay >> DP83867_RGMII_TX_CLK_DELAY_SHIFT) & in dp83867_of_init()
687 /* Per datasheet, IO impedance is default to 50-ohm, so we set the in dp83867_of_init()
691 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN / 2; in dp83867_of_init()
693 /* For non-OF device, the RX and TX FIFO depths are taken from in dp83867_of_init()
697 dp83867->tx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB; in dp83867_of_init()
698 dp83867->rx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB; in dp83867_of_init()
706 /* Disable PHY Interrupts */ in dp83867_suspend()
708 phydev->interrupts = PHY_INTERRUPT_DISABLED; in dp83867_suspend()
717 /* Enable PHY Interrupts */ in dp83867_resume()
719 phydev->interrupts = PHY_INTERRUPT_ENABLED; in dp83867_resume()
732 dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867), in dp83867_probe()
735 return -ENOMEM; in dp83867_probe()
737 phydev->priv = dp83867; in dp83867_probe()
744 struct dp83867_private *dp83867 = phydev->priv; in dp83867_config_init()
748 /* Force speed optimization for the PHY even if it strapped */ in dp83867_config_init()
759 if (dp83867->rxctrl_strap_quirk) in dp83867_config_init()
766 * be set to 0x2. This may causes the PHY link to be unstable - in dp83867_config_init()
778 phydev->interface == PHY_INTERFACE_MODE_SGMII) { in dp83867_config_init()
784 val |= (dp83867->tx_fifo_depth << in dp83867_config_init()
787 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { in dp83867_config_init()
789 val |= (dp83867->rx_fifo_depth << in dp83867_config_init()
806 * Such N/A mode enabled by mistake can put PHY IC in some in dp83867_config_init()
821 /* If rgmii mode with no internal delay is selected, we do NOT use in dp83867_config_init()
822 * aligned mode as one might expect. Instead we use the PHY's default in dp83867_config_init()
831 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) in dp83867_config_init()
834 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) in dp83867_config_init()
837 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) in dp83867_config_init()
843 if (dp83867->rx_id_delay != DP83867_RGMII_RX_CLK_DELAY_INV) in dp83867_config_init()
844 delay |= dp83867->rx_id_delay; in dp83867_config_init()
845 if (dp83867->tx_id_delay != DP83867_RGMII_TX_CLK_DELAY_INV) in dp83867_config_init()
846 delay |= dp83867->tx_id_delay << in dp83867_config_init()
854 if (dp83867->io_impedance >= 0) in dp83867_config_init()
857 dp83867->io_impedance); in dp83867_config_init()
859 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { in dp83867_config_init()
886 /* SGMII type is set to 4-wire mode by default. in dp83867_config_init()
888 * switch on 6-wire mode. in dp83867_config_init()
890 if (dp83867->sgmii_ref_clk_en) in dp83867_config_init()
900 if (dp83867->rxctrl_strap_quirk) in dp83867_config_init()
913 if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP) in dp83867_config_init()
917 if (dp83867->set_clk_output) { in dp83867_config_init()
920 if (dp83867->clk_output_sel == DP83867_CLK_O_SEL_OFF) { in dp83867_config_init()
924 val = dp83867->clk_output_sel << in dp83867_config_init()
970 /* There is a limitation in DP83867 PHY device where SGMII AN is in dp83867_link_change_notify()
972 * PHY TPI is down and up again, SGMII AN is not triggered and in dp83867_link_change_notify()
973 * hence no new in-band message from PHY to MAC side SGMII. in dp83867_link_change_notify()
974 * This could cause an issue during power up, when PHY is up prior in dp83867_link_change_notify()
976 * SGMII wouldn`t receive new in-band message from TI PHY with in dp83867_link_change_notify()
978 * Thus, implemented a SW solution here to retrigger SGMII Auto-Neg in dp83867_link_change_notify()
981 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { in dp83867_link_change_notify()
1007 return -EINVAL; in dp83867_led_brightness_set()
1061 MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver");