327 	u32 mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(dwmac4_addrs,  in dwmac4_dma_tx_chan_op_mode()  local
334 		mtl_tx_op |= MTL_OP_MODE_TSF;  in dwmac4_dma_tx_chan_op_mode()
337 		mtl_tx_op &= ~MTL_OP_MODE_TSF;  in dwmac4_dma_tx_chan_op_mode()
338 		mtl_tx_op &= MTL_OP_MODE_TTC_MASK;  in dwmac4_dma_tx_chan_op_mode()
341 			mtl_tx_op |= MTL_OP_MODE_TTC_32;  in dwmac4_dma_tx_chan_op_mode()
343 			mtl_tx_op |= MTL_OP_MODE_TTC_64;  in dwmac4_dma_tx_chan_op_mode()
345 			mtl_tx_op |= MTL_OP_MODE_TTC_96;  in dwmac4_dma_tx_chan_op_mode()
347 			mtl_tx_op |= MTL_OP_MODE_TTC_128;  in dwmac4_dma_tx_chan_op_mode()
349 			mtl_tx_op |= MTL_OP_MODE_TTC_192;  in dwmac4_dma_tx_chan_op_mode()
351 			mtl_tx_op |= MTL_OP_MODE_TTC_256;  in dwmac4_dma_tx_chan_op_mode()
353 			mtl_tx_op |= MTL_OP_MODE_TTC_384;  in dwmac4_dma_tx_chan_op_mode()
355 			mtl_tx_op |= MTL_OP_MODE_TTC_512;  in dwmac4_dma_tx_chan_op_mode()
366 	mtl_tx_op &= ~MTL_OP_MODE_TXQEN_MASK;  in dwmac4_dma_tx_chan_op_mode()
368 		mtl_tx_op |= MTL_OP_MODE_TXQEN;  in dwmac4_dma_tx_chan_op_mode()
370 		mtl_tx_op |= MTL_OP_MODE_TXQEN_AV;  in dwmac4_dma_tx_chan_op_mode()
371 	mtl_tx_op &= ~MTL_OP_MODE_TQS_MASK;  in dwmac4_dma_tx_chan_op_mode()
372 	mtl_tx_op |= tqs << MTL_OP_MODE_TQS_SHIFT;  in dwmac4_dma_tx_chan_op_mode()
374 	writel(mtl_tx_op, ioaddr +  MTL_CHAN_TX_OP_MODE(dwmac4_addrs, channel));  in dwmac4_dma_tx_chan_op_mode()
495 	u32 mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(dwmac4_addrs,  in dwmac4_qmode()  local
498 	mtl_tx_op &= ~MTL_OP_MODE_TXQEN_MASK;  in dwmac4_qmode()
500 		mtl_tx_op |= MTL_OP_MODE_TXQEN;  in dwmac4_qmode()
502 		mtl_tx_op |= MTL_OP_MODE_TXQEN_AV;  in dwmac4_qmode()
504 	writel(mtl_tx_op, ioaddr +  MTL_CHAN_TX_OP_MODE(dwmac4_addrs, channel));  in dwmac4_qmode()