ethernet/freescale/fec.h

1 /* SPDX-License-Identifier: GPL-2.0 */
5  *	fec.h  --  Fast Ethernet Controller for Motorola ColdFire SoC
8  *	(C) Copyright 2000-2005, Greg Ungerer (gerg@snapgear.com)
9  *	(C) Copyright 2000-2001, Lineo (www.lineo.com)
23 #include <dt-bindings/firmware/imx/rsrc.h>
48 #define FEC_TXIC0		0x0f0 /* Tx Interrupt Coalescing for ring 0 */
49 #define FEC_TXIC1		0x0f4 /* Tx Interrupt Coalescing for ring 1 */
50 #define FEC_TXIC2		0x0f8 /* Tx Interrupt Coalescing for ring 2 */
51 #define FEC_RXIC0		0x100 /* Rx Interrupt Coalescing for ring 0 */
52 #define FEC_RXIC1		0x104 /* Rx Interrupt Coalescing for ring 1 */
53 #define FEC_RXIC2		0x108 /* Rx Interrupt Coalescing for ring 2 */
61 #define FEC_R_DES_START_1	0x160 /* Receive descriptor ring 1 */
62 #define FEC_X_DES_START_1	0x164 /* Transmit descriptor ring 1 */
64 #define FEC_R_DES_START_2	0x16c /* Receive descriptor ring 2 */
65 #define FEC_X_DES_START_2	0x170 /* Transmit descriptor ring 2 */
67 #define FEC_R_DES_START_0	0x180 /* Receive descriptor ring */
68 #define FEC_X_DES_START_0	0x184 /* Transmit descriptor ring */
76 #define FEC_RCMR_1		0x1c8 /* Receive classification match ring 1 */
77 #define FEC_RCMR_2		0x1cc /* Receive classification match ring 2 */
78 #define FEC_DMA_CFG_1		0x1d8 /* DMA class configuration for ring 1 */
79 #define FEC_DMA_CFG_2		0x1dc /* DMA class Configuration for ring 2 */
80 #define FEC_R_DES_ACTIVE_1	0x1e0 /* Rx descriptor active for ring 1 */
81 #define FEC_X_DES_ACTIVE_1	0x1e4 /* Tx descriptor active for ring 1 */
82 #define FEC_R_DES_ACTIVE_2	0x1e8 /* Rx descriptor active for ring 2 */
83 #define FEC_X_DES_ACTIVE_2	0x1ec /* Tx descriptor active for ring 2 */
120 #define IEEE_T_CSERR		0x268 /* Frames tx'd with carrier sense err */
174 #define FEC_R_DES_START_0	0x3d0 /* Receive descriptor ring */
177 #define FEC_X_DES_START_0	0x3d4 /* Transmit descriptor ring */
347  * We don't need to allocate pages for the transmitter.  We just use
353 #define FEC_ENET_RX_FRSIZE	(PAGE_SIZE - FEC_ENET_XDP_HEADROOM \
354 		- SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
410 /* Controller is ENET-MAC */
429  * were added to the ring and the ENET_TDAR[TDAR] bit is set. This results in
430  * frames not being transmitted until there is a 0-to-1 transition on
437  * - Two class indicators on receive with configurable priority
438  * - Two class indicators and line speed timer on transmit allowing
440  * - Additional DMA registers provisioned to allow managing up to 3
445  * and the UDMA clears TDAR simultaneously or in a small window (2-4 cycles).
453  * The wait-time-cycles is at least 6 clock cycles of the slower clock between
455  * register clock is 66Mhz, so the wait-time-cycles must be greater than 240ns
487 /* i.MX6SX ENET IP supports multiple queues (3 queues), use this quirk to
581 	/* rx queue number, in the range 0-7 */
591 /* The FEC buffer descriptors track the ring buffers.  The rx_bd_base and
617 	/* The saved address of a sent-in-place packet/buffer, for skfree(). */