Lines Matching refs:bp
306 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp);
312 static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr);
314 static void __storm_memset_dma_mapping(struct bnx2x *bp, in __storm_memset_dma_mapping() argument
317 REG_WR(bp, addr, U64_LO(mapping)); in __storm_memset_dma_mapping()
318 REG_WR(bp, addr + 4, U64_HI(mapping)); in __storm_memset_dma_mapping()
321 static void storm_memset_spq_addr(struct bnx2x *bp, in storm_memset_spq_addr() argument
327 __storm_memset_dma_mapping(bp, addr, mapping); in storm_memset_spq_addr()
330 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid, in storm_memset_vf_to_pf() argument
333 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid), in storm_memset_vf_to_pf()
335 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid), in storm_memset_vf_to_pf()
337 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid), in storm_memset_vf_to_pf()
339 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid), in storm_memset_vf_to_pf()
343 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid, in storm_memset_func_en() argument
346 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid), in storm_memset_func_en()
348 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid), in storm_memset_func_en()
350 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid), in storm_memset_func_en()
352 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid), in storm_memset_func_en()
356 static void storm_memset_eq_data(struct bnx2x *bp, in storm_memset_eq_data() argument
364 __storm_memset_struct(bp, addr, size, (u32 *)eq_data); in storm_memset_eq_data()
367 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod, in storm_memset_eq_prod() argument
371 REG_WR16(bp, addr, eq_prod); in storm_memset_eq_prod()
377 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val) in bnx2x_reg_wr_ind() argument
379 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); in bnx2x_reg_wr_ind()
380 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val); in bnx2x_reg_wr_ind()
381 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, in bnx2x_reg_wr_ind()
385 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr) in bnx2x_reg_rd_ind() argument
389 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); in bnx2x_reg_rd_ind()
390 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val); in bnx2x_reg_rd_ind()
391 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, in bnx2x_reg_rd_ind()
403 static void bnx2x_dp_dmae(struct bnx2x *bp, in bnx2x_dp_dmae() argument
470 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx) in bnx2x_post_dmae() argument
477 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i)); in bnx2x_post_dmae()
479 REG_WR(bp, dmae_reg_go_c[idx], 1); in bnx2x_post_dmae()
493 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, in bnx2x_dmae_opcode() argument
503 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0); in bnx2x_dmae_opcode()
504 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) | in bnx2x_dmae_opcode()
505 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT)); in bnx2x_dmae_opcode()
518 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, in bnx2x_prep_dmae_with_comp() argument
525 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type, in bnx2x_prep_dmae_with_comp()
529 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp)); in bnx2x_prep_dmae_with_comp()
530 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp)); in bnx2x_prep_dmae_with_comp()
535 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae, in bnx2x_issue_dmae_with_comp() argument
538 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000; in bnx2x_issue_dmae_with_comp()
541 bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE); in bnx2x_issue_dmae_with_comp()
548 spin_lock_bh(&bp->dmae_lock); in bnx2x_issue_dmae_with_comp()
554 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp)); in bnx2x_issue_dmae_with_comp()
561 (bp->recovery_state != BNX2X_RECOVERY_DONE && in bnx2x_issue_dmae_with_comp()
562 bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) { in bnx2x_issue_dmae_with_comp()
577 spin_unlock_bh(&bp->dmae_lock); in bnx2x_issue_dmae_with_comp()
582 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, in bnx2x_write_dmae() argument
588 if (!bp->dmae_ready) { in bnx2x_write_dmae()
589 u32 *data = bnx2x_sp(bp, wb_data[0]); in bnx2x_write_dmae()
591 if (CHIP_IS_E1(bp)) in bnx2x_write_dmae()
592 bnx2x_init_ind_wr(bp, dst_addr, data, len32); in bnx2x_write_dmae()
594 bnx2x_init_str_wr(bp, dst_addr, data, len32); in bnx2x_write_dmae()
599 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC); in bnx2x_write_dmae()
609 rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp)); in bnx2x_write_dmae()
618 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32) in bnx2x_read_dmae() argument
623 if (!bp->dmae_ready) { in bnx2x_read_dmae()
624 u32 *data = bnx2x_sp(bp, wb_data[0]); in bnx2x_read_dmae()
627 if (CHIP_IS_E1(bp)) in bnx2x_read_dmae()
629 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4); in bnx2x_read_dmae()
632 data[i] = REG_RD(bp, src_addr + i*4); in bnx2x_read_dmae()
638 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI); in bnx2x_read_dmae()
643 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data)); in bnx2x_read_dmae()
644 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data)); in bnx2x_read_dmae()
648 rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp)); in bnx2x_read_dmae()
657 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr, in bnx2x_write_dmae_phys_len() argument
660 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp); in bnx2x_write_dmae_phys_len()
664 bnx2x_write_dmae(bp, phys_addr + offset, in bnx2x_write_dmae_phys_len()
670 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len); in bnx2x_write_dmae_phys_len()
684 static inline int bnx2x_get_assert_list_entry(struct bnx2x *bp, in bnx2x_get_assert_list_entry() argument
704 static int bnx2x_mc_assert(struct bnx2x *bp) in bnx2x_mc_assert() argument
730 last_idx = REG_RD8(bp, bar_storm_intmem[storm] + in bnx2x_mc_assert()
740 regs[j] = REG_RD(bp, bar_storm_intmem[storm] + in bnx2x_mc_assert()
741 bnx2x_get_assert_list_entry(bp, in bnx2x_mc_assert()
759 CHIP_IS_E1(bp) ? "everest1" : in bnx2x_mc_assert()
760 CHIP_IS_E1H(bp) ? "everest1h" : in bnx2x_mc_assert()
761 CHIP_IS_E2(bp) ? "everest2" : "everest3", in bnx2x_mc_assert()
762 bp->fw_major, bp->fw_minor, bp->fw_rev); in bnx2x_mc_assert()
768 #define SCRATCH_BUFFER_SIZE(bp) \ argument
769 (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000))
771 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl) in bnx2x_fw_dump_lvl() argument
778 if (BP_NOMCP(bp)) { in bnx2x_fw_dump_lvl()
782 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n", in bnx2x_fw_dump_lvl()
783 (bp->common.bc_ver & 0xff0000) >> 16, in bnx2x_fw_dump_lvl()
784 (bp->common.bc_ver & 0xff00) >> 8, in bnx2x_fw_dump_lvl()
785 (bp->common.bc_ver & 0xff)); in bnx2x_fw_dump_lvl()
787 if (pci_channel_offline(bp->pdev)) { in bnx2x_fw_dump_lvl()
792 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER); in bnx2x_fw_dump_lvl()
793 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER)) in bnx2x_fw_dump_lvl()
796 if (BP_PATH(bp) == 0) in bnx2x_fw_dump_lvl()
797 trace_shmem_base = bp->common.shmem_base; in bnx2x_fw_dump_lvl()
799 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr); in bnx2x_fw_dump_lvl()
802 if (trace_shmem_base < MCPR_SCRATCH_BASE(bp) + MCPR_TRACE_BUFFER_SIZE || in bnx2x_fw_dump_lvl()
803 trace_shmem_base >= MCPR_SCRATCH_BASE(bp) + in bnx2x_fw_dump_lvl()
804 SCRATCH_BUFFER_SIZE(bp)) { in bnx2x_fw_dump_lvl()
813 mark = REG_RD(bp, addr); in bnx2x_fw_dump_lvl()
821 mark = REG_RD(bp, addr); in bnx2x_fw_dump_lvl()
822 mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000; in bnx2x_fw_dump_lvl()
834 data[word] = htonl(REG_RD(bp, offset + 4*word)); in bnx2x_fw_dump_lvl()
842 data[word] = htonl(REG_RD(bp, offset + 4*word)); in bnx2x_fw_dump_lvl()
849 static void bnx2x_fw_dump(struct bnx2x *bp) in bnx2x_fw_dump() argument
851 bnx2x_fw_dump_lvl(bp, KERN_ERR); in bnx2x_fw_dump()
854 static void bnx2x_hc_int_disable(struct bnx2x *bp) in bnx2x_hc_int_disable() argument
856 int port = BP_PORT(bp); in bnx2x_hc_int_disable()
858 u32 val = REG_RD(bp, addr); in bnx2x_hc_int_disable()
864 if (CHIP_IS_E1(bp)) { in bnx2x_hc_int_disable()
869 REG_WR(bp, HC_REG_INT_MASK + port*4, 0); in bnx2x_hc_int_disable()
884 REG_WR(bp, addr, val); in bnx2x_hc_int_disable()
885 if (REG_RD(bp, addr) != val) in bnx2x_hc_int_disable()
889 static void bnx2x_igu_int_disable(struct bnx2x *bp) in bnx2x_igu_int_disable() argument
891 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); in bnx2x_igu_int_disable()
899 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); in bnx2x_igu_int_disable()
900 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val) in bnx2x_igu_int_disable()
904 static void bnx2x_int_disable(struct bnx2x *bp) in bnx2x_int_disable() argument
906 if (bp->common.int_block == INT_BLOCK_HC) in bnx2x_int_disable()
907 bnx2x_hc_int_disable(bp); in bnx2x_int_disable()
909 bnx2x_igu_int_disable(bp); in bnx2x_int_disable()
912 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int) in bnx2x_panic_dump() argument
917 int func = BP_FUNC(bp); in bnx2x_panic_dump()
922 if (IS_PF(bp) && disable_int) in bnx2x_panic_dump()
923 bnx2x_int_disable(bp); in bnx2x_panic_dump()
925 bp->stats_state = STATS_STATE_DISABLED; in bnx2x_panic_dump()
926 bp->eth_stats.unrecoverable_error++; in bnx2x_panic_dump()
933 if (IS_PF(bp)) { in bnx2x_panic_dump()
934 struct host_sp_status_block *def_sb = bp->def_status_blk; in bnx2x_panic_dump()
938 bp->def_idx, bp->def_att_idx, bp->attn_state, in bnx2x_panic_dump()
939 bp->spq_prod_idx, bp->stats_counter); in bnx2x_panic_dump()
956 REG_RD(bp, BAR_CSTRORM_INTMEM + cstorm_offset + in bnx2x_panic_dump()
969 for_each_eth_queue(bp, i) { in bnx2x_panic_dump()
970 struct bnx2x_fastpath *fp = &bp->fp[i]; in bnx2x_panic_dump()
975 CHIP_IS_E1x(bp) ? in bnx2x_panic_dump()
979 CHIP_IS_E1x(bp) ? in bnx2x_panic_dump()
986 if (!bp->fp) in bnx2x_panic_dump()
1019 loop = CHIP_IS_E1x(bp) ? in bnx2x_panic_dump()
1040 if (IS_VF(bp)) in bnx2x_panic_dump()
1044 data_size = CHIP_IS_E1x(bp) ? in bnx2x_panic_dump()
1048 sb_data_p = CHIP_IS_E1x(bp) ? in bnx2x_panic_dump()
1053 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM + in bnx2x_panic_dump()
1057 if (!CHIP_IS_E1x(bp)) { in bnx2x_panic_dump()
1094 if (IS_PF(bp)) { in bnx2x_panic_dump()
1096 BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod); in bnx2x_panic_dump()
1098 u32 *data = (u32 *)&bp->eq_ring[i].message.data; in bnx2x_panic_dump()
1101 i, bp->eq_ring[i].message.opcode, in bnx2x_panic_dump()
1102 bp->eq_ring[i].message.error); in bnx2x_panic_dump()
1110 for_each_valid_rx_queue(bp, i) { in bnx2x_panic_dump()
1111 struct bnx2x_fastpath *fp = &bp->fp[i]; in bnx2x_panic_dump()
1113 if (!bp->fp) in bnx2x_panic_dump()
1150 for_each_valid_tx_queue(bp, i) { in bnx2x_panic_dump()
1151 struct bnx2x_fastpath *fp = &bp->fp[i]; in bnx2x_panic_dump()
1153 if (!bp->fp) in bnx2x_panic_dump()
1188 if (IS_PF(bp)) { in bnx2x_panic_dump()
1189 int tmp_msg_en = bp->msg_enable; in bnx2x_panic_dump()
1191 bnx2x_fw_dump(bp); in bnx2x_panic_dump()
1192 bp->msg_enable |= NETIF_MSG_HW; in bnx2x_panic_dump()
1194 bnx2x_idle_chk(bp); in bnx2x_panic_dump()
1196 bnx2x_idle_chk(bp); in bnx2x_panic_dump()
1197 bp->msg_enable = tmp_msg_en; in bnx2x_panic_dump()
1198 bnx2x_mc_assert(bp); in bnx2x_panic_dump()
1227 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp, in bnx2x_pbf_pN_buf_flushed() argument
1234 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed); in bnx2x_pbf_pN_buf_flushed()
1235 crd = crd_start = REG_RD(bp, regs->crd); in bnx2x_pbf_pN_buf_flushed()
1236 init_crd = REG_RD(bp, regs->init_crd); in bnx2x_pbf_pN_buf_flushed()
1246 crd = REG_RD(bp, regs->crd); in bnx2x_pbf_pN_buf_flushed()
1247 crd_freed = REG_RD(bp, regs->crd_freed); in bnx2x_pbf_pN_buf_flushed()
1262 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp, in bnx2x_pbf_pN_cmd_flushed() argument
1269 occup = to_free = REG_RD(bp, regs->lines_occup); in bnx2x_pbf_pN_cmd_flushed()
1270 freed = freed_start = REG_RD(bp, regs->lines_freed); in bnx2x_pbf_pN_cmd_flushed()
1278 occup = REG_RD(bp, regs->lines_occup); in bnx2x_pbf_pN_cmd_flushed()
1279 freed = REG_RD(bp, regs->lines_freed); in bnx2x_pbf_pN_cmd_flushed()
1294 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg, in bnx2x_flr_clnup_reg_poll() argument
1300 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--) in bnx2x_flr_clnup_reg_poll()
1306 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg, in bnx2x_flr_clnup_poll_hw_counter() argument
1309 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt); in bnx2x_flr_clnup_poll_hw_counter()
1318 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp) in bnx2x_flr_clnup_poll_count() argument
1321 if (CHIP_REV_IS_EMUL(bp)) in bnx2x_flr_clnup_poll_count()
1324 if (CHIP_REV_IS_FPGA(bp)) in bnx2x_flr_clnup_poll_count()
1330 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count) in bnx2x_tx_hw_flushed() argument
1333 {0, (CHIP_IS_E3B0(bp)) ? in bnx2x_tx_hw_flushed()
1336 (CHIP_IS_E3B0(bp)) ? in bnx2x_tx_hw_flushed()
1339 {1, (CHIP_IS_E3B0(bp)) ? in bnx2x_tx_hw_flushed()
1342 (CHIP_IS_E3B0(bp)) ? in bnx2x_tx_hw_flushed()
1345 {4, (CHIP_IS_E3B0(bp)) ? in bnx2x_tx_hw_flushed()
1348 (CHIP_IS_E3B0(bp)) ? in bnx2x_tx_hw_flushed()
1354 {0, (CHIP_IS_E3B0(bp)) ? in bnx2x_tx_hw_flushed()
1357 (CHIP_IS_E3B0(bp)) ? in bnx2x_tx_hw_flushed()
1360 (CHIP_IS_E3B0(bp)) ? in bnx2x_tx_hw_flushed()
1363 {1, (CHIP_IS_E3B0(bp)) ? in bnx2x_tx_hw_flushed()
1366 (CHIP_IS_E3B0(bp)) ? in bnx2x_tx_hw_flushed()
1369 (CHIP_IS_E3B0(bp)) ? in bnx2x_tx_hw_flushed()
1372 {4, (CHIP_IS_E3B0(bp)) ? in bnx2x_tx_hw_flushed()
1375 (CHIP_IS_E3B0(bp)) ? in bnx2x_tx_hw_flushed()
1378 (CHIP_IS_E3B0(bp)) ? in bnx2x_tx_hw_flushed()
1387 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count); in bnx2x_tx_hw_flushed()
1391 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count); in bnx2x_tx_hw_flushed()
1403 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt) in bnx2x_send_final_clnup() argument
1409 if (REG_RD(bp, comp_addr)) { in bnx2x_send_final_clnup()
1420 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command); in bnx2x_send_final_clnup()
1422 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) { in bnx2x_send_final_clnup()
1425 (REG_RD(bp, comp_addr))); in bnx2x_send_final_clnup()
1430 REG_WR(bp, comp_addr, 0); in bnx2x_send_final_clnup()
1445 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt) in bnx2x_poll_hw_usage_counters() argument
1448 if (bnx2x_flr_clnup_poll_hw_counter(bp, in bnx2x_poll_hw_usage_counters()
1455 if (bnx2x_flr_clnup_poll_hw_counter(bp, in bnx2x_poll_hw_usage_counters()
1462 if (bnx2x_flr_clnup_poll_hw_counter(bp, in bnx2x_poll_hw_usage_counters()
1463 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp), in bnx2x_poll_hw_usage_counters()
1469 if (bnx2x_flr_clnup_poll_hw_counter(bp, in bnx2x_poll_hw_usage_counters()
1470 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp), in bnx2x_poll_hw_usage_counters()
1474 if (bnx2x_flr_clnup_poll_hw_counter(bp, in bnx2x_poll_hw_usage_counters()
1475 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp), in bnx2x_poll_hw_usage_counters()
1481 if (bnx2x_flr_clnup_poll_hw_counter(bp, in bnx2x_poll_hw_usage_counters()
1482 dmae_reg_go_c[INIT_DMAE_C(bp)], in bnx2x_poll_hw_usage_counters()
1490 static void bnx2x_hw_enable_status(struct bnx2x *bp) in bnx2x_hw_enable_status() argument
1494 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF); in bnx2x_hw_enable_status()
1497 val = REG_RD(bp, PBF_REG_DISABLE_PF); in bnx2x_hw_enable_status()
1500 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN); in bnx2x_hw_enable_status()
1503 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN); in bnx2x_hw_enable_status()
1506 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK); in bnx2x_hw_enable_status()
1509 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR); in bnx2x_hw_enable_status()
1512 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR); in bnx2x_hw_enable_status()
1515 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); in bnx2x_hw_enable_status()
1520 static int bnx2x_pf_flr_clnup(struct bnx2x *bp) in bnx2x_pf_flr_clnup() argument
1522 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp); in bnx2x_pf_flr_clnup()
1524 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp)); in bnx2x_pf_flr_clnup()
1527 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); in bnx2x_pf_flr_clnup()
1531 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt)) in bnx2x_pf_flr_clnup()
1537 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt)) in bnx2x_pf_flr_clnup()
1543 bnx2x_tx_hw_flushed(bp, poll_cnt); in bnx2x_pf_flr_clnup()
1549 if (bnx2x_is_pcie_pending(bp->pdev)) in bnx2x_pf_flr_clnup()
1553 bnx2x_hw_enable_status(bp); in bnx2x_pf_flr_clnup()
1559 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); in bnx2x_pf_flr_clnup()
1564 static void bnx2x_hc_int_enable(struct bnx2x *bp) in bnx2x_hc_int_enable() argument
1566 int port = BP_PORT(bp); in bnx2x_hc_int_enable()
1568 u32 val = REG_RD(bp, addr); in bnx2x_hc_int_enable()
1569 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false; in bnx2x_hc_int_enable()
1570 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false; in bnx2x_hc_int_enable()
1571 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false; in bnx2x_hc_int_enable()
1591 if (!CHIP_IS_E1(bp)) { in bnx2x_hc_int_enable()
1595 REG_WR(bp, addr, val); in bnx2x_hc_int_enable()
1601 if (CHIP_IS_E1(bp)) in bnx2x_hc_int_enable()
1602 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF); in bnx2x_hc_int_enable()
1608 REG_WR(bp, addr, val); in bnx2x_hc_int_enable()
1614 if (!CHIP_IS_E1(bp)) { in bnx2x_hc_int_enable()
1616 if (IS_MF(bp)) { in bnx2x_hc_int_enable()
1617 val = (0xee0f | (1 << (BP_VN(bp) + 4))); in bnx2x_hc_int_enable()
1618 if (bp->port.pmf) in bnx2x_hc_int_enable()
1624 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); in bnx2x_hc_int_enable()
1625 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); in bnx2x_hc_int_enable()
1629 static void bnx2x_igu_int_enable(struct bnx2x *bp) in bnx2x_igu_int_enable() argument
1632 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false; in bnx2x_igu_int_enable()
1633 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false; in bnx2x_igu_int_enable()
1634 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false; in bnx2x_igu_int_enable()
1636 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); in bnx2x_igu_int_enable()
1660 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); in bnx2x_igu_int_enable()
1661 bnx2x_ack_int(bp); in bnx2x_igu_int_enable()
1669 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); in bnx2x_igu_int_enable()
1672 pci_intx(bp->pdev, true); in bnx2x_igu_int_enable()
1677 if (IS_MF(bp)) { in bnx2x_igu_int_enable()
1678 val = (0xee0f | (1 << (BP_VN(bp) + 4))); in bnx2x_igu_int_enable()
1679 if (bp->port.pmf) in bnx2x_igu_int_enable()
1685 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); in bnx2x_igu_int_enable()
1686 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); in bnx2x_igu_int_enable()
1689 void bnx2x_int_enable(struct bnx2x *bp) in bnx2x_int_enable() argument
1691 if (bp->common.int_block == INT_BLOCK_HC) in bnx2x_int_enable()
1692 bnx2x_hc_int_enable(bp); in bnx2x_int_enable()
1694 bnx2x_igu_int_enable(bp); in bnx2x_int_enable()
1697 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw) in bnx2x_int_disable_sync() argument
1699 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; in bnx2x_int_disable_sync()
1704 bnx2x_int_disable(bp); in bnx2x_int_disable_sync()
1708 synchronize_irq(bp->msix_table[0].vector); in bnx2x_int_disable_sync()
1710 if (CNIC_SUPPORT(bp)) in bnx2x_int_disable_sync()
1712 for_each_eth_queue(bp, i) in bnx2x_int_disable_sync()
1713 synchronize_irq(bp->msix_table[offset++].vector); in bnx2x_int_disable_sync()
1715 synchronize_irq(bp->pdev->irq); in bnx2x_int_disable_sync()
1718 cancel_delayed_work(&bp->sp_task); in bnx2x_int_disable_sync()
1719 cancel_delayed_work(&bp->period_task); in bnx2x_int_disable_sync()
1730 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource) in bnx2x_trylock_hw_lock() argument
1734 int func = BP_FUNC(bp); in bnx2x_trylock_hw_lock()
1755 REG_WR(bp, hw_lock_control_reg + 4, resource_bit); in bnx2x_trylock_hw_lock()
1756 lock_status = REG_RD(bp, hw_lock_control_reg); in bnx2x_trylock_hw_lock()
1773 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp) in bnx2x_get_leader_lock_resource() argument
1775 if (BP_PATH(bp)) in bnx2x_get_leader_lock_resource()
1788 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp) in bnx2x_trylock_leader_lock() argument
1790 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); in bnx2x_trylock_leader_lock()
1793 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1796 static int bnx2x_schedule_sp_task(struct bnx2x *bp) in bnx2x_schedule_sp_task() argument
1802 atomic_set(&bp->interrupt_occurred, 1); in bnx2x_schedule_sp_task()
1811 return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); in bnx2x_schedule_sp_task()
1816 struct bnx2x *bp = fp->bp; in bnx2x_sp_event() local
1820 struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj; in bnx2x_sp_event()
1824 fp->index, cid, command, bp->state, in bnx2x_sp_event()
1832 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj); in bnx2x_sp_event()
1877 q_obj->complete_cmd(bp, q_obj, drv_cmd)) in bnx2x_sp_event()
1892 atomic_inc(&bp->cq_spq_left); in bnx2x_sp_event()
1896 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left)); in bnx2x_sp_event()
1899 (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) { in bnx2x_sp_event()
1910 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state); in bnx2x_sp_event()
1912 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state); in bnx2x_sp_event()
1916 bnx2x_schedule_sp_task(bp); in bnx2x_sp_event()
1924 struct bnx2x *bp = netdev_priv(dev_instance); in bnx2x_interrupt() local
1925 u16 status = bnx2x_ack_int(bp); in bnx2x_interrupt()
1938 if (unlikely(bp->panic)) in bnx2x_interrupt()
1942 for_each_eth_queue(bp, i) { in bnx2x_interrupt()
1943 struct bnx2x_fastpath *fp = &bp->fp[i]; in bnx2x_interrupt()
1945 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp)); in bnx2x_interrupt()
1951 napi_schedule_irqoff(&bnx2x_fp(bp, fp->index, napi)); in bnx2x_interrupt()
1956 if (CNIC_SUPPORT(bp)) { in bnx2x_interrupt()
1962 c_ops = rcu_dereference(bp->cnic_ops); in bnx2x_interrupt()
1963 if (c_ops && (bp->cnic_eth_dev.drv_state & in bnx2x_interrupt()
1965 c_ops->cnic_handler(bp->cnic_data, NULL); in bnx2x_interrupt()
1977 bnx2x_schedule_sp_task(bp); in bnx2x_interrupt()
1997 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource) in bnx2x_acquire_hw_lock() argument
2001 int func = BP_FUNC(bp); in bnx2x_acquire_hw_lock()
2020 lock_status = REG_RD(bp, hw_lock_control_reg); in bnx2x_acquire_hw_lock()
2030 REG_WR(bp, hw_lock_control_reg + 4, resource_bit); in bnx2x_acquire_hw_lock()
2031 lock_status = REG_RD(bp, hw_lock_control_reg); in bnx2x_acquire_hw_lock()
2041 int bnx2x_release_leader_lock(struct bnx2x *bp) in bnx2x_release_leader_lock() argument
2043 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); in bnx2x_release_leader_lock()
2046 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource) in bnx2x_release_hw_lock() argument
2050 int func = BP_FUNC(bp); in bnx2x_release_hw_lock()
2068 lock_status = REG_RD(bp, hw_lock_control_reg); in bnx2x_release_hw_lock()
2075 REG_WR(bp, hw_lock_control_reg, resource_bit); in bnx2x_release_hw_lock()
2079 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port) in bnx2x_get_gpio() argument
2082 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && in bnx2x_get_gpio()
2083 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; in bnx2x_get_gpio()
2096 gpio_reg = REG_RD(bp, MISC_REG_GPIO); in bnx2x_get_gpio()
2107 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) in bnx2x_set_gpio() argument
2110 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && in bnx2x_set_gpio()
2111 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; in bnx2x_set_gpio()
2122 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); in bnx2x_set_gpio()
2124 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT); in bnx2x_set_gpio()
2157 REG_WR(bp, MISC_REG_GPIO, gpio_reg); in bnx2x_set_gpio()
2158 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); in bnx2x_set_gpio()
2163 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode) in bnx2x_set_mult_gpio() argument
2170 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); in bnx2x_set_mult_gpio()
2172 gpio_reg = REG_RD(bp, MISC_REG_GPIO); in bnx2x_set_mult_gpio()
2203 REG_WR(bp, MISC_REG_GPIO, gpio_reg); in bnx2x_set_mult_gpio()
2205 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); in bnx2x_set_mult_gpio()
2210 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) in bnx2x_set_gpio_int() argument
2213 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && in bnx2x_set_gpio_int()
2214 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; in bnx2x_set_gpio_int()
2225 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); in bnx2x_set_gpio_int()
2227 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT); in bnx2x_set_gpio_int()
2252 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg); in bnx2x_set_gpio_int()
2253 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); in bnx2x_set_gpio_int()
2258 static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode) in bnx2x_set_spio() argument
2268 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); in bnx2x_set_spio()
2270 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT); in bnx2x_set_spio()
2297 REG_WR(bp, MISC_REG_SPIO, spio_reg); in bnx2x_set_spio()
2298 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); in bnx2x_set_spio()
2303 void bnx2x_calc_fc_adv(struct bnx2x *bp) in bnx2x_calc_fc_adv() argument
2305 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp); in bnx2x_calc_fc_adv()
2307 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | in bnx2x_calc_fc_adv()
2309 switch (bp->link_vars.ieee_fc & in bnx2x_calc_fc_adv()
2312 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause | in bnx2x_calc_fc_adv()
2317 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause; in bnx2x_calc_fc_adv()
2325 static void bnx2x_set_requested_fc(struct bnx2x *bp) in bnx2x_set_requested_fc() argument
2331 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000)) in bnx2x_set_requested_fc()
2332 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX; in bnx2x_set_requested_fc()
2334 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH; in bnx2x_set_requested_fc()
2337 static void bnx2x_init_dropless_fc(struct bnx2x *bp) in bnx2x_init_dropless_fc() argument
2341 if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) { in bnx2x_init_dropless_fc()
2342 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) in bnx2x_init_dropless_fc()
2345 REG_WR(bp, BAR_USTRORM_INTMEM + in bnx2x_init_dropless_fc()
2346 USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)), in bnx2x_init_dropless_fc()
2354 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode) in bnx2x_initial_phy_init() argument
2356 int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp); in bnx2x_initial_phy_init()
2357 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx]; in bnx2x_initial_phy_init()
2359 if (!BP_NOMCP(bp)) { in bnx2x_initial_phy_init()
2360 bnx2x_set_requested_fc(bp); in bnx2x_initial_phy_init()
2361 bnx2x_acquire_phy_lock(bp); in bnx2x_initial_phy_init()
2364 struct link_params *lp = &bp->link_params; in bnx2x_initial_phy_init()
2383 struct link_params *lp = &bp->link_params; in bnx2x_initial_phy_init()
2387 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars); in bnx2x_initial_phy_init()
2389 bnx2x_release_phy_lock(bp); in bnx2x_initial_phy_init()
2391 bnx2x_init_dropless_fc(bp); in bnx2x_initial_phy_init()
2393 bnx2x_calc_fc_adv(bp); in bnx2x_initial_phy_init()
2395 if (bp->link_vars.link_up) { in bnx2x_initial_phy_init()
2396 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); in bnx2x_initial_phy_init()
2397 bnx2x_link_report(bp); in bnx2x_initial_phy_init()
2399 queue_delayed_work(bnx2x_wq, &bp->period_task, 0); in bnx2x_initial_phy_init()
2400 bp->link_params.req_line_speed[cfx_idx] = req_line_speed; in bnx2x_initial_phy_init()
2407 void bnx2x_link_set(struct bnx2x *bp) in bnx2x_link_set() argument
2409 if (!BP_NOMCP(bp)) { in bnx2x_link_set()
2410 bnx2x_acquire_phy_lock(bp); in bnx2x_link_set()
2411 bnx2x_phy_init(&bp->link_params, &bp->link_vars); in bnx2x_link_set()
2412 bnx2x_release_phy_lock(bp); in bnx2x_link_set()
2414 bnx2x_init_dropless_fc(bp); in bnx2x_link_set()
2416 bnx2x_calc_fc_adv(bp); in bnx2x_link_set()
2421 static void bnx2x__link_reset(struct bnx2x *bp) in bnx2x__link_reset() argument
2423 if (!BP_NOMCP(bp)) { in bnx2x__link_reset()
2424 bnx2x_acquire_phy_lock(bp); in bnx2x__link_reset()
2425 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars); in bnx2x__link_reset()
2426 bnx2x_release_phy_lock(bp); in bnx2x__link_reset()
2431 void bnx2x_force_link_reset(struct bnx2x *bp) in bnx2x_force_link_reset() argument
2433 bnx2x_acquire_phy_lock(bp); in bnx2x_force_link_reset()
2434 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1); in bnx2x_force_link_reset()
2435 bnx2x_release_phy_lock(bp); in bnx2x_force_link_reset()
2438 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes) in bnx2x_link_test() argument
2442 if (!BP_NOMCP(bp)) { in bnx2x_link_test()
2443 bnx2x_acquire_phy_lock(bp); in bnx2x_link_test()
2444 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars, in bnx2x_link_test()
2446 bnx2x_release_phy_lock(bp); in bnx2x_link_test()
2462 static void bnx2x_calc_vn_min(struct bnx2x *bp, in bnx2x_calc_vn_min() argument
2468 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { in bnx2x_calc_vn_min()
2469 u32 vn_cfg = bp->mf_config[vn]; in bnx2x_calc_vn_min()
2486 if (BNX2X_IS_ETS_ENABLED(bp)) { in bnx2x_calc_vn_min()
2500 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn, in bnx2x_calc_vn_max() argument
2504 u32 vn_cfg = bp->mf_config[vn]; in bnx2x_calc_vn_max()
2509 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg); in bnx2x_calc_vn_max()
2511 if (IS_MF_PERCENT_BW(bp)) { in bnx2x_calc_vn_max()
2513 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100; in bnx2x_calc_vn_max()
2524 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp) in bnx2x_get_cmng_fns_mode() argument
2526 if (CHIP_REV_IS_SLOW(bp)) in bnx2x_get_cmng_fns_mode()
2528 if (IS_MF(bp)) in bnx2x_get_cmng_fns_mode()
2534 void bnx2x_read_mf_cfg(struct bnx2x *bp) in bnx2x_read_mf_cfg() argument
2536 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1); in bnx2x_read_mf_cfg()
2538 if (BP_NOMCP(bp)) in bnx2x_read_mf_cfg()
2552 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { in bnx2x_read_mf_cfg()
2553 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp); in bnx2x_read_mf_cfg()
2558 bp->mf_config[vn] = in bnx2x_read_mf_cfg()
2559 MF_CFG_RD(bp, func_mf_config[func].config); in bnx2x_read_mf_cfg()
2561 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { in bnx2x_read_mf_cfg()
2563 bp->flags |= MF_FUNC_DIS; in bnx2x_read_mf_cfg()
2566 bp->flags &= ~MF_FUNC_DIS; in bnx2x_read_mf_cfg()
2570 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type) in bnx2x_cmng_fns_init() argument
2575 input.port_rate = bp->link_vars.line_speed; in bnx2x_cmng_fns_init()
2582 bnx2x_read_mf_cfg(bp); in bnx2x_cmng_fns_init()
2585 bnx2x_calc_vn_min(bp, &input); in bnx2x_cmng_fns_init()
2588 if (bp->port.pmf) in bnx2x_cmng_fns_init()
2589 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) in bnx2x_cmng_fns_init()
2590 bnx2x_calc_vn_max(bp, vn, &input); in bnx2x_cmng_fns_init()
2596 bnx2x_init_cmng(&input, &bp->cmng); in bnx2x_cmng_fns_init()
2605 static void storm_memset_cmng(struct bnx2x *bp, in storm_memset_cmng() argument
2615 __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port); in storm_memset_cmng()
2617 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { in storm_memset_cmng()
2618 int func = func_by_vn(bp, vn); in storm_memset_cmng()
2623 __storm_memset_struct(bp, addr, size, in storm_memset_cmng()
2629 __storm_memset_struct(bp, addr, size, in storm_memset_cmng()
2635 void bnx2x_set_local_cmng(struct bnx2x *bp) in bnx2x_set_local_cmng() argument
2637 int cmng_fns = bnx2x_get_cmng_fns_mode(bp); in bnx2x_set_local_cmng()
2640 bnx2x_cmng_fns_init(bp, false, cmng_fns); in bnx2x_set_local_cmng()
2641 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); in bnx2x_set_local_cmng()
2650 static void bnx2x_link_attn(struct bnx2x *bp) in bnx2x_link_attn() argument
2653 bnx2x_stats_handle(bp, STATS_EVENT_STOP); in bnx2x_link_attn()
2655 bnx2x_link_update(&bp->link_params, &bp->link_vars); in bnx2x_link_attn()
2657 bnx2x_init_dropless_fc(bp); in bnx2x_link_attn()
2659 if (bp->link_vars.link_up) { in bnx2x_link_attn()
2661 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) { in bnx2x_link_attn()
2664 pstats = bnx2x_sp(bp, port_stats); in bnx2x_link_attn()
2669 if (bp->state == BNX2X_STATE_OPEN) in bnx2x_link_attn()
2670 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); in bnx2x_link_attn()
2673 if (bp->link_vars.link_up && bp->link_vars.line_speed) in bnx2x_link_attn()
2674 bnx2x_set_local_cmng(bp); in bnx2x_link_attn()
2676 __bnx2x_link_report(bp); in bnx2x_link_attn()
2678 if (IS_MF(bp)) in bnx2x_link_attn()
2679 bnx2x_link_sync_notify(bp); in bnx2x_link_attn()
2682 void bnx2x__link_status_update(struct bnx2x *bp) in bnx2x__link_status_update() argument
2684 if (bp->state != BNX2X_STATE_OPEN) in bnx2x__link_status_update()
2688 if (IS_PF(bp)) { in bnx2x__link_status_update()
2689 bnx2x_dcbx_pmf_update(bp); in bnx2x__link_status_update()
2690 bnx2x_link_status_update(&bp->link_params, &bp->link_vars); in bnx2x__link_status_update()
2691 if (bp->link_vars.link_up) in bnx2x__link_status_update()
2692 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); in bnx2x__link_status_update()
2694 bnx2x_stats_handle(bp, STATS_EVENT_STOP); in bnx2x__link_status_update()
2696 bnx2x_link_report(bp); in bnx2x__link_status_update()
2699 bp->port.supported[0] |= (SUPPORTED_10baseT_Half | in bnx2x__link_status_update()
2711 bp->port.advertising[0] = bp->port.supported[0]; in bnx2x__link_status_update()
2713 bp->link_params.bp = bp; in bnx2x__link_status_update()
2714 bp->link_params.port = BP_PORT(bp); in bnx2x__link_status_update()
2715 bp->link_params.req_duplex[0] = DUPLEX_FULL; in bnx2x__link_status_update()
2716 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE; in bnx2x__link_status_update()
2717 bp->link_params.req_line_speed[0] = SPEED_10000; in bnx2x__link_status_update()
2718 bp->link_params.speed_cap_mask[0] = 0x7f0000; in bnx2x__link_status_update()
2719 bp->link_params.switch_cfg = SWITCH_CFG_10G; in bnx2x__link_status_update()
2720 bp->link_vars.mac_type = MAC_TYPE_BMAC; in bnx2x__link_status_update()
2721 bp->link_vars.line_speed = SPEED_10000; in bnx2x__link_status_update()
2722 bp->link_vars.link_status = in bnx2x__link_status_update()
2725 bp->link_vars.link_up = 1; in bnx2x__link_status_update()
2726 bp->link_vars.duplex = DUPLEX_FULL; in bnx2x__link_status_update()
2727 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE; in bnx2x__link_status_update()
2728 __bnx2x_link_report(bp); in bnx2x__link_status_update()
2730 bnx2x_sample_bulletin(bp); in bnx2x__link_status_update()
2737 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); in bnx2x__link_status_update()
2741 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid, in bnx2x_afex_func_update() argument
2748 func_params.f_obj = &bp->func_obj; in bnx2x_afex_func_update()
2760 if (bnx2x_func_state_change(bp, &func_params) < 0) in bnx2x_afex_func_update()
2761 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); in bnx2x_afex_func_update()
2766 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type, in bnx2x_afex_handle_vif_list_cmd() argument
2780 func_params.f_obj = &bp->func_obj; in bnx2x_afex_handle_vif_list_cmd()
2797 rc = bnx2x_func_state_change(bp, &func_params); in bnx2x_afex_handle_vif_list_cmd()
2799 bnx2x_fw_command(bp, drv_msg_code, 0); in bnx2x_afex_handle_vif_list_cmd()
2804 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd) in bnx2x_handle_afex_cmd() argument
2807 u32 func = BP_ABS_FUNC(bp); in bnx2x_handle_afex_cmd()
2817 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]); in bnx2x_handle_afex_cmd()
2820 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0); in bnx2x_handle_afex_cmd()
2824 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]); in bnx2x_handle_afex_cmd()
2825 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]); in bnx2x_handle_afex_cmd()
2829 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid, in bnx2x_handle_afex_cmd()
2834 addr_to_write = SHMEM2_RD(bp, in bnx2x_handle_afex_cmd()
2835 afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]); in bnx2x_handle_afex_cmd()
2836 stats_type = SHMEM2_RD(bp, in bnx2x_handle_afex_cmd()
2837 afex_param1_to_driver[BP_FW_MB_IDX(bp)]); in bnx2x_handle_afex_cmd()
2843 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type); in bnx2x_handle_afex_cmd()
2847 REG_WR(bp, addr_to_write + i*sizeof(u32), in bnx2x_handle_afex_cmd()
2851 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0); in bnx2x_handle_afex_cmd()
2855 mf_config = MF_CFG_RD(bp, func_mf_config[func].config); in bnx2x_handle_afex_cmd()
2856 bp->mf_config[BP_VN(bp)] = mf_config; in bnx2x_handle_afex_cmd()
2868 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp)); in bnx2x_handle_afex_cmd()
2870 bp->mf_config[BP_VN(bp)] = mf_config; in bnx2x_handle_afex_cmd()
2872 bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input); in bnx2x_handle_afex_cmd()
2874 cmng_input.vnic_max_rate[BP_VN(bp)]; in bnx2x_handle_afex_cmd()
2879 __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn); in bnx2x_handle_afex_cmd()
2883 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & in bnx2x_handle_afex_cmd()
2887 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & in bnx2x_handle_afex_cmd()
2895 (MF_CFG_RD(bp, in bnx2x_handle_afex_cmd()
2900 (MF_CFG_RD(bp, in bnx2x_handle_afex_cmd()
2906 if (bnx2x_afex_func_update(bp, vif_id, vlan_val, in bnx2x_handle_afex_cmd()
2910 bp->afex_def_vlan_tag = vlan_val; in bnx2x_handle_afex_cmd()
2911 bp->afex_vlan_mode = vlan_mode; in bnx2x_handle_afex_cmd()
2914 bnx2x_link_report(bp); in bnx2x_handle_afex_cmd()
2917 bnx2x_afex_func_update(bp, 0xFFFF, 0, 0); in bnx2x_handle_afex_cmd()
2920 bp->afex_def_vlan_tag = -1; in bnx2x_handle_afex_cmd()
2925 static void bnx2x_handle_update_svid_cmd(struct bnx2x *bp) in bnx2x_handle_update_svid_cmd() argument
2932 func_params.f_obj = &bp->func_obj; in bnx2x_handle_update_svid_cmd()
2939 if (IS_MF_UFP(bp) || IS_MF_BD(bp)) { in bnx2x_handle_update_svid_cmd()
2940 int func = BP_ABS_FUNC(bp); in bnx2x_handle_update_svid_cmd()
2944 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & in bnx2x_handle_update_svid_cmd()
2947 bp->mf_ov = val; in bnx2x_handle_update_svid_cmd()
2954 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + BP_PORT(bp) * 8, in bnx2x_handle_update_svid_cmd()
2955 bp->mf_ov); in bnx2x_handle_update_svid_cmd()
2960 switch_update_params->vlan = bp->mf_ov; in bnx2x_handle_update_svid_cmd()
2962 if (bnx2x_func_state_change(bp, &func_params) < 0) { in bnx2x_handle_update_svid_cmd()
2964 bp->mf_ov); in bnx2x_handle_update_svid_cmd()
2968 bp->mf_ov); in bnx2x_handle_update_svid_cmd()
2974 bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_OK, 0); in bnx2x_handle_update_svid_cmd()
2977 bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE, 0); in bnx2x_handle_update_svid_cmd()
2980 static void bnx2x_pmf_update(struct bnx2x *bp) in bnx2x_pmf_update() argument
2982 int port = BP_PORT(bp); in bnx2x_pmf_update()
2985 bp->port.pmf = 1; in bnx2x_pmf_update()
2986 DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf); in bnx2x_pmf_update()
2995 queue_delayed_work(bnx2x_wq, &bp->period_task, 0); in bnx2x_pmf_update()
2997 bnx2x_dcbx_pmf_update(bp); in bnx2x_pmf_update()
3000 val = (0xff0f | (1 << (BP_VN(bp) + 4))); in bnx2x_pmf_update()
3001 if (bp->common.int_block == INT_BLOCK_HC) { in bnx2x_pmf_update()
3002 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); in bnx2x_pmf_update()
3003 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); in bnx2x_pmf_update()
3004 } else if (!CHIP_IS_E1x(bp)) { in bnx2x_pmf_update()
3005 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); in bnx2x_pmf_update()
3006 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); in bnx2x_pmf_update()
3009 bnx2x_stats_handle(bp, STATS_EVENT_PMF); in bnx2x_pmf_update()
3021 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param) in bnx2x_fw_command() argument
3023 int mb_idx = BP_FW_MB_IDX(bp); in bnx2x_fw_command()
3027 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10; in bnx2x_fw_command()
3029 mutex_lock(&bp->fw_mb_mutex); in bnx2x_fw_command()
3030 seq = ++bp->fw_seq; in bnx2x_fw_command()
3031 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param); in bnx2x_fw_command()
3032 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq)); in bnx2x_fw_command()
3041 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header); in bnx2x_fw_command()
3055 bnx2x_fw_dump(bp); in bnx2x_fw_command()
3058 mutex_unlock(&bp->fw_mb_mutex); in bnx2x_fw_command()
3063 static void storm_memset_func_cfg(struct bnx2x *bp, in storm_memset_func_cfg() argument
3072 __storm_memset_struct(bp, addr, size, (u32 *)tcfg); in storm_memset_func_cfg()
3075 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p) in bnx2x_func_init() argument
3077 if (CHIP_IS_E1x(bp)) { in bnx2x_func_init()
3080 storm_memset_func_cfg(bp, &tcfg, p->func_id); in bnx2x_func_init()
3084 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id); in bnx2x_func_init()
3085 storm_memset_func_en(bp, p->func_id, 1); in bnx2x_func_init()
3089 storm_memset_spq_addr(bp, p->spq_map, p->func_id); in bnx2x_func_init()
3090 REG_WR(bp, XSEM_REG_FAST_MEMORY + in bnx2x_func_init()
3104 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp, in bnx2x_get_common_flags() argument
3122 if (bp->flags & TX_SWITCHING) in bnx2x_get_common_flags()
3135 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp, in bnx2x_get_q_flags() argument
3142 if (IS_MF_SD(bp)) in bnx2x_get_q_flags()
3167 if (IS_MF_AFEX(bp)) in bnx2x_get_q_flags()
3170 return flags | bnx2x_get_common_flags(bp, fp, true); in bnx2x_get_q_flags()
3173 static void bnx2x_pf_q_prep_general(struct bnx2x *bp, in bnx2x_pf_q_prep_general() argument
3184 gen_init->mtu = bp->dev->mtu; in bnx2x_pf_q_prep_general()
3191 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp, in bnx2x_pf_rx_q_prep() argument
3200 pause->sge_th_lo = SGE_TH_LO(bp); in bnx2x_pf_rx_q_prep()
3201 pause->sge_th_hi = SGE_TH_HI(bp); in bnx2x_pf_rx_q_prep()
3204 WARN_ON(bp->dropless_fc && in bnx2x_pf_rx_q_prep()
3209 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >> in bnx2x_pf_rx_q_prep()
3217 if (!CHIP_IS_E1(bp)) { in bnx2x_pf_rx_q_prep()
3218 pause->bd_th_lo = BD_TH_LO(bp); in bnx2x_pf_rx_q_prep()
3219 pause->bd_th_hi = BD_TH_HI(bp); in bnx2x_pf_rx_q_prep()
3221 pause->rcq_th_lo = RCQ_TH_LO(bp); in bnx2x_pf_rx_q_prep()
3222 pause->rcq_th_hi = RCQ_TH_HI(bp); in bnx2x_pf_rx_q_prep()
3227 WARN_ON(bp->dropless_fc && in bnx2x_pf_rx_q_prep()
3229 bp->rx_ring_size); in bnx2x_pf_rx_q_prep()
3230 WARN_ON(bp->dropless_fc && in bnx2x_pf_rx_q_prep()
3253 rxq_init->rss_engine_id = BP_FUNC(bp); in bnx2x_pf_rx_q_prep()
3254 rxq_init->mcast_engine_id = BP_FUNC(bp); in bnx2x_pf_rx_q_prep()
3261 rxq_init->max_tpa_queues = MAX_AGG_QS(bp); in bnx2x_pf_rx_q_prep()
3273 if (IS_MF_AFEX(bp)) { in bnx2x_pf_rx_q_prep()
3274 rxq_init->silent_removal_value = bp->afex_def_vlan_tag; in bnx2x_pf_rx_q_prep()
3279 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp, in bnx2x_pf_tx_q_prep() argument
3292 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id); in bnx2x_pf_tx_q_prep()
3300 static void bnx2x_pf_init(struct bnx2x *bp) in bnx2x_pf_init() argument
3305 if (!CHIP_IS_E1x(bp)) { in bnx2x_pf_init()
3308 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + in bnx2x_pf_init()
3310 (CHIP_MODE_IS_4_PORT(bp) ? in bnx2x_pf_init()
3311 BP_FUNC(bp) : BP_VN(bp))*4, 0); in bnx2x_pf_init()
3313 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + in bnx2x_pf_init()
3316 (CHIP_MODE_IS_4_PORT(bp) ? in bnx2x_pf_init()
3317 BP_FUNC(bp) : BP_VN(bp))*4, 0); in bnx2x_pf_init()
3321 func_init.pf_id = BP_FUNC(bp); in bnx2x_pf_init()
3322 func_init.func_id = BP_FUNC(bp); in bnx2x_pf_init()
3323 func_init.spq_map = bp->spq_mapping; in bnx2x_pf_init()
3324 func_init.spq_prod = bp->spq_prod_idx; in bnx2x_pf_init()
3326 bnx2x_func_init(bp, &func_init); in bnx2x_pf_init()
3328 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port)); in bnx2x_pf_init()
3336 bp->link_vars.line_speed = SPEED_10000; in bnx2x_pf_init()
3337 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp)); in bnx2x_pf_init()
3340 if (bp->port.pmf) in bnx2x_pf_init()
3341 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); in bnx2x_pf_init()
3344 eq_data.base_addr.hi = U64_HI(bp->eq_mapping); in bnx2x_pf_init()
3345 eq_data.base_addr.lo = U64_LO(bp->eq_mapping); in bnx2x_pf_init()
3346 eq_data.producer = bp->eq_prod; in bnx2x_pf_init()
3349 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp)); in bnx2x_pf_init()
3352 static void bnx2x_e1h_disable(struct bnx2x *bp) in bnx2x_e1h_disable() argument
3354 int port = BP_PORT(bp); in bnx2x_e1h_disable()
3356 bnx2x_tx_disable(bp); in bnx2x_e1h_disable()
3358 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); in bnx2x_e1h_disable()
3361 static void bnx2x_e1h_enable(struct bnx2x *bp) in bnx2x_e1h_enable() argument
3363 int port = BP_PORT(bp); in bnx2x_e1h_enable()
3365 if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) in bnx2x_e1h_enable()
3366 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1); in bnx2x_e1h_enable()
3369 netif_tx_wake_all_queues(bp->dev); in bnx2x_e1h_enable()
3379 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp) in bnx2x_drv_info_ether_stat() argument
3382 &bp->slowpath->drv_info_to_mcp.ether_stat; in bnx2x_drv_info_ether_stat()
3384 &bp->sp_objs->mac_obj; in bnx2x_drv_info_ether_stat()
3401 mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj, in bnx2x_drv_info_ether_stat()
3405 ether_stat->mtu_size = bp->dev->mtu; in bnx2x_drv_info_ether_stat()
3406 if (bp->dev->features & NETIF_F_RXCSUM) in bnx2x_drv_info_ether_stat()
3408 if (bp->dev->features & NETIF_F_TSO) in bnx2x_drv_info_ether_stat()
3410 ether_stat->feature_flags |= bp->common.boot_mode; in bnx2x_drv_info_ether_stat()
3412 ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0; in bnx2x_drv_info_ether_stat()
3414 ether_stat->txq_size = bp->tx_ring_size; in bnx2x_drv_info_ether_stat()
3415 ether_stat->rxq_size = bp->rx_ring_size; in bnx2x_drv_info_ether_stat()
3418 ether_stat->vf_cnt = IS_SRIOV(bp) ? bp->vfdb->sriov.nr_virtfn : 0; in bnx2x_drv_info_ether_stat()
3422 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp) in bnx2x_drv_info_fcoe_stat() argument
3424 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; in bnx2x_drv_info_fcoe_stat()
3426 &bp->slowpath->drv_info_to_mcp.fcoe_stat; in bnx2x_drv_info_fcoe_stat()
3428 if (!CNIC_LOADED(bp)) in bnx2x_drv_info_fcoe_stat()
3431 memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN); in bnx2x_drv_info_fcoe_stat()
3437 if (!NO_FCOE(bp)) { in bnx2x_drv_info_fcoe_stat()
3439 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)]. in bnx2x_drv_info_fcoe_stat()
3443 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)]. in bnx2x_drv_info_fcoe_stat()
3447 &bp->fw_stats_data->fcoe; in bnx2x_drv_info_fcoe_stat()
3521 bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD); in bnx2x_drv_info_fcoe_stat()
3524 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp) in bnx2x_drv_info_iscsi_stat() argument
3526 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; in bnx2x_drv_info_iscsi_stat()
3528 &bp->slowpath->drv_info_to_mcp.iscsi_stat; in bnx2x_drv_info_iscsi_stat()
3530 if (!CNIC_LOADED(bp)) in bnx2x_drv_info_iscsi_stat()
3533 memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac, in bnx2x_drv_info_iscsi_stat()
3540 bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD); in bnx2x_drv_info_iscsi_stat()
3548 static void bnx2x_config_mf_bw(struct bnx2x *bp) in bnx2x_config_mf_bw() argument
3554 if (!IS_MF(bp)) { in bnx2x_config_mf_bw()
3560 if (bp->link_vars.link_up) { in bnx2x_config_mf_bw()
3561 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX); in bnx2x_config_mf_bw()
3562 bnx2x_link_sync_notify(bp); in bnx2x_config_mf_bw()
3564 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); in bnx2x_config_mf_bw()
3567 static void bnx2x_set_mf_bw(struct bnx2x *bp) in bnx2x_set_mf_bw() argument
3569 bnx2x_config_mf_bw(bp); in bnx2x_set_mf_bw()
3570 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0); in bnx2x_set_mf_bw()
3573 static void bnx2x_handle_eee_event(struct bnx2x *bp) in bnx2x_handle_eee_event() argument
3576 bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0); in bnx2x_handle_eee_event()
3582 static void bnx2x_handle_drv_info_req(struct bnx2x *bp) in bnx2x_handle_drv_info_req() argument
3585 u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control); in bnx2x_handle_drv_info_req()
3591 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); in bnx2x_handle_drv_info_req()
3599 mutex_lock(&bp->drv_info_mutex); in bnx2x_handle_drv_info_req()
3601 memset(&bp->slowpath->drv_info_to_mcp, 0, in bnx2x_handle_drv_info_req()
3606 bnx2x_drv_info_ether_stat(bp); in bnx2x_handle_drv_info_req()
3609 bnx2x_drv_info_fcoe_stat(bp); in bnx2x_handle_drv_info_req()
3612 bnx2x_drv_info_iscsi_stat(bp); in bnx2x_handle_drv_info_req()
3616 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); in bnx2x_handle_drv_info_req()
3623 SHMEM2_WR(bp, drv_info_host_addr_lo, in bnx2x_handle_drv_info_req()
3624 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp))); in bnx2x_handle_drv_info_req()
3625 SHMEM2_WR(bp, drv_info_host_addr_hi, in bnx2x_handle_drv_info_req()
3626 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp))); in bnx2x_handle_drv_info_req()
3628 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0); in bnx2x_handle_drv_info_req()
3634 if (!SHMEM2_HAS(bp, mfw_drv_indication)) { in bnx2x_handle_drv_info_req()
3636 } else if (!bp->drv_info_mng_owner) { in bnx2x_handle_drv_info_req()
3637 u32 bit = MFW_DRV_IND_READ_DONE_OFFSET((BP_ABS_FUNC(bp) >> 1)); in bnx2x_handle_drv_info_req()
3640 u32 indication = SHMEM2_RD(bp, mfw_drv_indication); in bnx2x_handle_drv_info_req()
3644 SHMEM2_WR(bp, mfw_drv_indication, in bnx2x_handle_drv_info_req()
3655 bp->drv_info_mng_owner = true; in bnx2x_handle_drv_info_req()
3659 mutex_unlock(&bp->drv_info_mutex); in bnx2x_handle_drv_info_req()
3683 void bnx2x_update_mng_version(struct bnx2x *bp) in bnx2x_update_mng_version() argument
3688 int idx = BP_FW_MB_IDX(bp); in bnx2x_update_mng_version()
3691 if (!SHMEM2_HAS(bp, func_os_drv_ver)) in bnx2x_update_mng_version()
3694 mutex_lock(&bp->drv_info_mutex); in bnx2x_update_mng_version()
3696 if (bp->drv_info_mng_owner) in bnx2x_update_mng_version()
3699 if (bp->state != BNX2X_STATE_OPEN) in bnx2x_update_mng_version()
3704 if (!CNIC_LOADED(bp)) in bnx2x_update_mng_version()
3708 memset(&bp->slowpath->drv_info_to_mcp, 0, in bnx2x_update_mng_version()
3710 bnx2x_drv_info_iscsi_stat(bp); in bnx2x_update_mng_version()
3711 version = bp->slowpath->drv_info_to_mcp.iscsi_stat.version; in bnx2x_update_mng_version()
3714 memset(&bp->slowpath->drv_info_to_mcp, 0, in bnx2x_update_mng_version()
3716 bnx2x_drv_info_fcoe_stat(bp); in bnx2x_update_mng_version()
3717 version = bp->slowpath->drv_info_to_mcp.fcoe_stat.version; in bnx2x_update_mng_version()
3721 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ETHERNET], ethver); in bnx2x_update_mng_version()
3722 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ISCSI], iscsiver); in bnx2x_update_mng_version()
3723 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_FCOE], fcoever); in bnx2x_update_mng_version()
3725 mutex_unlock(&bp->drv_info_mutex); in bnx2x_update_mng_version()
3731 void bnx2x_update_mfw_dump(struct bnx2x *bp) in bnx2x_update_mfw_dump() argument
3736 if (!SHMEM2_HAS(bp, drv_info)) in bnx2x_update_mfw_dump()
3740 SHMEM2_WR(bp, drv_info.epoc, (u32)ktime_get_real_seconds()); in bnx2x_update_mfw_dump()
3743 SHMEM2_WR(bp, drv_info.drv_ver, drv_ver); in bnx2x_update_mfw_dump()
3745 SHMEM2_WR(bp, drv_info.fw_ver, REG_RD(bp, XSEM_REG_PRAM)); in bnx2x_update_mfw_dump()
3748 valid_dump = SHMEM2_RD(bp, drv_info.valid_dump); in bnx2x_update_mfw_dump()
3757 static void bnx2x_oem_event(struct bnx2x *bp, u32 event) in bnx2x_oem_event() argument
3784 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { in bnx2x_oem_event()
3786 bp->flags |= MF_FUNC_DIS; in bnx2x_oem_event()
3788 bnx2x_e1h_disable(bp); in bnx2x_oem_event()
3791 bp->flags &= ~MF_FUNC_DIS; in bnx2x_oem_event()
3793 bnx2x_e1h_enable(bp); in bnx2x_oem_event()
3801 bnx2x_config_mf_bw(bp); in bnx2x_oem_event()
3808 bnx2x_fw_command(bp, cmd_fail, 0); in bnx2x_oem_event()
3810 bnx2x_fw_command(bp, cmd_ok, 0); in bnx2x_oem_event()
3814 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp) in bnx2x_sp_get_next() argument
3816 struct eth_spe *next_spe = bp->spq_prod_bd; in bnx2x_sp_get_next()
3818 if (bp->spq_prod_bd == bp->spq_last_bd) { in bnx2x_sp_get_next()
3819 bp->spq_prod_bd = bp->spq; in bnx2x_sp_get_next()
3820 bp->spq_prod_idx = 0; in bnx2x_sp_get_next()
3823 bp->spq_prod_bd++; in bnx2x_sp_get_next()
3824 bp->spq_prod_idx++; in bnx2x_sp_get_next()
3830 static void bnx2x_sp_prod_update(struct bnx2x *bp) in bnx2x_sp_prod_update() argument
3832 int func = BP_FUNC(bp); in bnx2x_sp_prod_update()
3841 REG_WR16_RELAXED(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func), in bnx2x_sp_prod_update()
3842 bp->spq_prod_idx); in bnx2x_sp_prod_update()
3879 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, in bnx2x_sp_post() argument
3887 if (unlikely(bp->panic)) { in bnx2x_sp_post()
3893 spin_lock_bh(&bp->spq_lock); in bnx2x_sp_post()
3896 if (!atomic_read(&bp->eq_spq_left)) { in bnx2x_sp_post()
3898 spin_unlock_bh(&bp->spq_lock); in bnx2x_sp_post()
3902 } else if (!atomic_read(&bp->cq_spq_left)) { in bnx2x_sp_post()
3904 spin_unlock_bh(&bp->spq_lock); in bnx2x_sp_post()
3909 spe = bnx2x_sp_get_next(bp); in bnx2x_sp_post()
3914 HW_CID(bp, cid)); in bnx2x_sp_post()
3923 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) & in bnx2x_sp_post()
3940 atomic_dec(&bp->eq_spq_left); in bnx2x_sp_post()
3942 atomic_dec(&bp->cq_spq_left); in bnx2x_sp_post()
3946 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping), in bnx2x_sp_post()
3947 (u32)(U64_LO(bp->spq_mapping) + in bnx2x_sp_post()
3948 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common, in bnx2x_sp_post()
3949 HW_CID(bp, cid), data_hi, data_lo, type, in bnx2x_sp_post()
3950 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left)); in bnx2x_sp_post()
3952 bnx2x_sp_prod_update(bp); in bnx2x_sp_post()
3953 spin_unlock_bh(&bp->spq_lock); in bnx2x_sp_post()
3958 static int bnx2x_acquire_alr(struct bnx2x *bp) in bnx2x_acquire_alr() argument
3965 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK); in bnx2x_acquire_alr()
3966 val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK); in bnx2x_acquire_alr()
3981 static void bnx2x_release_alr(struct bnx2x *bp) in bnx2x_release_alr() argument
3983 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0); in bnx2x_release_alr()
3989 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp) in bnx2x_update_dsb_idx() argument
3991 struct host_sp_status_block *def_sb = bp->def_status_blk; in bnx2x_update_dsb_idx()
3995 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) { in bnx2x_update_dsb_idx()
3996 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index; in bnx2x_update_dsb_idx()
4000 if (bp->def_idx != def_sb->sp_sb.running_index) { in bnx2x_update_dsb_idx()
4001 bp->def_idx = def_sb->sp_sb.running_index; in bnx2x_update_dsb_idx()
4014 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted) in bnx2x_attn_int_asserted() argument
4016 int port = BP_PORT(bp); in bnx2x_attn_int_asserted()
4025 if (bp->attn_state & asserted) in bnx2x_attn_int_asserted()
4028 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); in bnx2x_attn_int_asserted()
4029 aeu_mask = REG_RD(bp, aeu_addr); in bnx2x_attn_int_asserted()
4036 REG_WR(bp, aeu_addr, aeu_mask); in bnx2x_attn_int_asserted()
4037 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); in bnx2x_attn_int_asserted()
4039 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); in bnx2x_attn_int_asserted()
4040 bp->attn_state |= asserted; in bnx2x_attn_int_asserted()
4041 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); in bnx2x_attn_int_asserted()
4046 bnx2x_acquire_phy_lock(bp); in bnx2x_attn_int_asserted()
4049 nig_mask = REG_RD(bp, nig_int_mask_addr); in bnx2x_attn_int_asserted()
4055 REG_WR(bp, nig_int_mask_addr, 0); in bnx2x_attn_int_asserted()
4057 bnx2x_link_attn(bp); in bnx2x_attn_int_asserted()
4077 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0); in bnx2x_attn_int_asserted()
4081 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0); in bnx2x_attn_int_asserted()
4085 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0); in bnx2x_attn_int_asserted()
4090 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0); in bnx2x_attn_int_asserted()
4094 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0); in bnx2x_attn_int_asserted()
4098 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0); in bnx2x_attn_int_asserted()
4104 if (bp->common.int_block == INT_BLOCK_HC) in bnx2x_attn_int_asserted()
4111 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); in bnx2x_attn_int_asserted()
4112 REG_WR(bp, reg_addr, asserted); in bnx2x_attn_int_asserted()
4119 if (bp->common.int_block != INT_BLOCK_HC) { in bnx2x_attn_int_asserted()
4122 igu_acked = REG_RD(bp, in bnx2x_attn_int_asserted()
4131 REG_WR(bp, nig_int_mask_addr, nig_mask); in bnx2x_attn_int_asserted()
4132 bnx2x_release_phy_lock(bp); in bnx2x_attn_int_asserted()
4136 static void bnx2x_fan_failure(struct bnx2x *bp) in bnx2x_fan_failure() argument
4138 int port = BP_PORT(bp); in bnx2x_fan_failure()
4142 SHMEM_RD(bp, in bnx2x_fan_failure()
4147 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config, in bnx2x_fan_failure()
4151 …netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card … in bnx2x_fan_failure()
4158 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_FAN_FAILURE, 0); in bnx2x_fan_failure()
4161 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn) in bnx2x_attn_int_deasserted0() argument
4163 int port = BP_PORT(bp); in bnx2x_attn_int_deasserted0()
4172 val = REG_RD(bp, reg_offset); in bnx2x_attn_int_deasserted0()
4174 REG_WR(bp, reg_offset, val); in bnx2x_attn_int_deasserted0()
4179 bnx2x_hw_reset_phy(&bp->link_params); in bnx2x_attn_int_deasserted0()
4180 bnx2x_fan_failure(bp); in bnx2x_attn_int_deasserted0()
4183 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) { in bnx2x_attn_int_deasserted0()
4184 bnx2x_acquire_phy_lock(bp); in bnx2x_attn_int_deasserted0()
4185 bnx2x_handle_module_detect_int(&bp->link_params); in bnx2x_attn_int_deasserted0()
4186 bnx2x_release_phy_lock(bp); in bnx2x_attn_int_deasserted0()
4191 val = REG_RD(bp, reg_offset); in bnx2x_attn_int_deasserted0()
4193 REG_WR(bp, reg_offset, val); in bnx2x_attn_int_deasserted0()
4201 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn) in bnx2x_attn_int_deasserted1() argument
4207 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR); in bnx2x_attn_int_deasserted1()
4216 int port = BP_PORT(bp); in bnx2x_attn_int_deasserted1()
4222 val = REG_RD(bp, reg_offset); in bnx2x_attn_int_deasserted1()
4224 REG_WR(bp, reg_offset, val); in bnx2x_attn_int_deasserted1()
4232 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn) in bnx2x_attn_int_deasserted2() argument
4238 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR); in bnx2x_attn_int_deasserted2()
4246 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0); in bnx2x_attn_int_deasserted2()
4252 if (!CHIP_IS_E1x(bp)) { in bnx2x_attn_int_deasserted2()
4253 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1); in bnx2x_attn_int_deasserted2()
4260 int port = BP_PORT(bp); in bnx2x_attn_int_deasserted2()
4266 val = REG_RD(bp, reg_offset); in bnx2x_attn_int_deasserted2()
4268 REG_WR(bp, reg_offset, val); in bnx2x_attn_int_deasserted2()
4276 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn) in bnx2x_attn_int_deasserted3() argument
4283 int func = BP_FUNC(bp); in bnx2x_attn_int_deasserted3()
4285 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); in bnx2x_attn_int_deasserted3()
4286 bnx2x_read_mf_cfg(bp); in bnx2x_attn_int_deasserted3()
4287 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp, in bnx2x_attn_int_deasserted3()
4288 func_mf_config[BP_ABS_FUNC(bp)].config); in bnx2x_attn_int_deasserted3()
4289 val = SHMEM_RD(bp, in bnx2x_attn_int_deasserted3()
4290 func_mb[BP_FW_MB_IDX(bp)].drv_status); in bnx2x_attn_int_deasserted3()
4294 bnx2x_oem_event(bp, in bnx2x_attn_int_deasserted3()
4299 bnx2x_set_mf_bw(bp); in bnx2x_attn_int_deasserted3()
4302 bnx2x_handle_drv_info_req(bp); in bnx2x_attn_int_deasserted3()
4305 bnx2x_schedule_iov_task(bp, in bnx2x_attn_int_deasserted3()
4308 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF)) in bnx2x_attn_int_deasserted3()
4309 bnx2x_pmf_update(bp); in bnx2x_attn_int_deasserted3()
4311 if (bp->port.pmf && in bnx2x_attn_int_deasserted3()
4313 bp->dcbx_enabled > 0) in bnx2x_attn_int_deasserted3()
4315 bnx2x_dcbx_set_params(bp, in bnx2x_attn_int_deasserted3()
4318 bnx2x_handle_afex_cmd(bp, in bnx2x_attn_int_deasserted3()
4321 bnx2x_handle_eee_event(bp); in bnx2x_attn_int_deasserted3()
4324 bnx2x_schedule_sp_rtnl(bp, in bnx2x_attn_int_deasserted3()
4327 if (bp->link_vars.periodic_flags & in bnx2x_attn_int_deasserted3()
4330 bnx2x_acquire_phy_lock(bp); in bnx2x_attn_int_deasserted3()
4331 bp->link_vars.periodic_flags &= in bnx2x_attn_int_deasserted3()
4333 bnx2x_release_phy_lock(bp); in bnx2x_attn_int_deasserted3()
4334 if (IS_MF(bp)) in bnx2x_attn_int_deasserted3()
4335 bnx2x_link_sync_notify(bp); in bnx2x_attn_int_deasserted3()
4336 bnx2x_link_report(bp); in bnx2x_attn_int_deasserted3()
4341 bnx2x__link_status_update(bp); in bnx2x_attn_int_deasserted3()
4345 bnx2x_mc_assert(bp); in bnx2x_attn_int_deasserted3()
4346 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0); in bnx2x_attn_int_deasserted3()
4347 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0); in bnx2x_attn_int_deasserted3()
4348 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0); in bnx2x_attn_int_deasserted3()
4349 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0); in bnx2x_attn_int_deasserted3()
4355 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0); in bnx2x_attn_int_deasserted3()
4356 bnx2x_fw_dump(bp); in bnx2x_attn_int_deasserted3()
4365 val = CHIP_IS_E1(bp) ? 0 : in bnx2x_attn_int_deasserted3()
4366 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN); in bnx2x_attn_int_deasserted3()
4370 val = CHIP_IS_E1(bp) ? 0 : in bnx2x_attn_int_deasserted3()
4371 REG_RD(bp, MISC_REG_GRC_RSV_ATTN); in bnx2x_attn_int_deasserted3()
4374 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff); in bnx2x_attn_int_deasserted3()
4407 void bnx2x_set_reset_global(struct bnx2x *bp) in bnx2x_set_reset_global() argument
4410 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); in bnx2x_set_reset_global()
4411 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); in bnx2x_set_reset_global()
4412 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT); in bnx2x_set_reset_global()
4413 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); in bnx2x_set_reset_global()
4421 static void bnx2x_clear_reset_global(struct bnx2x *bp) in bnx2x_clear_reset_global() argument
4424 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); in bnx2x_clear_reset_global()
4425 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); in bnx2x_clear_reset_global()
4426 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT)); in bnx2x_clear_reset_global()
4427 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); in bnx2x_clear_reset_global()
4435 static bool bnx2x_reset_is_global(struct bnx2x *bp) in bnx2x_reset_is_global() argument
4437 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); in bnx2x_reset_is_global()
4448 static void bnx2x_set_reset_done(struct bnx2x *bp) in bnx2x_set_reset_done() argument
4451 u32 bit = BP_PATH(bp) ? in bnx2x_set_reset_done()
4453 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); in bnx2x_set_reset_done()
4454 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); in bnx2x_set_reset_done()
4458 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); in bnx2x_set_reset_done()
4460 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); in bnx2x_set_reset_done()
4468 void bnx2x_set_reset_in_progress(struct bnx2x *bp) in bnx2x_set_reset_in_progress() argument
4471 u32 bit = BP_PATH(bp) ? in bnx2x_set_reset_in_progress()
4473 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); in bnx2x_set_reset_in_progress()
4474 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); in bnx2x_set_reset_in_progress()
4478 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); in bnx2x_set_reset_in_progress()
4479 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); in bnx2x_set_reset_in_progress()
4486 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine) in bnx2x_reset_is_done() argument
4488 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); in bnx2x_reset_is_done()
4501 void bnx2x_set_pf_load(struct bnx2x *bp) in bnx2x_set_pf_load() argument
4504 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : in bnx2x_set_pf_load()
4506 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : in bnx2x_set_pf_load()
4509 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); in bnx2x_set_pf_load()
4510 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); in bnx2x_set_pf_load()
4518 val1 |= (1 << bp->pf_num); in bnx2x_set_pf_load()
4526 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); in bnx2x_set_pf_load()
4527 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); in bnx2x_set_pf_load()
4539 bool bnx2x_clear_pf_load(struct bnx2x *bp) in bnx2x_clear_pf_load() argument
4542 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : in bnx2x_clear_pf_load()
4544 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : in bnx2x_clear_pf_load()
4547 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); in bnx2x_clear_pf_load()
4548 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); in bnx2x_clear_pf_load()
4555 val1 &= ~(1 << bp->pf_num); in bnx2x_clear_pf_load()
4563 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); in bnx2x_clear_pf_load()
4564 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); in bnx2x_clear_pf_load()
4573 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine) in bnx2x_get_load_status() argument
4579 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); in bnx2x_get_load_status()
4591 static void _print_parity(struct bnx2x *bp, u32 reg) in _print_parity() argument
4593 pr_cont(" [0x%08x] ", REG_RD(bp, reg)); in _print_parity()
4601 static bool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig, in bnx2x_check_blocks_with_parity0() argument
4619 _print_parity(bp, in bnx2x_check_blocks_with_parity0()
4625 _print_parity(bp, PRS_REG_PRS_PRTY_STS); in bnx2x_check_blocks_with_parity0()
4629 _print_parity(bp, in bnx2x_check_blocks_with_parity0()
4635 _print_parity(bp, SRC_REG_SRC_PRTY_STS); in bnx2x_check_blocks_with_parity0()
4639 _print_parity(bp, TCM_REG_TCM_PRTY_STS); in bnx2x_check_blocks_with_parity0()
4644 _print_parity(bp, in bnx2x_check_blocks_with_parity0()
4646 _print_parity(bp, in bnx2x_check_blocks_with_parity0()
4651 _print_parity(bp, GRCBASE_XPB + in bnx2x_check_blocks_with_parity0()
4665 static bool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig, in bnx2x_check_blocks_with_parity1() argument
4683 _print_parity(bp, PBF_REG_PBF_PRTY_STS); in bnx2x_check_blocks_with_parity1()
4689 _print_parity(bp, QM_REG_QM_PRTY_STS); in bnx2x_check_blocks_with_parity1()
4695 _print_parity(bp, TM_REG_TM_PRTY_STS); in bnx2x_check_blocks_with_parity1()
4701 _print_parity(bp, in bnx2x_check_blocks_with_parity1()
4708 _print_parity(bp, XCM_REG_XCM_PRTY_STS); in bnx2x_check_blocks_with_parity1()
4715 _print_parity(bp, in bnx2x_check_blocks_with_parity1()
4717 _print_parity(bp, in bnx2x_check_blocks_with_parity1()
4725 _print_parity(bp, in bnx2x_check_blocks_with_parity1()
4732 if (CHIP_IS_E1x(bp)) { in bnx2x_check_blocks_with_parity1()
4733 _print_parity(bp, in bnx2x_check_blocks_with_parity1()
4736 _print_parity(bp, in bnx2x_check_blocks_with_parity1()
4738 _print_parity(bp, in bnx2x_check_blocks_with_parity1()
4753 _print_parity(bp, DBG_REG_DBG_PRTY_STS); in bnx2x_check_blocks_with_parity1()
4759 _print_parity(bp, in bnx2x_check_blocks_with_parity1()
4766 _print_parity(bp, UCM_REG_UCM_PRTY_STS); in bnx2x_check_blocks_with_parity1()
4773 _print_parity(bp, in bnx2x_check_blocks_with_parity1()
4775 _print_parity(bp, in bnx2x_check_blocks_with_parity1()
4782 _print_parity(bp, GRCBASE_UPB + in bnx2x_check_blocks_with_parity1()
4789 _print_parity(bp, in bnx2x_check_blocks_with_parity1()
4796 _print_parity(bp, CCM_REG_CCM_PRTY_STS); in bnx2x_check_blocks_with_parity1()
4809 static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig, in bnx2x_check_blocks_with_parity2() argument
4827 _print_parity(bp, in bnx2x_check_blocks_with_parity2()
4829 _print_parity(bp, in bnx2x_check_blocks_with_parity2()
4834 _print_parity(bp, PXP_REG_PXP_PRTY_STS); in bnx2x_check_blocks_with_parity2()
4835 _print_parity(bp, in bnx2x_check_blocks_with_parity2()
4837 _print_parity(bp, in bnx2x_check_blocks_with_parity2()
4846 _print_parity(bp, in bnx2x_check_blocks_with_parity2()
4851 _print_parity(bp, CDU_REG_CDU_PRTY_STS); in bnx2x_check_blocks_with_parity2()
4855 _print_parity(bp, in bnx2x_check_blocks_with_parity2()
4860 if (CHIP_IS_E1x(bp)) in bnx2x_check_blocks_with_parity2()
4861 _print_parity(bp, in bnx2x_check_blocks_with_parity2()
4864 _print_parity(bp, in bnx2x_check_blocks_with_parity2()
4869 _print_parity(bp, in bnx2x_check_blocks_with_parity2()
4883 static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig, in bnx2x_check_blocks_with_parity3() argument
4919 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, in bnx2x_check_blocks_with_parity3()
4932 static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig, in bnx2x_check_blocks_with_parity4() argument
4950 _print_parity(bp, in bnx2x_check_blocks_with_parity4()
4955 _print_parity(bp, in bnx2x_check_blocks_with_parity4()
4968 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print, in bnx2x_parity_attn() argument
4993 netdev_err(bp->dev, in bnx2x_parity_attn()
4999 res |= bnx2x_check_blocks_with_parity0(bp, in bnx2x_parity_attn()
5001 res |= bnx2x_check_blocks_with_parity1(bp, in bnx2x_parity_attn()
5003 res |= bnx2x_check_blocks_with_parity2(bp, in bnx2x_parity_attn()
5005 res |= bnx2x_check_blocks_with_parity3(bp, in bnx2x_parity_attn()
5007 res |= bnx2x_check_blocks_with_parity4(bp, in bnx2x_parity_attn()
5024 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print) in bnx2x_chk_parity_attn() argument
5027 int port = BP_PORT(bp); in bnx2x_chk_parity_attn()
5029 attn.sig[0] = REG_RD(bp, in bnx2x_chk_parity_attn()
5032 attn.sig[1] = REG_RD(bp, in bnx2x_chk_parity_attn()
5035 attn.sig[2] = REG_RD(bp, in bnx2x_chk_parity_attn()
5038 attn.sig[3] = REG_RD(bp, in bnx2x_chk_parity_attn()
5044 attn.sig[3] &= ((REG_RD(bp, in bnx2x_chk_parity_attn()
5050 if (!CHIP_IS_E1x(bp)) in bnx2x_chk_parity_attn()
5051 attn.sig[4] = REG_RD(bp, in bnx2x_chk_parity_attn()
5055 return bnx2x_parity_attn(bp, global, print, attn.sig); in bnx2x_chk_parity_attn()
5058 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn) in bnx2x_attn_int_deasserted4() argument
5063 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR); in bnx2x_attn_int_deasserted4()
5087 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR); in bnx2x_attn_int_deasserted4()
5111 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted) in bnx2x_attn_int_deasserted() argument
5114 int port = BP_PORT(bp); in bnx2x_attn_int_deasserted()
5123 bnx2x_acquire_alr(bp); in bnx2x_attn_int_deasserted()
5125 if (bnx2x_chk_parity_attn(bp, &global, true)) { in bnx2x_attn_int_deasserted()
5127 bp->recovery_state = BNX2X_RECOVERY_INIT; in bnx2x_attn_int_deasserted()
5128 schedule_delayed_work(&bp->sp_rtnl_task, 0); in bnx2x_attn_int_deasserted()
5130 bnx2x_int_disable(bp); in bnx2x_attn_int_deasserted()
5137 bnx2x_release_alr(bp); in bnx2x_attn_int_deasserted()
5141 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4); in bnx2x_attn_int_deasserted()
5142 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4); in bnx2x_attn_int_deasserted()
5143 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4); in bnx2x_attn_int_deasserted()
5144 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4); in bnx2x_attn_int_deasserted()
5145 if (!CHIP_IS_E1x(bp)) in bnx2x_attn_int_deasserted()
5147 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4); in bnx2x_attn_int_deasserted()
5156 group_mask = &bp->attn_group[index]; in bnx2x_attn_int_deasserted()
5164 bnx2x_attn_int_deasserted4(bp, in bnx2x_attn_int_deasserted()
5166 bnx2x_attn_int_deasserted3(bp, in bnx2x_attn_int_deasserted()
5168 bnx2x_attn_int_deasserted1(bp, in bnx2x_attn_int_deasserted()
5170 bnx2x_attn_int_deasserted2(bp, in bnx2x_attn_int_deasserted()
5172 bnx2x_attn_int_deasserted0(bp, in bnx2x_attn_int_deasserted()
5177 bnx2x_release_alr(bp); in bnx2x_attn_int_deasserted()
5179 if (bp->common.int_block == INT_BLOCK_HC) in bnx2x_attn_int_deasserted()
5187 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); in bnx2x_attn_int_deasserted()
5188 REG_WR(bp, reg_addr, val); in bnx2x_attn_int_deasserted()
5190 if (~bp->attn_state & deasserted) in bnx2x_attn_int_deasserted()
5196 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); in bnx2x_attn_int_deasserted()
5197 aeu_mask = REG_RD(bp, reg_addr); in bnx2x_attn_int_deasserted()
5204 REG_WR(bp, reg_addr, aeu_mask); in bnx2x_attn_int_deasserted()
5205 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); in bnx2x_attn_int_deasserted()
5207 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); in bnx2x_attn_int_deasserted()
5208 bp->attn_state &= ~deasserted; in bnx2x_attn_int_deasserted()
5209 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); in bnx2x_attn_int_deasserted()
5212 static void bnx2x_attn_int(struct bnx2x *bp) in bnx2x_attn_int() argument
5215 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block. in bnx2x_attn_int()
5217 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block. in bnx2x_attn_int()
5219 u32 attn_state = bp->attn_state; in bnx2x_attn_int()
5234 bnx2x_attn_int_asserted(bp, asserted); in bnx2x_attn_int()
5237 bnx2x_attn_int_deasserted(bp, deasserted); in bnx2x_attn_int()
5240 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment, in bnx2x_igu_ack_sb() argument
5243 u32 igu_addr = bp->igu_base_addr; in bnx2x_igu_ack_sb()
5245 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update, in bnx2x_igu_ack_sb()
5249 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod) in bnx2x_update_eq_prod() argument
5252 storm_memset_eq_prod(bp, prod, BP_FUNC(bp)); in bnx2x_update_eq_prod()
5255 static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid, in bnx2x_cnic_handle_cfc_del() argument
5260 if (!bp->cnic_eth_dev.starting_cid || in bnx2x_cnic_handle_cfc_del()
5261 (cid < bp->cnic_eth_dev.starting_cid && in bnx2x_cnic_handle_cfc_del()
5262 cid != bp->cnic_eth_dev.iscsi_l2_cid)) in bnx2x_cnic_handle_cfc_del()
5271 bnx2x_panic_dump(bp, false); in bnx2x_cnic_handle_cfc_del()
5273 bnx2x_cnic_cfc_comp(bp, cid, err); in bnx2x_cnic_handle_cfc_del()
5277 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp) in bnx2x_handle_mcast_eqe() argument
5284 rparam.mcast_obj = &bp->mcast_obj; in bnx2x_handle_mcast_eqe()
5286 netif_addr_lock_bh(bp->dev); in bnx2x_handle_mcast_eqe()
5289 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw); in bnx2x_handle_mcast_eqe()
5292 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) { in bnx2x_handle_mcast_eqe()
5293 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT); in bnx2x_handle_mcast_eqe()
5299 netif_addr_unlock_bh(bp->dev); in bnx2x_handle_mcast_eqe()
5302 static void bnx2x_handle_classification_eqe(struct bnx2x *bp, in bnx2x_handle_classification_eqe() argument
5317 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp))) in bnx2x_handle_classification_eqe()
5318 vlan_mac_obj = &bp->iscsi_l2_mac_obj; in bnx2x_handle_classification_eqe()
5320 vlan_mac_obj = &bp->sp_objs[cid].mac_obj; in bnx2x_handle_classification_eqe()
5325 vlan_mac_obj = &bp->sp_objs[cid].vlan_obj; in bnx2x_handle_classification_eqe()
5332 bnx2x_handle_mcast_eqe(bp); in bnx2x_handle_classification_eqe()
5339 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags); in bnx2x_handle_classification_eqe()
5347 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
5349 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp) in bnx2x_handle_rx_mode_eqe() argument
5351 netif_addr_lock_bh(bp->dev); in bnx2x_handle_rx_mode_eqe()
5353 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); in bnx2x_handle_rx_mode_eqe()
5356 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state)) in bnx2x_handle_rx_mode_eqe()
5357 bnx2x_set_storm_rx_mode(bp); in bnx2x_handle_rx_mode_eqe()
5359 &bp->sp_state)) in bnx2x_handle_rx_mode_eqe()
5360 bnx2x_set_iscsi_eth_rx_mode(bp, true); in bnx2x_handle_rx_mode_eqe()
5362 &bp->sp_state)) in bnx2x_handle_rx_mode_eqe()
5363 bnx2x_set_iscsi_eth_rx_mode(bp, false); in bnx2x_handle_rx_mode_eqe()
5365 netif_addr_unlock_bh(bp->dev); in bnx2x_handle_rx_mode_eqe()
5368 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp, in bnx2x_after_afex_vif_lists() argument
5375 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK, in bnx2x_after_afex_vif_lists()
5380 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0); in bnx2x_after_afex_vif_lists()
5385 static void bnx2x_after_function_update(struct bnx2x *bp) in bnx2x_after_function_update() argument
5404 if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) { in bnx2x_after_function_update()
5409 (bp->afex_def_vlan_tag & VLAN_VID_MASK); in bnx2x_after_function_update()
5413 for_each_eth_queue(bp, q) { in bnx2x_after_function_update()
5415 fp = &bp->fp[q]; in bnx2x_after_function_update()
5416 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; in bnx2x_after_function_update()
5419 rc = bnx2x_queue_state_change(bp, &queue_params); in bnx2x_after_function_update()
5425 if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) { in bnx2x_after_function_update()
5426 fp = &bp->fp[FCOE_IDX(bp)]; in bnx2x_after_function_update()
5427 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; in bnx2x_after_function_update()
5434 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state); in bnx2x_after_function_update()
5438 rc = bnx2x_queue_state_change(bp, &queue_params); in bnx2x_after_function_update()
5444 bnx2x_link_report(bp); in bnx2x_after_function_update()
5445 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); in bnx2x_after_function_update()
5450 struct bnx2x *bp, u32 cid) in bnx2x_cid_to_q_obj() argument
5454 if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp))) in bnx2x_cid_to_q_obj()
5455 return &bnx2x_fcoe_sp_obj(bp, q_obj); in bnx2x_cid_to_q_obj()
5457 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj; in bnx2x_cid_to_q_obj()
5460 static void bnx2x_eq_int(struct bnx2x *bp) in bnx2x_eq_int() argument
5469 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj; in bnx2x_eq_int()
5470 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw; in bnx2x_eq_int()
5472 hw_cons = le16_to_cpu(*bp->eq_cons_sb); in bnx2x_eq_int()
5486 sw_cons = bp->eq_cons; in bnx2x_eq_int()
5487 sw_prod = bp->eq_prod; in bnx2x_eq_int()
5490 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left)); in bnx2x_eq_int()
5495 elem = &bp->eq_ring[EQ_DESC(sw_cons)]; in bnx2x_eq_int()
5497 rc = bnx2x_iov_eq_sp_event(bp, elem); in bnx2x_eq_int()
5509 bnx2x_vf_mbx_schedule(bp, in bnx2x_eq_int()
5516 bp->stats_comp++); in bnx2x_eq_int()
5533 if (CNIC_LOADED(bp) && in bnx2x_eq_int()
5534 !bnx2x_cnic_handle_cfc_del(bp, cid, elem)) in bnx2x_eq_int()
5537 q_obj = bnx2x_cid_to_q_obj(bp, cid); in bnx2x_eq_int()
5539 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL)) in bnx2x_eq_int()
5546 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED); in bnx2x_eq_int()
5547 if (f_obj->complete_cmd(bp, f_obj, in bnx2x_eq_int()
5554 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED); in bnx2x_eq_int()
5555 if (f_obj->complete_cmd(bp, f_obj, in bnx2x_eq_int()
5566 bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE)) in bnx2x_eq_int()
5574 f_obj->complete_cmd(bp, f_obj, in bnx2x_eq_int()
5581 bnx2x_schedule_sp_rtnl(bp, cmd, 0); in bnx2x_eq_int()
5587 f_obj->complete_cmd(bp, f_obj, in bnx2x_eq_int()
5589 bnx2x_after_afex_vif_lists(bp, elem); in bnx2x_eq_int()
5594 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START)) in bnx2x_eq_int()
5602 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP)) in bnx2x_eq_int()
5610 if (f_obj->complete_cmd(bp, f_obj, in bnx2x_eq_int()
5616 switch (opcode | bp->state) { in bnx2x_eq_int()
5639 bnx2x_handle_classification_eqe(bp, elem); in bnx2x_eq_int()
5649 bnx2x_handle_mcast_eqe(bp); in bnx2x_eq_int()
5659 bnx2x_handle_rx_mode_eqe(bp); in bnx2x_eq_int()
5664 elem->message.opcode, bp->state); in bnx2x_eq_int()
5671 atomic_add(spqe_cnt, &bp->eq_spq_left); in bnx2x_eq_int()
5673 bp->eq_cons = sw_cons; in bnx2x_eq_int()
5674 bp->eq_prod = sw_prod; in bnx2x_eq_int()
5679 bnx2x_update_eq_prod(bp, bp->eq_prod); in bnx2x_eq_int()
5684 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work); in bnx2x_sp_task() local
5690 if (atomic_read(&bp->interrupt_occurred)) { in bnx2x_sp_task()
5693 u16 status = bnx2x_update_dsb_idx(bp); in bnx2x_sp_task()
5697 atomic_set(&bp->interrupt_occurred, 0); in bnx2x_sp_task()
5701 bnx2x_attn_int(bp); in bnx2x_sp_task()
5707 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); in bnx2x_sp_task()
5709 if (FCOE_INIT(bp) && in bnx2x_sp_task()
5715 napi_schedule(&bnx2x_fcoe(bp, napi)); in bnx2x_sp_task()
5720 bnx2x_eq_int(bp); in bnx2x_sp_task()
5721 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, in bnx2x_sp_task()
5722 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1); in bnx2x_sp_task()
5733 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID, in bnx2x_sp_task()
5734 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1); in bnx2x_sp_task()
5739 &bp->sp_state)) { in bnx2x_sp_task()
5740 bnx2x_link_report(bp); in bnx2x_sp_task()
5741 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); in bnx2x_sp_task()
5748 struct bnx2x *bp = netdev_priv(dev); in bnx2x_msix_sp_int() local
5750 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, in bnx2x_msix_sp_int()
5754 if (unlikely(bp->panic)) in bnx2x_msix_sp_int()
5758 if (CNIC_LOADED(bp)) { in bnx2x_msix_sp_int()
5762 c_ops = rcu_dereference(bp->cnic_ops); in bnx2x_msix_sp_int()
5764 c_ops->cnic_handler(bp->cnic_data, NULL); in bnx2x_msix_sp_int()
5771 bnx2x_schedule_sp_task(bp); in bnx2x_msix_sp_int()
5778 void bnx2x_drv_pulse(struct bnx2x *bp) in bnx2x_drv_pulse() argument
5780 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb, in bnx2x_drv_pulse()
5781 bp->fw_drv_pulse_wr_seq); in bnx2x_drv_pulse()
5786 struct bnx2x *bp = from_timer(bp, t, timer); in bnx2x_timer() local
5788 if (!netif_running(bp->dev)) in bnx2x_timer()
5791 if (IS_PF(bp) && in bnx2x_timer()
5792 !BP_NOMCP(bp)) { in bnx2x_timer()
5793 int mb_idx = BP_FW_MB_IDX(bp); in bnx2x_timer()
5797 ++bp->fw_drv_pulse_wr_seq; in bnx2x_timer()
5798 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK; in bnx2x_timer()
5799 drv_pulse = bp->fw_drv_pulse_wr_seq; in bnx2x_timer()
5800 bnx2x_drv_pulse(bp); in bnx2x_timer()
5802 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) & in bnx2x_timer()
5814 if (bp->state == BNX2X_STATE_OPEN) in bnx2x_timer()
5815 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE); in bnx2x_timer()
5818 if (IS_VF(bp)) in bnx2x_timer()
5819 bnx2x_timer_sriov(bp); in bnx2x_timer()
5821 mod_timer(&bp->timer, jiffies + bp->current_interval); in bnx2x_timer()
5832 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len) in bnx2x_fill() argument
5837 REG_WR(bp, addr + i, fill); in bnx2x_fill()
5840 REG_WR8(bp, addr + i, fill); in bnx2x_fill()
5844 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp, in bnx2x_wr_fp_sb_data() argument
5851 REG_WR(bp, BAR_CSTRORM_INTMEM + in bnx2x_wr_fp_sb_data()
5857 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id) in bnx2x_zero_fp_sb() argument
5865 if (!CHIP_IS_E1x(bp)) { in bnx2x_zero_fp_sb()
5879 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); in bnx2x_zero_fp_sb()
5881 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + in bnx2x_zero_fp_sb()
5884 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + in bnx2x_zero_fp_sb()
5890 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp, in bnx2x_wr_sp_sb_data() argument
5893 int func = BP_FUNC(bp); in bnx2x_wr_sp_sb_data()
5896 REG_WR(bp, BAR_CSTRORM_INTMEM + in bnx2x_wr_sp_sb_data()
5902 static void bnx2x_zero_sp_sb(struct bnx2x *bp) in bnx2x_zero_sp_sb() argument
5904 int func = BP_FUNC(bp); in bnx2x_zero_sp_sb()
5911 bnx2x_wr_sp_sb_data(bp, &sp_sb_data); in bnx2x_zero_sp_sb()
5913 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + in bnx2x_zero_sp_sb()
5916 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + in bnx2x_zero_sp_sb()
5959 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid, in bnx2x_init_sb() argument
5970 if (CHIP_INT_MODE_IS_BC(bp)) in bnx2x_init_sb()
5975 bnx2x_zero_fp_sb(bp, fw_sb_id); in bnx2x_init_sb()
5977 if (!CHIP_IS_E1x(bp)) { in bnx2x_init_sb()
5980 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp); in bnx2x_init_sb()
5983 sb_data_e2.common.p_func.vnic_id = BP_VN(bp); in bnx2x_init_sb()
5995 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp); in bnx2x_init_sb()
5998 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp); in bnx2x_init_sb()
6016 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); in bnx2x_init_sb()
6019 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id, in bnx2x_update_coalesce_sb() argument
6022 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS, in bnx2x_update_coalesce_sb()
6024 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, in bnx2x_update_coalesce_sb()
6027 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, in bnx2x_update_coalesce_sb()
6030 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, in bnx2x_update_coalesce_sb()
6035 static void bnx2x_init_def_sb(struct bnx2x *bp) in bnx2x_init_def_sb() argument
6037 struct host_sp_status_block *def_sb = bp->def_status_blk; in bnx2x_init_def_sb()
6038 dma_addr_t mapping = bp->def_status_blk_mapping; in bnx2x_init_def_sb()
6041 int port = BP_PORT(bp); in bnx2x_init_def_sb()
6042 int func = BP_FUNC(bp); in bnx2x_init_def_sb()
6049 if (CHIP_INT_MODE_IS_BC(bp)) { in bnx2x_init_def_sb()
6053 igu_sp_sb_index = bp->igu_dsb_id; in bnx2x_init_def_sb()
6062 bp->attn_state = 0; in bnx2x_init_def_sb()
6072 bp->attn_group[index].sig[sindex] = in bnx2x_init_def_sb()
6073 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index); in bnx2x_init_def_sb()
6075 if (!CHIP_IS_E1x(bp)) in bnx2x_init_def_sb()
6081 bp->attn_group[index].sig[4] = REG_RD(bp, in bnx2x_init_def_sb()
6084 bp->attn_group[index].sig[4] = 0; in bnx2x_init_def_sb()
6087 if (bp->common.int_block == INT_BLOCK_HC) { in bnx2x_init_def_sb()
6091 REG_WR(bp, reg_offset, U64_LO(section)); in bnx2x_init_def_sb()
6092 REG_WR(bp, reg_offset + 4, U64_HI(section)); in bnx2x_init_def_sb()
6093 } else if (!CHIP_IS_E1x(bp)) { in bnx2x_init_def_sb()
6094 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section)); in bnx2x_init_def_sb()
6095 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section)); in bnx2x_init_def_sb()
6101 bnx2x_zero_sp_sb(bp); in bnx2x_init_def_sb()
6110 sp_sb_data.p_func.vnic_id = BP_VN(bp); in bnx2x_init_def_sb()
6113 bnx2x_wr_sp_sb_data(bp, &sp_sb_data); in bnx2x_init_def_sb()
6115 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0); in bnx2x_init_def_sb()
6118 void bnx2x_update_coalesce(struct bnx2x *bp) in bnx2x_update_coalesce() argument
6122 for_each_eth_queue(bp, i) in bnx2x_update_coalesce()
6123 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id, in bnx2x_update_coalesce()
6124 bp->tx_ticks, bp->rx_ticks); in bnx2x_update_coalesce()
6127 static void bnx2x_init_sp_ring(struct bnx2x *bp) in bnx2x_init_sp_ring() argument
6129 spin_lock_init(&bp->spq_lock); in bnx2x_init_sp_ring()
6130 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING); in bnx2x_init_sp_ring()
6132 bp->spq_prod_idx = 0; in bnx2x_init_sp_ring()
6133 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX; in bnx2x_init_sp_ring()
6134 bp->spq_prod_bd = bp->spq; in bnx2x_init_sp_ring()
6135 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT; in bnx2x_init_sp_ring()
6138 static void bnx2x_init_eq_ring(struct bnx2x *bp) in bnx2x_init_eq_ring() argument
6143 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1]; in bnx2x_init_eq_ring()
6146 cpu_to_le32(U64_HI(bp->eq_mapping + in bnx2x_init_eq_ring()
6149 cpu_to_le32(U64_LO(bp->eq_mapping + in bnx2x_init_eq_ring()
6152 bp->eq_cons = 0; in bnx2x_init_eq_ring()
6153 bp->eq_prod = NUM_EQ_DESC; in bnx2x_init_eq_ring()
6154 bp->eq_cons_sb = BNX2X_EQ_INDEX; in bnx2x_init_eq_ring()
6156 atomic_set(&bp->eq_spq_left, in bnx2x_init_eq_ring()
6161 static int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id, in bnx2x_set_q_rx_mode() argument
6175 ramrod_param.rx_mode_obj = &bp->rx_mode_obj; in bnx2x_set_q_rx_mode()
6176 ramrod_param.func_id = BP_FUNC(bp); in bnx2x_set_q_rx_mode()
6178 ramrod_param.pstate = &bp->sp_state; in bnx2x_set_q_rx_mode()
6181 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata); in bnx2x_set_q_rx_mode()
6182 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata); in bnx2x_set_q_rx_mode()
6184 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); in bnx2x_set_q_rx_mode()
6192 rc = bnx2x_config_rx_mode(bp, &ramrod_param); in bnx2x_set_q_rx_mode()
6194 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode); in bnx2x_set_q_rx_mode()
6201 static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode, in bnx2x_fill_accept_flags() argument
6226 if (bp->accept_any_vlan) { in bnx2x_fill_accept_flags()
6242 if (bp->accept_any_vlan) { in bnx2x_fill_accept_flags()
6262 if (IS_MF_SI(bp)) in bnx2x_fill_accept_flags()
6280 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp) in bnx2x_set_storm_rx_mode() argument
6286 if (!NO_FCOE(bp)) in bnx2x_set_storm_rx_mode()
6290 rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags, in bnx2x_set_storm_rx_mode()
6298 return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, in bnx2x_set_storm_rx_mode()
6303 static void bnx2x_init_internal_common(struct bnx2x *bp) in bnx2x_init_internal_common() argument
6310 REG_WR(bp, BAR_USTRORM_INTMEM + in bnx2x_init_internal_common()
6312 if (!CHIP_IS_E1x(bp)) { in bnx2x_init_internal_common()
6313 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET, in bnx2x_init_internal_common()
6314 CHIP_INT_MODE_IS_BC(bp) ? in bnx2x_init_internal_common()
6319 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code) in bnx2x_init_internal() argument
6324 bnx2x_init_internal_common(bp); in bnx2x_init_internal()
6344 return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp); in bnx2x_fp_igu_sb_id()
6349 return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp); in bnx2x_fp_fw_sb_id()
6354 if (CHIP_IS_E1x(fp->bp)) in bnx2x_fp_cl_id()
6355 return BP_L_ID(fp->bp) + fp->index; in bnx2x_fp_cl_id()
6360 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx) in bnx2x_init_eth_fp() argument
6362 struct bnx2x_fastpath *fp = &bp->fp[fp_idx]; in bnx2x_init_eth_fp()
6388 bnx2x_init_txdata(bp, fp->txdata_ptr[cos], in bnx2x_init_eth_fp()
6389 CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp), in bnx2x_init_eth_fp()
6390 FP_COS_TO_TXQ(fp, cos, bp), in bnx2x_init_eth_fp()
6396 if (IS_VF(bp)) in bnx2x_init_eth_fp()
6399 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false, in bnx2x_init_eth_fp()
6402 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids, in bnx2x_init_eth_fp()
6403 fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata), in bnx2x_init_eth_fp()
6404 bnx2x_sp_mapping(bp, q_rdata), q_type); in bnx2x_init_eth_fp()
6413 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, in bnx2x_init_eth_fp()
6446 static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp) in bnx2x_init_tx_rings_cnic() argument
6450 for_each_tx_queue_cnic(bp, i) in bnx2x_init_tx_rings_cnic()
6451 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]); in bnx2x_init_tx_rings_cnic()
6454 static void bnx2x_init_tx_rings(struct bnx2x *bp) in bnx2x_init_tx_rings() argument
6459 for_each_eth_queue(bp, i) in bnx2x_init_tx_rings()
6460 for_each_cos_in_tx_queue(&bp->fp[i], cos) in bnx2x_init_tx_rings()
6461 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]); in bnx2x_init_tx_rings()
6464 static void bnx2x_init_fcoe_fp(struct bnx2x *bp) in bnx2x_init_fcoe_fp() argument
6466 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); in bnx2x_init_fcoe_fp()
6469 bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp); in bnx2x_init_fcoe_fp()
6470 bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp, in bnx2x_init_fcoe_fp()
6472 bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp); in bnx2x_init_fcoe_fp()
6473 bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID; in bnx2x_init_fcoe_fp()
6474 bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id; in bnx2x_init_fcoe_fp()
6475 bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX; in bnx2x_init_fcoe_fp()
6476 bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]), in bnx2x_init_fcoe_fp()
6477 fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX, in bnx2x_init_fcoe_fp()
6483 bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp); in bnx2x_init_fcoe_fp()
6485 bnx2x_fcoe(bp, ustorm_rx_prods_offset) = in bnx2x_init_fcoe_fp()
6495 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, in bnx2x_init_fcoe_fp()
6496 &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata), in bnx2x_init_fcoe_fp()
6497 bnx2x_sp_mapping(bp, q_rdata), q_type); in bnx2x_init_fcoe_fp()
6501 fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, in bnx2x_init_fcoe_fp()
6505 void bnx2x_nic_init_cnic(struct bnx2x *bp) in bnx2x_nic_init_cnic() argument
6507 if (!NO_FCOE(bp)) in bnx2x_nic_init_cnic()
6508 bnx2x_init_fcoe_fp(bp); in bnx2x_nic_init_cnic()
6510 bnx2x_init_sb(bp, bp->cnic_sb_mapping, in bnx2x_nic_init_cnic()
6512 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp)); in bnx2x_nic_init_cnic()
6516 bnx2x_init_rx_rings_cnic(bp); in bnx2x_nic_init_cnic()
6517 bnx2x_init_tx_rings_cnic(bp); in bnx2x_nic_init_cnic()
6523 void bnx2x_pre_irq_nic_init(struct bnx2x *bp) in bnx2x_pre_irq_nic_init() argument
6528 for_each_eth_queue(bp, i) in bnx2x_pre_irq_nic_init()
6529 bnx2x_init_eth_fp(bp, i); in bnx2x_pre_irq_nic_init()
6533 bnx2x_init_rx_rings(bp); in bnx2x_pre_irq_nic_init()
6534 bnx2x_init_tx_rings(bp); in bnx2x_pre_irq_nic_init()
6536 if (IS_PF(bp)) { in bnx2x_pre_irq_nic_init()
6538 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id, in bnx2x_pre_irq_nic_init()
6539 bp->common.shmem_base, in bnx2x_pre_irq_nic_init()
6540 bp->common.shmem2_base, BP_PORT(bp)); in bnx2x_pre_irq_nic_init()
6543 bnx2x_init_def_sb(bp); in bnx2x_pre_irq_nic_init()
6544 bnx2x_update_dsb_idx(bp); in bnx2x_pre_irq_nic_init()
6545 bnx2x_init_sp_ring(bp); in bnx2x_pre_irq_nic_init()
6547 bnx2x_memset_stats(bp); in bnx2x_pre_irq_nic_init()
6551 void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code) in bnx2x_post_irq_nic_init() argument
6553 bnx2x_init_eq_ring(bp); in bnx2x_post_irq_nic_init()
6554 bnx2x_init_internal(bp, load_code); in bnx2x_post_irq_nic_init()
6555 bnx2x_pf_init(bp); in bnx2x_post_irq_nic_init()
6556 bnx2x_stats_init(bp); in bnx2x_post_irq_nic_init()
6561 bnx2x_int_enable(bp); in bnx2x_post_irq_nic_init()
6564 bnx2x_attn_int_deasserted0(bp, in bnx2x_post_irq_nic_init()
6565 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) & in bnx2x_post_irq_nic_init()
6570 static int bnx2x_gunzip_init(struct bnx2x *bp) in bnx2x_gunzip_init() argument
6572 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE, in bnx2x_gunzip_init()
6573 &bp->gunzip_mapping, GFP_KERNEL); in bnx2x_gunzip_init()
6574 if (bp->gunzip_buf == NULL) in bnx2x_gunzip_init()
6577 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL); in bnx2x_gunzip_init()
6578 if (bp->strm == NULL) in bnx2x_gunzip_init()
6581 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize()); in bnx2x_gunzip_init()
6582 if (bp->strm->workspace == NULL) in bnx2x_gunzip_init()
6588 kfree(bp->strm); in bnx2x_gunzip_init()
6589 bp->strm = NULL; in bnx2x_gunzip_init()
6592 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, in bnx2x_gunzip_init()
6593 bp->gunzip_mapping); in bnx2x_gunzip_init()
6594 bp->gunzip_buf = NULL; in bnx2x_gunzip_init()
6601 static void bnx2x_gunzip_end(struct bnx2x *bp) in bnx2x_gunzip_end() argument
6603 if (bp->strm) { in bnx2x_gunzip_end()
6604 vfree(bp->strm->workspace); in bnx2x_gunzip_end()
6605 kfree(bp->strm); in bnx2x_gunzip_end()
6606 bp->strm = NULL; in bnx2x_gunzip_end()
6609 if (bp->gunzip_buf) { in bnx2x_gunzip_end()
6610 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, in bnx2x_gunzip_end()
6611 bp->gunzip_mapping); in bnx2x_gunzip_end()
6612 bp->gunzip_buf = NULL; in bnx2x_gunzip_end()
6616 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len) in bnx2x_gunzip() argument
6633 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n; in bnx2x_gunzip()
6634 bp->strm->avail_in = len - n; in bnx2x_gunzip()
6635 bp->strm->next_out = bp->gunzip_buf; in bnx2x_gunzip()
6636 bp->strm->avail_out = FW_BUF_SIZE; in bnx2x_gunzip()
6638 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS); in bnx2x_gunzip()
6642 rc = zlib_inflate(bp->strm, Z_FINISH); in bnx2x_gunzip()
6644 netdev_err(bp->dev, "Firmware decompression error: %s\n", in bnx2x_gunzip()
6645 bp->strm->msg); in bnx2x_gunzip()
6647 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out); in bnx2x_gunzip()
6648 if (bp->gunzip_outlen & 0x3) in bnx2x_gunzip()
6649 netdev_err(bp->dev, in bnx2x_gunzip()
6651 bp->gunzip_outlen); in bnx2x_gunzip()
6652 bp->gunzip_outlen >>= 2; in bnx2x_gunzip()
6654 zlib_inflateEnd(bp->strm); in bnx2x_gunzip()
6669 static void bnx2x_lb_pckt(struct bnx2x *bp) in bnx2x_lb_pckt() argument
6677 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); in bnx2x_lb_pckt()
6683 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); in bnx2x_lb_pckt()
6690 static int bnx2x_int_mem_test(struct bnx2x *bp) in bnx2x_int_mem_test() argument
6696 if (CHIP_REV_IS_FPGA(bp)) in bnx2x_int_mem_test()
6698 else if (CHIP_REV_IS_EMUL(bp)) in bnx2x_int_mem_test()
6704 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); in bnx2x_int_mem_test()
6705 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); in bnx2x_int_mem_test()
6706 REG_WR(bp, CFC_REG_DEBUG0, 0x1); in bnx2x_int_mem_test()
6707 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); in bnx2x_int_mem_test()
6710 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); in bnx2x_int_mem_test()
6713 bnx2x_lb_pckt(bp); in bnx2x_int_mem_test()
6720 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); in bnx2x_int_mem_test()
6721 val = *bnx2x_sp(bp, wb_data[0]); in bnx2x_int_mem_test()
6736 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); in bnx2x_int_mem_test()
6749 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); in bnx2x_int_mem_test()
6751 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); in bnx2x_int_mem_test()
6753 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); in bnx2x_int_mem_test()
6754 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); in bnx2x_int_mem_test()
6759 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); in bnx2x_int_mem_test()
6760 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); in bnx2x_int_mem_test()
6761 REG_WR(bp, CFC_REG_DEBUG0, 0x1); in bnx2x_int_mem_test()
6762 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); in bnx2x_int_mem_test()
6765 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); in bnx2x_int_mem_test()
6769 bnx2x_lb_pckt(bp); in bnx2x_int_mem_test()
6776 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); in bnx2x_int_mem_test()
6777 val = *bnx2x_sp(bp, wb_data[0]); in bnx2x_int_mem_test()
6790 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); in bnx2x_int_mem_test()
6795 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1); in bnx2x_int_mem_test()
6800 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); in bnx2x_int_mem_test()
6806 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO); in bnx2x_int_mem_test()
6807 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY); in bnx2x_int_mem_test()
6814 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); in bnx2x_int_mem_test()
6816 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); in bnx2x_int_mem_test()
6818 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); in bnx2x_int_mem_test()
6819 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); in bnx2x_int_mem_test()
6820 if (!CNIC_SUPPORT(bp)) in bnx2x_int_mem_test()
6822 REG_WR(bp, PRS_REG_NIC_MODE, 1); in bnx2x_int_mem_test()
6825 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff); in bnx2x_int_mem_test()
6826 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1); in bnx2x_int_mem_test()
6827 REG_WR(bp, CFC_REG_DEBUG0, 0x0); in bnx2x_int_mem_test()
6828 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1); in bnx2x_int_mem_test()
6835 static void bnx2x_enable_blocks_attention(struct bnx2x *bp) in bnx2x_enable_blocks_attention() argument
6839 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); in bnx2x_enable_blocks_attention()
6840 if (!CHIP_IS_E1x(bp)) in bnx2x_enable_blocks_attention()
6841 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40); in bnx2x_enable_blocks_attention()
6843 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0); in bnx2x_enable_blocks_attention()
6844 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6845 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6852 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00); in bnx2x_enable_blocks_attention()
6853 REG_WR(bp, QM_REG_QM_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6854 REG_WR(bp, TM_REG_TM_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6855 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0); in bnx2x_enable_blocks_attention()
6856 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0); in bnx2x_enable_blocks_attention()
6857 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6860 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0); in bnx2x_enable_blocks_attention()
6861 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0); in bnx2x_enable_blocks_attention()
6862 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6865 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6866 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0); in bnx2x_enable_blocks_attention()
6867 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0); in bnx2x_enable_blocks_attention()
6868 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6875 if (!CHIP_IS_E1x(bp)) in bnx2x_enable_blocks_attention()
6878 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val); in bnx2x_enable_blocks_attention()
6880 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0); in bnx2x_enable_blocks_attention()
6881 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0); in bnx2x_enable_blocks_attention()
6882 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6885 if (!CHIP_IS_E1x(bp)) in bnx2x_enable_blocks_attention()
6887 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff); in bnx2x_enable_blocks_attention()
6889 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6890 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6892 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */ in bnx2x_enable_blocks_attention()
6895 static void bnx2x_reset_common(struct bnx2x *bp) in bnx2x_reset_common() argument
6900 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, in bnx2x_reset_common()
6903 if (CHIP_IS_E3(bp)) { in bnx2x_reset_common()
6908 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val); in bnx2x_reset_common()
6911 static void bnx2x_setup_dmae(struct bnx2x *bp) in bnx2x_setup_dmae() argument
6913 bp->dmae_ready = 0; in bnx2x_setup_dmae()
6914 spin_lock_init(&bp->dmae_lock); in bnx2x_setup_dmae()
6917 static void bnx2x_init_pxp(struct bnx2x *bp) in bnx2x_init_pxp() argument
6922 pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl); in bnx2x_init_pxp()
6925 if (bp->mrrs == -1) in bnx2x_init_pxp()
6928 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs); in bnx2x_init_pxp()
6929 r_order = bp->mrrs; in bnx2x_init_pxp()
6932 bnx2x_init_pxp_arb(bp, r_order, w_order); in bnx2x_init_pxp()
6935 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp) in bnx2x_setup_fan_failure_detection() argument
6941 if (BP_NOMCP(bp)) in bnx2x_setup_fan_failure_detection()
6945 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) & in bnx2x_setup_fan_failure_detection()
6960 bp, in bnx2x_setup_fan_failure_detection()
6961 bp->common.shmem_base, in bnx2x_setup_fan_failure_detection()
6962 bp->common.shmem2_base, in bnx2x_setup_fan_failure_detection()
6972 bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z); in bnx2x_setup_fan_failure_detection()
6975 val = REG_RD(bp, MISC_REG_SPIO_INT); in bnx2x_setup_fan_failure_detection()
6977 REG_WR(bp, MISC_REG_SPIO_INT, val); in bnx2x_setup_fan_failure_detection()
6980 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); in bnx2x_setup_fan_failure_detection()
6982 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val); in bnx2x_setup_fan_failure_detection()
6985 void bnx2x_pf_disable(struct bnx2x *bp) in bnx2x_pf_disable() argument
6987 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); in bnx2x_pf_disable()
6990 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); in bnx2x_pf_disable()
6991 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); in bnx2x_pf_disable()
6992 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0); in bnx2x_pf_disable()
6995 static void bnx2x__common_init_phy(struct bnx2x *bp) in bnx2x__common_init_phy() argument
6999 if (SHMEM2_RD(bp, size) > in bnx2x__common_init_phy()
7000 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)])) in bnx2x__common_init_phy()
7002 shmem_base[0] = bp->common.shmem_base; in bnx2x__common_init_phy()
7003 shmem2_base[0] = bp->common.shmem2_base; in bnx2x__common_init_phy()
7004 if (!CHIP_IS_E1x(bp)) { in bnx2x__common_init_phy()
7006 SHMEM2_RD(bp, other_shmem_base_addr); in bnx2x__common_init_phy()
7008 SHMEM2_RD(bp, other_shmem2_base_addr); in bnx2x__common_init_phy()
7010 bnx2x_acquire_phy_lock(bp); in bnx2x__common_init_phy()
7011 bnx2x_common_init_phy(bp, shmem_base, shmem2_base, in bnx2x__common_init_phy()
7012 bp->common.chip_id); in bnx2x__common_init_phy()
7013 bnx2x_release_phy_lock(bp); in bnx2x__common_init_phy()
7016 static void bnx2x_config_endianity(struct bnx2x *bp, u32 val) in bnx2x_config_endianity() argument
7018 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, val); in bnx2x_config_endianity()
7019 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, val); in bnx2x_config_endianity()
7020 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, val); in bnx2x_config_endianity()
7021 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, val); in bnx2x_config_endianity()
7022 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, val); in bnx2x_config_endianity()
7025 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0); in bnx2x_config_endianity()
7027 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, val); in bnx2x_config_endianity()
7028 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, val); in bnx2x_config_endianity()
7029 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, val); in bnx2x_config_endianity()
7030 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, val); in bnx2x_config_endianity()
7033 static void bnx2x_set_endianity(struct bnx2x *bp) in bnx2x_set_endianity() argument
7036 bnx2x_config_endianity(bp, 1); in bnx2x_set_endianity()
7038 bnx2x_config_endianity(bp, 0); in bnx2x_set_endianity()
7042 static void bnx2x_reset_endianity(struct bnx2x *bp) in bnx2x_reset_endianity() argument
7044 bnx2x_config_endianity(bp, 0); in bnx2x_reset_endianity()
7052 static int bnx2x_init_hw_common(struct bnx2x *bp) in bnx2x_init_hw_common() argument
7056 DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp)); in bnx2x_init_hw_common()
7062 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); in bnx2x_init_hw_common()
7064 bnx2x_reset_common(bp); in bnx2x_init_hw_common()
7065 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff); in bnx2x_init_hw_common()
7068 if (CHIP_IS_E3(bp)) { in bnx2x_init_hw_common()
7072 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val); in bnx2x_init_hw_common()
7074 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); in bnx2x_init_hw_common()
7076 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON); in bnx2x_init_hw_common()
7078 if (!CHIP_IS_E1x(bp)) { in bnx2x_init_hw_common()
7088 for (abs_func_id = BP_PATH(bp); in bnx2x_init_hw_common()
7090 if (abs_func_id == BP_ABS_FUNC(bp)) { in bnx2x_init_hw_common()
7091 REG_WR(bp, in bnx2x_init_hw_common()
7097 bnx2x_pretend_func(bp, abs_func_id); in bnx2x_init_hw_common()
7099 bnx2x_pf_disable(bp); in bnx2x_init_hw_common()
7100 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); in bnx2x_init_hw_common()
7104 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON); in bnx2x_init_hw_common()
7105 if (CHIP_IS_E1(bp)) { in bnx2x_init_hw_common()
7108 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); in bnx2x_init_hw_common()
7111 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON); in bnx2x_init_hw_common()
7112 bnx2x_init_pxp(bp); in bnx2x_init_hw_common()
7113 bnx2x_set_endianity(bp); in bnx2x_init_hw_common()
7114 bnx2x_ilt_init_page_size(bp, INITOP_SET); in bnx2x_init_hw_common()
7116 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp)) in bnx2x_init_hw_common()
7117 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1); in bnx2x_init_hw_common()
7122 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE); in bnx2x_init_hw_common()
7127 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE); in bnx2x_init_hw_common()
7138 if (!CHIP_IS_E1x(bp)) { in bnx2x_init_hw_common()
7222 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6)); in bnx2x_init_hw_common()
7223 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR); in bnx2x_init_hw_common()
7224 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); in bnx2x_init_hw_common()
7226 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN); in bnx2x_init_hw_common()
7227 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN); in bnx2x_init_hw_common()
7228 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1); in bnx2x_init_hw_common()
7231 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0); in bnx2x_init_hw_common()
7232 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0); in bnx2x_init_hw_common()
7234 if (!CHIP_IS_E1x(bp)) { in bnx2x_init_hw_common()
7235 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 : in bnx2x_init_hw_common()
7236 (CHIP_REV_IS_FPGA(bp) ? 400 : 0); in bnx2x_init_hw_common()
7237 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON); in bnx2x_init_hw_common()
7239 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON); in bnx2x_init_hw_common()
7244 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE); in bnx2x_init_hw_common()
7253 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON); in bnx2x_init_hw_common()
7255 bnx2x_iov_init_dmae(bp); in bnx2x_init_hw_common()
7258 bp->dmae_ready = 1; in bnx2x_init_hw_common()
7259 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1); in bnx2x_init_hw_common()
7261 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON); in bnx2x_init_hw_common()
7263 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON); in bnx2x_init_hw_common()
7265 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON); in bnx2x_init_hw_common()
7267 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON); in bnx2x_init_hw_common()
7269 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3); in bnx2x_init_hw_common()
7270 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3); in bnx2x_init_hw_common()
7271 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3); in bnx2x_init_hw_common()
7272 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3); in bnx2x_init_hw_common()
7274 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON); in bnx2x_init_hw_common()
7277 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET); in bnx2x_init_hw_common()
7280 REG_WR(bp, QM_REG_SOFT_RESET, 1); in bnx2x_init_hw_common()
7281 REG_WR(bp, QM_REG_SOFT_RESET, 0); in bnx2x_init_hw_common()
7283 if (CNIC_SUPPORT(bp)) in bnx2x_init_hw_common()
7284 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON); in bnx2x_init_hw_common()
7286 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON); in bnx2x_init_hw_common()
7288 if (!CHIP_REV_IS_SLOW(bp)) in bnx2x_init_hw_common()
7290 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); in bnx2x_init_hw_common()
7292 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); in bnx2x_init_hw_common()
7294 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); in bnx2x_init_hw_common()
7295 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf); in bnx2x_init_hw_common()
7297 if (!CHIP_IS_E1(bp)) in bnx2x_init_hw_common()
7298 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan); in bnx2x_init_hw_common()
7300 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) { in bnx2x_init_hw_common()
7301 if (IS_MF_AFEX(bp)) { in bnx2x_init_hw_common()
7305 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE); in bnx2x_init_hw_common()
7306 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA); in bnx2x_init_hw_common()
7307 REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6); in bnx2x_init_hw_common()
7308 REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926); in bnx2x_init_hw_common()
7309 REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4); in bnx2x_init_hw_common()
7314 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, in bnx2x_init_hw_common()
7315 bp->path_has_ovlan ? 7 : 6); in bnx2x_init_hw_common()
7319 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON); in bnx2x_init_hw_common()
7320 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON); in bnx2x_init_hw_common()
7321 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON); in bnx2x_init_hw_common()
7322 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON); in bnx2x_init_hw_common()
7324 if (!CHIP_IS_E1x(bp)) { in bnx2x_init_hw_common()
7326 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, in bnx2x_init_hw_common()
7329 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, in bnx2x_init_hw_common()
7336 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON); in bnx2x_init_hw_common()
7337 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON); in bnx2x_init_hw_common()
7338 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON); in bnx2x_init_hw_common()
7339 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON); in bnx2x_init_hw_common()
7342 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, in bnx2x_init_hw_common()
7344 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, in bnx2x_init_hw_common()
7347 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON); in bnx2x_init_hw_common()
7348 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON); in bnx2x_init_hw_common()
7349 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON); in bnx2x_init_hw_common()
7351 if (!CHIP_IS_E1x(bp)) { in bnx2x_init_hw_common()
7352 if (IS_MF_AFEX(bp)) { in bnx2x_init_hw_common()
7356 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE); in bnx2x_init_hw_common()
7357 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA); in bnx2x_init_hw_common()
7358 REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6); in bnx2x_init_hw_common()
7359 REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926); in bnx2x_init_hw_common()
7360 REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4); in bnx2x_init_hw_common()
7362 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, in bnx2x_init_hw_common()
7363 bp->path_has_ovlan ? 7 : 6); in bnx2x_init_hw_common()
7367 REG_WR(bp, SRC_REG_SOFT_RST, 1); in bnx2x_init_hw_common()
7369 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON); in bnx2x_init_hw_common()
7371 if (CNIC_SUPPORT(bp)) { in bnx2x_init_hw_common()
7372 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672); in bnx2x_init_hw_common()
7373 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc); in bnx2x_init_hw_common()
7374 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b); in bnx2x_init_hw_common()
7375 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a); in bnx2x_init_hw_common()
7376 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116); in bnx2x_init_hw_common()
7377 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b); in bnx2x_init_hw_common()
7378 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf); in bnx2x_init_hw_common()
7379 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09); in bnx2x_init_hw_common()
7380 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f); in bnx2x_init_hw_common()
7381 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7); in bnx2x_init_hw_common()
7383 REG_WR(bp, SRC_REG_SOFT_RST, 0); in bnx2x_init_hw_common()
7387 dev_alert(&bp->pdev->dev, in bnx2x_init_hw_common()
7391 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON); in bnx2x_init_hw_common()
7393 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val); in bnx2x_init_hw_common()
7395 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON); in bnx2x_init_hw_common()
7396 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF); in bnx2x_init_hw_common()
7398 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); in bnx2x_init_hw_common()
7401 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000); in bnx2x_init_hw_common()
7403 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON); in bnx2x_init_hw_common()
7405 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp)) in bnx2x_init_hw_common()
7406 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36); in bnx2x_init_hw_common()
7408 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON); in bnx2x_init_hw_common()
7409 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON); in bnx2x_init_hw_common()
7412 REG_WR(bp, 0x2814, 0xffffffff); in bnx2x_init_hw_common()
7413 REG_WR(bp, 0x3820, 0xffffffff); in bnx2x_init_hw_common()
7415 if (!CHIP_IS_E1x(bp)) { in bnx2x_init_hw_common()
7416 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5, in bnx2x_init_hw_common()
7419 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT, in bnx2x_init_hw_common()
7423 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT, in bnx2x_init_hw_common()
7429 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON); in bnx2x_init_hw_common()
7430 if (!CHIP_IS_E1(bp)) { in bnx2x_init_hw_common()
7432 if (!CHIP_IS_E3(bp)) in bnx2x_init_hw_common()
7433 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp)); in bnx2x_init_hw_common()
7435 if (CHIP_IS_E1H(bp)) in bnx2x_init_hw_common()
7437 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp)); in bnx2x_init_hw_common()
7439 if (CHIP_REV_IS_SLOW(bp)) in bnx2x_init_hw_common()
7443 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10); in bnx2x_init_hw_common()
7448 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10); in bnx2x_init_hw_common()
7453 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10); in bnx2x_init_hw_common()
7458 REG_WR(bp, CFC_REG_DEBUG0, 0); in bnx2x_init_hw_common()
7460 if (CHIP_IS_E1(bp)) { in bnx2x_init_hw_common()
7463 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); in bnx2x_init_hw_common()
7464 val = *bnx2x_sp(bp, wb_data[0]); in bnx2x_init_hw_common()
7467 if ((val == 0) && bnx2x_int_mem_test(bp)) { in bnx2x_init_hw_common()
7473 bnx2x_setup_fan_failure_detection(bp); in bnx2x_init_hw_common()
7476 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0); in bnx2x_init_hw_common()
7478 bnx2x_enable_blocks_attention(bp); in bnx2x_init_hw_common()
7479 bnx2x_enable_blocks_parity(bp); in bnx2x_init_hw_common()
7481 if (!BP_NOMCP(bp)) { in bnx2x_init_hw_common()
7482 if (CHIP_IS_E1x(bp)) in bnx2x_init_hw_common()
7483 bnx2x__common_init_phy(bp); in bnx2x_init_hw_common()
7487 if (SHMEM2_HAS(bp, netproc_fw_ver)) in bnx2x_init_hw_common()
7488 SHMEM2_WR(bp, netproc_fw_ver, REG_RD(bp, XSEM_REG_PRAM)); in bnx2x_init_hw_common()
7498 static int bnx2x_init_hw_common_chip(struct bnx2x *bp) in bnx2x_init_hw_common_chip() argument
7500 int rc = bnx2x_init_hw_common(bp); in bnx2x_init_hw_common_chip()
7506 if (!BP_NOMCP(bp)) in bnx2x_init_hw_common_chip()
7507 bnx2x__common_init_phy(bp); in bnx2x_init_hw_common_chip()
7512 static int bnx2x_init_hw_port(struct bnx2x *bp) in bnx2x_init_hw_port() argument
7514 int port = BP_PORT(bp); in bnx2x_init_hw_port()
7521 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); in bnx2x_init_hw_port()
7523 bnx2x_init_block(bp, BLOCK_MISC, init_phase); in bnx2x_init_hw_port()
7524 bnx2x_init_block(bp, BLOCK_PXP, init_phase); in bnx2x_init_hw_port()
7525 bnx2x_init_block(bp, BLOCK_PXP2, init_phase); in bnx2x_init_hw_port()
7532 if (!CHIP_IS_E1x(bp)) in bnx2x_init_hw_port()
7533 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); in bnx2x_init_hw_port()
7535 bnx2x_init_block(bp, BLOCK_ATC, init_phase); in bnx2x_init_hw_port()
7536 bnx2x_init_block(bp, BLOCK_DMAE, init_phase); in bnx2x_init_hw_port()
7537 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); in bnx2x_init_hw_port()
7538 bnx2x_init_block(bp, BLOCK_QM, init_phase); in bnx2x_init_hw_port()
7540 bnx2x_init_block(bp, BLOCK_TCM, init_phase); in bnx2x_init_hw_port()
7541 bnx2x_init_block(bp, BLOCK_UCM, init_phase); in bnx2x_init_hw_port()
7542 bnx2x_init_block(bp, BLOCK_CCM, init_phase); in bnx2x_init_hw_port()
7543 bnx2x_init_block(bp, BLOCK_XCM, init_phase); in bnx2x_init_hw_port()
7546 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET); in bnx2x_init_hw_port()
7548 if (CNIC_SUPPORT(bp)) { in bnx2x_init_hw_port()
7549 bnx2x_init_block(bp, BLOCK_TM, init_phase); in bnx2x_init_hw_port()
7550 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20); in bnx2x_init_hw_port()
7551 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31); in bnx2x_init_hw_port()
7554 bnx2x_init_block(bp, BLOCK_DORQ, init_phase); in bnx2x_init_hw_port()
7556 bnx2x_init_block(bp, BLOCK_BRB1, init_phase); in bnx2x_init_hw_port()
7558 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) { in bnx2x_init_hw_port()
7560 if (IS_MF(bp)) in bnx2x_init_hw_port()
7561 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246); in bnx2x_init_hw_port()
7562 else if (bp->dev->mtu > 4096) { in bnx2x_init_hw_port()
7563 if (bp->flags & ONE_PORT_FLAG) in bnx2x_init_hw_port()
7566 val = bp->dev->mtu; in bnx2x_init_hw_port()
7572 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160); in bnx2x_init_hw_port()
7574 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low); in bnx2x_init_hw_port()
7575 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high); in bnx2x_init_hw_port()
7578 if (CHIP_MODE_IS_4_PORT(bp)) in bnx2x_init_hw_port()
7579 REG_WR(bp, (BP_PORT(bp) ? in bnx2x_init_hw_port()
7583 bnx2x_init_block(bp, BLOCK_PRS, init_phase); in bnx2x_init_hw_port()
7584 if (CHIP_IS_E3B0(bp)) { in bnx2x_init_hw_port()
7585 if (IS_MF_AFEX(bp)) { in bnx2x_init_hw_port()
7587 REG_WR(bp, BP_PORT(bp) ? in bnx2x_init_hw_port()
7590 REG_WR(bp, BP_PORT(bp) ? in bnx2x_init_hw_port()
7593 REG_WR(bp, BP_PORT(bp) ? in bnx2x_init_hw_port()
7601 REG_WR(bp, BP_PORT(bp) ? in bnx2x_init_hw_port()
7604 (bp->path_has_ovlan ? 7 : 6)); in bnx2x_init_hw_port()
7608 bnx2x_init_block(bp, BLOCK_TSDM, init_phase); in bnx2x_init_hw_port()
7609 bnx2x_init_block(bp, BLOCK_CSDM, init_phase); in bnx2x_init_hw_port()
7610 bnx2x_init_block(bp, BLOCK_USDM, init_phase); in bnx2x_init_hw_port()
7611 bnx2x_init_block(bp, BLOCK_XSDM, init_phase); in bnx2x_init_hw_port()
7613 bnx2x_init_block(bp, BLOCK_TSEM, init_phase); in bnx2x_init_hw_port()
7614 bnx2x_init_block(bp, BLOCK_USEM, init_phase); in bnx2x_init_hw_port()
7615 bnx2x_init_block(bp, BLOCK_CSEM, init_phase); in bnx2x_init_hw_port()
7616 bnx2x_init_block(bp, BLOCK_XSEM, init_phase); in bnx2x_init_hw_port()
7618 bnx2x_init_block(bp, BLOCK_UPB, init_phase); in bnx2x_init_hw_port()
7619 bnx2x_init_block(bp, BLOCK_XPB, init_phase); in bnx2x_init_hw_port()
7621 bnx2x_init_block(bp, BLOCK_PBF, init_phase); in bnx2x_init_hw_port()
7623 if (CHIP_IS_E1x(bp)) { in bnx2x_init_hw_port()
7625 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); in bnx2x_init_hw_port()
7628 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16)); in bnx2x_init_hw_port()
7630 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22); in bnx2x_init_hw_port()
7633 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1); in bnx2x_init_hw_port()
7635 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0); in bnx2x_init_hw_port()
7638 if (CNIC_SUPPORT(bp)) in bnx2x_init_hw_port()
7639 bnx2x_init_block(bp, BLOCK_SRC, init_phase); in bnx2x_init_hw_port()
7641 bnx2x_init_block(bp, BLOCK_CDU, init_phase); in bnx2x_init_hw_port()
7642 bnx2x_init_block(bp, BLOCK_CFC, init_phase); in bnx2x_init_hw_port()
7644 if (CHIP_IS_E1(bp)) { in bnx2x_init_hw_port()
7645 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); in bnx2x_init_hw_port()
7646 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); in bnx2x_init_hw_port()
7648 bnx2x_init_block(bp, BLOCK_HC, init_phase); in bnx2x_init_hw_port()
7650 bnx2x_init_block(bp, BLOCK_IGU, init_phase); in bnx2x_init_hw_port()
7652 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); in bnx2x_init_hw_port()
7657 val = IS_MF(bp) ? 0xF7 : 0x7; in bnx2x_init_hw_port()
7659 val |= CHIP_IS_E1(bp) ? 0 : 0x10; in bnx2x_init_hw_port()
7660 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val); in bnx2x_init_hw_port()
7664 REG_WR(bp, reg, in bnx2x_init_hw_port()
7665 REG_RD(bp, reg) & in bnx2x_init_hw_port()
7669 REG_WR(bp, reg, in bnx2x_init_hw_port()
7670 REG_RD(bp, reg) & in bnx2x_init_hw_port()
7673 bnx2x_init_block(bp, BLOCK_NIG, init_phase); in bnx2x_init_hw_port()
7675 if (!CHIP_IS_E1x(bp)) { in bnx2x_init_hw_port()
7679 if (IS_MF_AFEX(bp)) in bnx2x_init_hw_port()
7680 REG_WR(bp, BP_PORT(bp) ? in bnx2x_init_hw_port()
7684 REG_WR(bp, BP_PORT(bp) ? in bnx2x_init_hw_port()
7687 IS_MF_SD(bp) ? 7 : 6); in bnx2x_init_hw_port()
7689 if (CHIP_IS_E3(bp)) in bnx2x_init_hw_port()
7690 REG_WR(bp, BP_PORT(bp) ? in bnx2x_init_hw_port()
7692 NIG_REG_LLH_MF_MODE, IS_MF(bp)); in bnx2x_init_hw_port()
7694 if (!CHIP_IS_E3(bp)) in bnx2x_init_hw_port()
7695 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); in bnx2x_init_hw_port()
7697 if (!CHIP_IS_E1(bp)) { in bnx2x_init_hw_port()
7699 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4, in bnx2x_init_hw_port()
7700 (IS_MF_SD(bp) ? 0x1 : 0x2)); in bnx2x_init_hw_port()
7702 if (!CHIP_IS_E1x(bp)) { in bnx2x_init_hw_port()
7704 switch (bp->mf_mode) { in bnx2x_init_hw_port()
7714 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE : in bnx2x_init_hw_port()
7718 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0); in bnx2x_init_hw_port()
7719 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0); in bnx2x_init_hw_port()
7720 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1); in bnx2x_init_hw_port()
7725 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); in bnx2x_init_hw_port()
7729 val = REG_RD(bp, reg_addr); in bnx2x_init_hw_port()
7731 REG_WR(bp, reg_addr, val); in bnx2x_init_hw_port()
7734 if (CHIP_IS_E3B0(bp)) in bnx2x_init_hw_port()
7735 bp->flags |= PTP_SUPPORTED; in bnx2x_init_hw_port()
7740 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr) in bnx2x_ilt_wr() argument
7745 if (CHIP_IS_E1(bp)) in bnx2x_ilt_wr()
7752 REG_WR_DMAE(bp, reg, wb_write, 2); in bnx2x_ilt_wr()
7755 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf) in bnx2x_igu_clear_sb_gen() argument
7766 if (CHIP_INT_MODE_IS_BC(bp)) in bnx2x_igu_clear_sb_gen()
7780 REG_WR(bp, igu_addr_data, data); in bnx2x_igu_clear_sb_gen()
7784 REG_WR(bp, igu_addr_ctl, ctl); in bnx2x_igu_clear_sb_gen()
7788 while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt) in bnx2x_igu_clear_sb_gen()
7791 if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) { in bnx2x_igu_clear_sb_gen()
7798 static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id) in bnx2x_igu_clear_sb() argument
7800 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/); in bnx2x_igu_clear_sb()
7803 static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func) in bnx2x_clear_func_ilt() argument
7807 bnx2x_ilt_wr(bp, i, 0); in bnx2x_clear_func_ilt()
7810 static void bnx2x_init_searcher(struct bnx2x *bp) in bnx2x_init_searcher() argument
7812 int port = BP_PORT(bp); in bnx2x_init_searcher()
7813 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM); in bnx2x_init_searcher()
7815 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS); in bnx2x_init_searcher()
7818 static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend) in bnx2x_func_switch_update() argument
7829 func_params.f_obj = &bp->func_obj; in bnx2x_func_switch_update()
7839 rc = bnx2x_func_state_change(bp, &func_params); in bnx2x_func_switch_update()
7844 static int bnx2x_reset_nic_mode(struct bnx2x *bp) in bnx2x_reset_nic_mode() argument
7846 int rc, i, port = BP_PORT(bp); in bnx2x_reset_nic_mode()
7850 if (bp->mf_mode == SINGLE_FUNCTION) { in bnx2x_reset_nic_mode()
7851 bnx2x_set_rx_filter(&bp->link_params, 0); in bnx2x_reset_nic_mode()
7853 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN : in bnx2x_reset_nic_mode()
7855 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN : in bnx2x_reset_nic_mode()
7858 mac_en[i] = REG_RD(bp, port ? in bnx2x_reset_nic_mode()
7863 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE + in bnx2x_reset_nic_mode()
7870 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE : in bnx2x_reset_nic_mode()
7878 rc = bnx2x_func_switch_update(bp, 1); in bnx2x_reset_nic_mode()
7885 REG_WR(bp, PRS_REG_NIC_MODE, 0); in bnx2x_reset_nic_mode()
7888 if (bp->mf_mode == SINGLE_FUNCTION) { in bnx2x_reset_nic_mode()
7889 bnx2x_set_rx_filter(&bp->link_params, 1); in bnx2x_reset_nic_mode()
7891 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN : in bnx2x_reset_nic_mode()
7894 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE + in bnx2x_reset_nic_mode()
7902 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE : in bnx2x_reset_nic_mode()
7906 rc = bnx2x_func_switch_update(bp, 0); in bnx2x_reset_nic_mode()
7916 int bnx2x_init_hw_func_cnic(struct bnx2x *bp) in bnx2x_init_hw_func_cnic() argument
7920 bnx2x_ilt_init_op_cnic(bp, INITOP_SET); in bnx2x_init_hw_func_cnic()
7922 if (CONFIGURE_NIC_MODE(bp)) { in bnx2x_init_hw_func_cnic()
7924 bnx2x_init_searcher(bp); in bnx2x_init_hw_func_cnic()
7927 rc = bnx2x_reset_nic_mode(bp); in bnx2x_init_hw_func_cnic()
7943 static void bnx2x_clean_pglue_errors(struct bnx2x *bp) in bnx2x_clean_pglue_errors() argument
7945 if (!CHIP_IS_E1x(bp)) in bnx2x_clean_pglue_errors()
7946 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, in bnx2x_clean_pglue_errors()
7947 1 << BP_ABS_FUNC(bp)); in bnx2x_clean_pglue_errors()
7950 static int bnx2x_init_hw_func(struct bnx2x *bp) in bnx2x_init_hw_func() argument
7952 int port = BP_PORT(bp); in bnx2x_init_hw_func()
7953 int func = BP_FUNC(bp); in bnx2x_init_hw_func()
7955 struct bnx2x_ilt *ilt = BP_ILT(bp); in bnx2x_init_hw_func()
7964 if (!CHIP_IS_E1x(bp)) { in bnx2x_init_hw_func()
7965 rc = bnx2x_pf_flr_clnup(bp); in bnx2x_init_hw_func()
7967 bnx2x_fw_dump(bp); in bnx2x_init_hw_func()
7973 if (bp->common.int_block == INT_BLOCK_HC) { in bnx2x_init_hw_func()
7975 val = REG_RD(bp, addr); in bnx2x_init_hw_func()
7977 REG_WR(bp, addr, val); in bnx2x_init_hw_func()
7980 bnx2x_init_block(bp, BLOCK_PXP, init_phase); in bnx2x_init_hw_func()
7981 bnx2x_init_block(bp, BLOCK_PXP2, init_phase); in bnx2x_init_hw_func()
7983 ilt = BP_ILT(bp); in bnx2x_init_hw_func()
7986 if (IS_SRIOV(bp)) in bnx2x_init_hw_func()
7988 cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start); in bnx2x_init_hw_func()
7994 for (i = 0; i < L2_ILT_LINES(bp); i++) { in bnx2x_init_hw_func()
7995 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt; in bnx2x_init_hw_func()
7997 bp->context[i].cxt_mapping; in bnx2x_init_hw_func()
7998 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size; in bnx2x_init_hw_func()
8001 bnx2x_ilt_init_op(bp, INITOP_SET); in bnx2x_init_hw_func()
8003 if (!CONFIGURE_NIC_MODE(bp)) { in bnx2x_init_hw_func()
8004 bnx2x_init_searcher(bp); in bnx2x_init_hw_func()
8005 REG_WR(bp, PRS_REG_NIC_MODE, 0); in bnx2x_init_hw_func()
8009 REG_WR(bp, PRS_REG_NIC_MODE, 1); in bnx2x_init_hw_func()
8013 if (!CHIP_IS_E1x(bp)) { in bnx2x_init_hw_func()
8019 if (!(bp->flags & USING_MSIX_FLAG)) in bnx2x_init_hw_func()
8033 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); in bnx2x_init_hw_func()
8035 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf); in bnx2x_init_hw_func()
8038 bp->dmae_ready = 1; in bnx2x_init_hw_func()
8040 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); in bnx2x_init_hw_func()
8042 bnx2x_clean_pglue_errors(bp); in bnx2x_init_hw_func()
8044 bnx2x_init_block(bp, BLOCK_ATC, init_phase); in bnx2x_init_hw_func()
8045 bnx2x_init_block(bp, BLOCK_DMAE, init_phase); in bnx2x_init_hw_func()
8046 bnx2x_init_block(bp, BLOCK_NIG, init_phase); in bnx2x_init_hw_func()
8047 bnx2x_init_block(bp, BLOCK_SRC, init_phase); in bnx2x_init_hw_func()
8048 bnx2x_init_block(bp, BLOCK_MISC, init_phase); in bnx2x_init_hw_func()
8049 bnx2x_init_block(bp, BLOCK_TCM, init_phase); in bnx2x_init_hw_func()
8050 bnx2x_init_block(bp, BLOCK_UCM, init_phase); in bnx2x_init_hw_func()
8051 bnx2x_init_block(bp, BLOCK_CCM, init_phase); in bnx2x_init_hw_func()
8052 bnx2x_init_block(bp, BLOCK_XCM, init_phase); in bnx2x_init_hw_func()
8053 bnx2x_init_block(bp, BLOCK_TSEM, init_phase); in bnx2x_init_hw_func()
8054 bnx2x_init_block(bp, BLOCK_USEM, init_phase); in bnx2x_init_hw_func()
8055 bnx2x_init_block(bp, BLOCK_CSEM, init_phase); in bnx2x_init_hw_func()
8056 bnx2x_init_block(bp, BLOCK_XSEM, init_phase); in bnx2x_init_hw_func()
8058 if (!CHIP_IS_E1x(bp)) in bnx2x_init_hw_func()
8059 REG_WR(bp, QM_REG_PF_EN, 1); in bnx2x_init_hw_func()
8061 if (!CHIP_IS_E1x(bp)) { in bnx2x_init_hw_func()
8062 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); in bnx2x_init_hw_func()
8063 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); in bnx2x_init_hw_func()
8064 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); in bnx2x_init_hw_func()
8065 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); in bnx2x_init_hw_func()
8067 bnx2x_init_block(bp, BLOCK_QM, init_phase); in bnx2x_init_hw_func()
8069 bnx2x_init_block(bp, BLOCK_TM, init_phase); in bnx2x_init_hw_func()
8070 bnx2x_init_block(bp, BLOCK_DORQ, init_phase); in bnx2x_init_hw_func()
8071 REG_WR(bp, DORQ_REG_MODE_ACT, 1); /* no dpm */ in bnx2x_init_hw_func()
8073 bnx2x_iov_init_dq(bp); in bnx2x_init_hw_func()
8075 bnx2x_init_block(bp, BLOCK_BRB1, init_phase); in bnx2x_init_hw_func()
8076 bnx2x_init_block(bp, BLOCK_PRS, init_phase); in bnx2x_init_hw_func()
8077 bnx2x_init_block(bp, BLOCK_TSDM, init_phase); in bnx2x_init_hw_func()
8078 bnx2x_init_block(bp, BLOCK_CSDM, init_phase); in bnx2x_init_hw_func()
8079 bnx2x_init_block(bp, BLOCK_USDM, init_phase); in bnx2x_init_hw_func()
8080 bnx2x_init_block(bp, BLOCK_XSDM, init_phase); in bnx2x_init_hw_func()
8081 bnx2x_init_block(bp, BLOCK_UPB, init_phase); in bnx2x_init_hw_func()
8082 bnx2x_init_block(bp, BLOCK_XPB, init_phase); in bnx2x_init_hw_func()
8083 bnx2x_init_block(bp, BLOCK_PBF, init_phase); in bnx2x_init_hw_func()
8084 if (!CHIP_IS_E1x(bp)) in bnx2x_init_hw_func()
8085 REG_WR(bp, PBF_REG_DISABLE_PF, 0); in bnx2x_init_hw_func()
8087 bnx2x_init_block(bp, BLOCK_CDU, init_phase); in bnx2x_init_hw_func()
8089 bnx2x_init_block(bp, BLOCK_CFC, init_phase); in bnx2x_init_hw_func()
8091 if (!CHIP_IS_E1x(bp)) in bnx2x_init_hw_func()
8092 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1); in bnx2x_init_hw_func()
8094 if (IS_MF(bp)) { in bnx2x_init_hw_func()
8095 if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) { in bnx2x_init_hw_func()
8096 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1); in bnx2x_init_hw_func()
8097 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8, in bnx2x_init_hw_func()
8098 bp->mf_ov); in bnx2x_init_hw_func()
8102 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); in bnx2x_init_hw_func()
8105 if (bp->common.int_block == INT_BLOCK_HC) { in bnx2x_init_hw_func()
8106 if (CHIP_IS_E1H(bp)) { in bnx2x_init_hw_func()
8107 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); in bnx2x_init_hw_func()
8109 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); in bnx2x_init_hw_func()
8110 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); in bnx2x_init_hw_func()
8112 bnx2x_init_block(bp, BLOCK_HC, init_phase); in bnx2x_init_hw_func()
8117 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); in bnx2x_init_hw_func()
8119 if (!CHIP_IS_E1x(bp)) { in bnx2x_init_hw_func()
8120 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); in bnx2x_init_hw_func()
8121 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); in bnx2x_init_hw_func()
8124 bnx2x_init_block(bp, BLOCK_IGU, init_phase); in bnx2x_init_hw_func()
8126 if (!CHIP_IS_E1x(bp)) { in bnx2x_init_hw_func()
8149 num_segs = CHIP_INT_MODE_IS_BC(bp) ? in bnx2x_init_hw_func()
8151 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) { in bnx2x_init_hw_func()
8152 prod_offset = (bp->igu_base_sb + sb_idx) * in bnx2x_init_hw_func()
8158 REG_WR(bp, addr, 0); in bnx2x_init_hw_func()
8161 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx, in bnx2x_init_hw_func()
8163 bnx2x_igu_clear_sb(bp, in bnx2x_init_hw_func()
8164 bp->igu_base_sb + sb_idx); in bnx2x_init_hw_func()
8168 num_segs = CHIP_INT_MODE_IS_BC(bp) ? in bnx2x_init_hw_func()
8171 if (CHIP_MODE_IS_4_PORT(bp)) in bnx2x_init_hw_func()
8172 dsb_idx = BP_FUNC(bp); in bnx2x_init_hw_func()
8174 dsb_idx = BP_VN(bp); in bnx2x_init_hw_func()
8176 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ? in bnx2x_init_hw_func()
8188 REG_WR(bp, addr, 0); in bnx2x_init_hw_func()
8191 if (CHIP_INT_MODE_IS_BC(bp)) { in bnx2x_init_hw_func()
8192 bnx2x_ack_sb(bp, bp->igu_dsb_id, in bnx2x_init_hw_func()
8194 bnx2x_ack_sb(bp, bp->igu_dsb_id, in bnx2x_init_hw_func()
8196 bnx2x_ack_sb(bp, bp->igu_dsb_id, in bnx2x_init_hw_func()
8198 bnx2x_ack_sb(bp, bp->igu_dsb_id, in bnx2x_init_hw_func()
8200 bnx2x_ack_sb(bp, bp->igu_dsb_id, in bnx2x_init_hw_func()
8203 bnx2x_ack_sb(bp, bp->igu_dsb_id, in bnx2x_init_hw_func()
8205 bnx2x_ack_sb(bp, bp->igu_dsb_id, in bnx2x_init_hw_func()
8208 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id); in bnx2x_init_hw_func()
8212 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); in bnx2x_init_hw_func()
8213 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0); in bnx2x_init_hw_func()
8214 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0); in bnx2x_init_hw_func()
8215 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0); in bnx2x_init_hw_func()
8216 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0); in bnx2x_init_hw_func()
8217 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0); in bnx2x_init_hw_func()
8222 REG_WR(bp, 0x2114, 0xffffffff); in bnx2x_init_hw_func()
8223 REG_WR(bp, 0x2120, 0xffffffff); in bnx2x_init_hw_func()
8225 if (CHIP_IS_E1x(bp)) { in bnx2x_init_hw_func()
8228 BP_PORT(bp) * (main_mem_size * 4); in bnx2x_init_hw_func()
8232 val = REG_RD(bp, main_mem_prty_clr); in bnx2x_init_hw_func()
8242 bnx2x_read_dmae(bp, i, main_mem_width / 4); in bnx2x_init_hw_func()
8243 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), in bnx2x_init_hw_func()
8247 REG_RD(bp, main_mem_prty_clr); in bnx2x_init_hw_func()
8252 REG_WR8(bp, BAR_USTRORM_INTMEM + in bnx2x_init_hw_func()
8253 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); in bnx2x_init_hw_func()
8254 REG_WR8(bp, BAR_TSTRORM_INTMEM + in bnx2x_init_hw_func()
8255 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); in bnx2x_init_hw_func()
8256 REG_WR8(bp, BAR_CSTRORM_INTMEM + in bnx2x_init_hw_func()
8257 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); in bnx2x_init_hw_func()
8258 REG_WR8(bp, BAR_XSTRORM_INTMEM + in bnx2x_init_hw_func()
8259 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); in bnx2x_init_hw_func()
8262 bnx2x_phy_probe(&bp->link_params); in bnx2x_init_hw_func()
8267 void bnx2x_free_mem_cnic(struct bnx2x *bp) in bnx2x_free_mem_cnic() argument
8269 bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE); in bnx2x_free_mem_cnic()
8271 if (!CHIP_IS_E1x(bp)) in bnx2x_free_mem_cnic()
8272 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping, in bnx2x_free_mem_cnic()
8275 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping, in bnx2x_free_mem_cnic()
8278 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ); in bnx2x_free_mem_cnic()
8281 void bnx2x_free_mem(struct bnx2x *bp) in bnx2x_free_mem() argument
8285 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping, in bnx2x_free_mem()
8286 bp->fw_stats_data_sz + bp->fw_stats_req_sz); in bnx2x_free_mem()
8288 if (IS_VF(bp)) in bnx2x_free_mem()
8291 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping, in bnx2x_free_mem()
8294 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping, in bnx2x_free_mem()
8297 for (i = 0; i < L2_ILT_LINES(bp); i++) in bnx2x_free_mem()
8298 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping, in bnx2x_free_mem()
8299 bp->context[i].size); in bnx2x_free_mem()
8300 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE); in bnx2x_free_mem()
8302 BNX2X_FREE(bp->ilt->lines); in bnx2x_free_mem()
8304 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE); in bnx2x_free_mem()
8306 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping, in bnx2x_free_mem()
8309 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ); in bnx2x_free_mem()
8311 bnx2x_iov_free_mem(bp); in bnx2x_free_mem()
8314 int bnx2x_alloc_mem_cnic(struct bnx2x *bp) in bnx2x_alloc_mem_cnic() argument
8316 if (!CHIP_IS_E1x(bp)) { in bnx2x_alloc_mem_cnic()
8318 bp->cnic_sb.e2_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping, in bnx2x_alloc_mem_cnic()
8320 if (!bp->cnic_sb.e2_sb) in bnx2x_alloc_mem_cnic()
8323 bp->cnic_sb.e1x_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping, in bnx2x_alloc_mem_cnic()
8325 if (!bp->cnic_sb.e1x_sb) in bnx2x_alloc_mem_cnic()
8329 if (CONFIGURE_NIC_MODE(bp) && !bp->t2) { in bnx2x_alloc_mem_cnic()
8331 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ); in bnx2x_alloc_mem_cnic()
8332 if (!bp->t2) in bnx2x_alloc_mem_cnic()
8337 bp->cnic_eth_dev.addr_drv_info_to_mcp = in bnx2x_alloc_mem_cnic()
8338 &bp->slowpath->drv_info_to_mcp; in bnx2x_alloc_mem_cnic()
8340 if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC)) in bnx2x_alloc_mem_cnic()
8346 bnx2x_free_mem_cnic(bp); in bnx2x_alloc_mem_cnic()
8351 int bnx2x_alloc_mem(struct bnx2x *bp) in bnx2x_alloc_mem() argument
8355 if (!CONFIGURE_NIC_MODE(bp) && !bp->t2) { in bnx2x_alloc_mem()
8357 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ); in bnx2x_alloc_mem()
8358 if (!bp->t2) in bnx2x_alloc_mem()
8362 bp->def_status_blk = BNX2X_PCI_ALLOC(&bp->def_status_blk_mapping, in bnx2x_alloc_mem()
8364 if (!bp->def_status_blk) in bnx2x_alloc_mem()
8367 bp->slowpath = BNX2X_PCI_ALLOC(&bp->slowpath_mapping, in bnx2x_alloc_mem()
8369 if (!bp->slowpath) in bnx2x_alloc_mem()
8385 context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp); in bnx2x_alloc_mem()
8388 bp->context[i].size = min(CDU_ILT_PAGE_SZ, in bnx2x_alloc_mem()
8390 bp->context[i].vcxt = BNX2X_PCI_ALLOC(&bp->context[i].cxt_mapping, in bnx2x_alloc_mem()
8391 bp->context[i].size); in bnx2x_alloc_mem()
8392 if (!bp->context[i].vcxt) in bnx2x_alloc_mem()
8394 allocated += bp->context[i].size; in bnx2x_alloc_mem()
8396 bp->ilt->lines = kcalloc(ILT_MAX_LINES, sizeof(struct ilt_line), in bnx2x_alloc_mem()
8398 if (!bp->ilt->lines) in bnx2x_alloc_mem()
8401 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC)) in bnx2x_alloc_mem()
8404 if (bnx2x_iov_alloc_mem(bp)) in bnx2x_alloc_mem()
8408 bp->spq = BNX2X_PCI_ALLOC(&bp->spq_mapping, BCM_PAGE_SIZE); in bnx2x_alloc_mem()
8409 if (!bp->spq) in bnx2x_alloc_mem()
8413 bp->eq_ring = BNX2X_PCI_ALLOC(&bp->eq_mapping, in bnx2x_alloc_mem()
8415 if (!bp->eq_ring) in bnx2x_alloc_mem()
8421 bnx2x_free_mem(bp); in bnx2x_alloc_mem()
8430 int bnx2x_set_mac_one(struct bnx2x *bp, const u8 *mac, in bnx2x_set_mac_one() argument
8456 rc = bnx2x_config_vlan_mac(bp, &ramrod_param); in bnx2x_set_mac_one()
8468 int bnx2x_set_vlan_one(struct bnx2x *bp, u16 vlan, in bnx2x_set_vlan_one() argument
8492 rc = bnx2x_config_vlan_mac(bp, &ramrod_param); in bnx2x_set_vlan_one()
8505 void bnx2x_clear_vlan_info(struct bnx2x *bp) in bnx2x_clear_vlan_info() argument
8510 list_for_each_entry(vlan, &bp->vlan_reg, link) in bnx2x_clear_vlan_info()
8513 bp->vlan_cnt = 0; in bnx2x_clear_vlan_info()
8516 static int bnx2x_del_all_vlans(struct bnx2x *bp) in bnx2x_del_all_vlans() argument
8518 struct bnx2x_vlan_mac_obj *vlan_obj = &bp->sp_objs[0].vlan_obj; in bnx2x_del_all_vlans()
8524 rc = vlan_obj->delete_all(bp, vlan_obj, &vlan_flags, &ramrod_flags); in bnx2x_del_all_vlans()
8528 bnx2x_clear_vlan_info(bp); in bnx2x_del_all_vlans()
8533 int bnx2x_del_all_macs(struct bnx2x *bp, in bnx2x_del_all_macs() argument
8547 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags); in bnx2x_del_all_macs()
8554 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set) in bnx2x_set_eth_mac() argument
8556 if (IS_PF(bp)) { in bnx2x_set_eth_mac()
8561 return bnx2x_set_mac_one(bp, bp->dev->dev_addr, in bnx2x_set_eth_mac()
8562 &bp->sp_objs->mac_obj, set, in bnx2x_set_eth_mac()
8565 return bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr, in bnx2x_set_eth_mac()
8566 bp->fp->index, set); in bnx2x_set_eth_mac()
8570 int bnx2x_setup_leading(struct bnx2x *bp) in bnx2x_setup_leading() argument
8572 if (IS_PF(bp)) in bnx2x_setup_leading()
8573 return bnx2x_setup_queue(bp, &bp->fp[0], true); in bnx2x_setup_leading()
8575 return bnx2x_vfpf_setup_q(bp, &bp->fp[0], true); in bnx2x_setup_leading()
8585 int bnx2x_set_int_mode(struct bnx2x *bp) in bnx2x_set_int_mode() argument
8589 if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX) { in bnx2x_set_int_mode()
8597 rc = bnx2x_enable_msix(bp); in bnx2x_set_int_mode()
8604 if (rc && IS_VF(bp)) in bnx2x_set_int_mode()
8609 bp->num_queues, in bnx2x_set_int_mode()
8610 1 + bp->num_cnic_queues); in bnx2x_set_int_mode()
8614 bnx2x_enable_msi(bp); in bnx2x_set_int_mode()
8618 bp->num_ethernet_queues = 1; in bnx2x_set_int_mode()
8619 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues; in bnx2x_set_int_mode()
8630 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp) in bnx2x_cid_ilt_lines() argument
8632 if (IS_SRIOV(bp)) in bnx2x_cid_ilt_lines()
8634 return L2_ILT_LINES(bp); in bnx2x_cid_ilt_lines()
8637 void bnx2x_ilt_set_info(struct bnx2x *bp) in bnx2x_ilt_set_info() argument
8640 struct bnx2x_ilt *ilt = BP_ILT(bp); in bnx2x_ilt_set_info()
8643 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp)); in bnx2x_ilt_set_info()
8652 line += bnx2x_cid_ilt_lines(bp); in bnx2x_ilt_set_info()
8654 if (CNIC_SUPPORT(bp)) in bnx2x_ilt_set_info()
8666 if (QM_INIT(bp->qm_cid_count)) { in bnx2x_ilt_set_info()
8674 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4, in bnx2x_ilt_set_info()
8688 if (CNIC_SUPPORT(bp)) { in bnx2x_ilt_set_info()
8738 static void bnx2x_pf_q_prep_init(struct bnx2x *bp, in bnx2x_pf_q_prep_init() argument
8756 init_params->rx.hc_rate = bp->rx_ticks ? in bnx2x_pf_q_prep_init()
8757 (1000000 / bp->rx_ticks) : 0; in bnx2x_pf_q_prep_init()
8758 init_params->tx.hc_rate = bp->tx_ticks ? in bnx2x_pf_q_prep_init()
8759 (1000000 / bp->tx_ticks) : 0; in bnx2x_pf_q_prep_init()
8785 &bp->context[cxt_index].vcxt[cxt_offset].eth; in bnx2x_pf_q_prep_init()
8789 static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp, in bnx2x_setup_tx_only() argument
8800 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false); in bnx2x_setup_tx_only()
8806 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index); in bnx2x_setup_tx_only()
8809 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index); in bnx2x_setup_tx_only()
8818 return bnx2x_queue_state_change(bp, q_params); in bnx2x_setup_tx_only()
8832 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp, in bnx2x_setup_queue() argument
8847 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0, in bnx2x_setup_queue()
8850 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; in bnx2x_setup_queue()
8855 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init); in bnx2x_setup_queue()
8861 rc = bnx2x_queue_state_change(bp, &q_params); in bnx2x_setup_queue()
8873 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading); in bnx2x_setup_queue()
8876 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params, in bnx2x_setup_queue()
8879 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params, in bnx2x_setup_queue()
8882 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params, in bnx2x_setup_queue()
8889 bp->fcoe_init = true; in bnx2x_setup_queue()
8892 rc = bnx2x_queue_state_change(bp, &q_params); in bnx2x_setup_queue()
8904 rc = bnx2x_setup_tx_only(bp, fp, &q_params, in bnx2x_setup_queue()
8916 static int bnx2x_stop_queue(struct bnx2x *bp, int index) in bnx2x_stop_queue() argument
8918 struct bnx2x_fastpath *fp = &bp->fp[index]; in bnx2x_stop_queue()
8925 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; in bnx2x_stop_queue()
8946 rc = bnx2x_queue_state_change(bp, &q_params); in bnx2x_stop_queue()
8955 rc = bnx2x_queue_state_change(bp, &q_params); in bnx2x_stop_queue()
8962 rc = bnx2x_queue_state_change(bp, &q_params); in bnx2x_stop_queue()
8971 rc = bnx2x_queue_state_change(bp, &q_params); in bnx2x_stop_queue()
8979 return bnx2x_queue_state_change(bp, &q_params); in bnx2x_stop_queue()
8982 static void bnx2x_reset_func(struct bnx2x *bp) in bnx2x_reset_func() argument
8984 int port = BP_PORT(bp); in bnx2x_reset_func()
8985 int func = BP_FUNC(bp); in bnx2x_reset_func()
8989 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0); in bnx2x_reset_func()
8990 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0); in bnx2x_reset_func()
8991 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0); in bnx2x_reset_func()
8992 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0); in bnx2x_reset_func()
8995 for_each_eth_queue(bp, i) { in bnx2x_reset_func()
8996 struct bnx2x_fastpath *fp = &bp->fp[i]; in bnx2x_reset_func()
8997 REG_WR8(bp, BAR_CSTRORM_INTMEM + in bnx2x_reset_func()
9002 if (CNIC_LOADED(bp)) in bnx2x_reset_func()
9004 REG_WR8(bp, BAR_CSTRORM_INTMEM + in bnx2x_reset_func()
9006 (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED); in bnx2x_reset_func()
9009 REG_WR8(bp, BAR_CSTRORM_INTMEM + in bnx2x_reset_func()
9014 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func), in bnx2x_reset_func()
9018 if (bp->common.int_block == INT_BLOCK_HC) { in bnx2x_reset_func()
9019 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); in bnx2x_reset_func()
9020 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); in bnx2x_reset_func()
9022 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); in bnx2x_reset_func()
9023 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); in bnx2x_reset_func()
9026 if (CNIC_LOADED(bp)) { in bnx2x_reset_func()
9028 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0); in bnx2x_reset_func()
9035 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4)) in bnx2x_reset_func()
9040 bnx2x_clear_func_ilt(bp, func); in bnx2x_reset_func()
9045 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) { in bnx2x_reset_func()
9053 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR); in bnx2x_reset_func()
9057 if (!CHIP_IS_E1x(bp)) in bnx2x_reset_func()
9058 bnx2x_pf_disable(bp); in bnx2x_reset_func()
9060 bp->dmae_ready = 0; in bnx2x_reset_func()
9063 static void bnx2x_reset_port(struct bnx2x *bp) in bnx2x_reset_port() argument
9065 int port = BP_PORT(bp); in bnx2x_reset_port()
9069 bnx2x__link_reset(bp); in bnx2x_reset_port()
9071 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); in bnx2x_reset_port()
9074 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0); in bnx2x_reset_port()
9076 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP : in bnx2x_reset_port()
9080 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0); in bnx2x_reset_port()
9084 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4); in bnx2x_reset_port()
9092 static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code) in bnx2x_reset_hw() argument
9099 func_params.f_obj = &bp->func_obj; in bnx2x_reset_hw()
9104 return bnx2x_func_state_change(bp, &func_params); in bnx2x_reset_hw()
9107 static int bnx2x_func_stop(struct bnx2x *bp) in bnx2x_func_stop() argument
9114 func_params.f_obj = &bp->func_obj; in bnx2x_func_stop()
9123 rc = bnx2x_func_state_change(bp, &func_params); in bnx2x_func_stop()
9130 return bnx2x_func_state_change(bp, &func_params); in bnx2x_func_stop()
9145 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode) in bnx2x_send_unload_req() argument
9148 int port = BP_PORT(bp); in bnx2x_send_unload_req()
9154 else if (bp->flags & NO_WOL_FLAG) in bnx2x_send_unload_req()
9157 else if (bp->wol) { in bnx2x_send_unload_req()
9159 const u8 *mac_addr = bp->dev->dev_addr; in bnx2x_send_unload_req()
9160 struct pci_dev *pdev = bp->pdev; in bnx2x_send_unload_req()
9167 u8 entry = (BP_VN(bp) + 1)*8; in bnx2x_send_unload_req()
9170 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val); in bnx2x_send_unload_req()
9174 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val); in bnx2x_send_unload_req()
9187 if (!BP_NOMCP(bp)) in bnx2x_send_unload_req()
9188 reset_code = bnx2x_fw_command(bp, reset_code, 0); in bnx2x_send_unload_req()
9190 int path = BP_PATH(bp); in bnx2x_send_unload_req()
9217 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link) in bnx2x_send_unload_done() argument
9222 if (!BP_NOMCP(bp)) in bnx2x_send_unload_done()
9223 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param); in bnx2x_send_unload_done()
9226 static int bnx2x_func_wait_started(struct bnx2x *bp) in bnx2x_func_wait_started() argument
9229 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; in bnx2x_func_wait_started()
9231 if (!bp->port.pmf) in bnx2x_func_wait_started()
9250 synchronize_irq(bp->msix_table[0].vector); in bnx2x_func_wait_started()
9252 synchronize_irq(bp->pdev->irq); in bnx2x_func_wait_started()
9257 while (bnx2x_func_get_state(bp, &bp->func_obj) != in bnx2x_func_wait_started()
9261 if (bnx2x_func_get_state(bp, &bp->func_obj) != in bnx2x_func_wait_started()
9276 func_params.f_obj = &bp->func_obj; in bnx2x_func_wait_started()
9282 bnx2x_func_state_change(bp, &func_params); in bnx2x_func_wait_started()
9286 return bnx2x_func_state_change(bp, &func_params); in bnx2x_func_wait_started()
9293 static void bnx2x_disable_ptp(struct bnx2x *bp) in bnx2x_disable_ptp() argument
9295 int port = BP_PORT(bp); in bnx2x_disable_ptp()
9298 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST : in bnx2x_disable_ptp()
9302 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : in bnx2x_disable_ptp()
9304 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK : in bnx2x_disable_ptp()
9306 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK : in bnx2x_disable_ptp()
9308 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK : in bnx2x_disable_ptp()
9312 REG_WR(bp, port ? NIG_REG_P1_PTP_EN : in bnx2x_disable_ptp()
9317 static void bnx2x_stop_ptp(struct bnx2x *bp) in bnx2x_stop_ptp() argument
9322 cancel_work_sync(&bp->ptp_task); in bnx2x_stop_ptp()
9324 if (bp->ptp_tx_skb) { in bnx2x_stop_ptp()
9325 dev_kfree_skb_any(bp->ptp_tx_skb); in bnx2x_stop_ptp()
9326 bp->ptp_tx_skb = NULL; in bnx2x_stop_ptp()
9330 bnx2x_disable_ptp(bp); in bnx2x_stop_ptp()
9335 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link) in bnx2x_chip_cleanup() argument
9337 int port = BP_PORT(bp); in bnx2x_chip_cleanup()
9344 for_each_tx_queue(bp, i) { in bnx2x_chip_cleanup()
9345 struct bnx2x_fastpath *fp = &bp->fp[i]; in bnx2x_chip_cleanup()
9348 rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]); in bnx2x_chip_cleanup()
9359 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC, in bnx2x_chip_cleanup()
9365 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC, in bnx2x_chip_cleanup()
9375 if (!CHIP_IS_E1x(bp)) { in bnx2x_chip_cleanup()
9377 rc = bnx2x_del_all_vlans(bp); in bnx2x_chip_cleanup()
9383 if (!CHIP_IS_E1(bp)) in bnx2x_chip_cleanup()
9384 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); in bnx2x_chip_cleanup()
9390 netif_addr_lock_bh(bp->dev); in bnx2x_chip_cleanup()
9392 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) in bnx2x_chip_cleanup()
9393 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); in bnx2x_chip_cleanup()
9394 else if (bp->slowpath) in bnx2x_chip_cleanup()
9395 bnx2x_set_storm_rx_mode(bp); in bnx2x_chip_cleanup()
9398 rparam.mcast_obj = &bp->mcast_obj; in bnx2x_chip_cleanup()
9399 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); in bnx2x_chip_cleanup()
9403 netif_addr_unlock_bh(bp->dev); in bnx2x_chip_cleanup()
9405 bnx2x_iov_chip_cleanup(bp); in bnx2x_chip_cleanup()
9412 reset_code = bnx2x_send_unload_req(bp, unload_mode); in bnx2x_chip_cleanup()
9418 rc = bnx2x_func_wait_started(bp); in bnx2x_chip_cleanup()
9429 for_each_eth_queue(bp, i) in bnx2x_chip_cleanup()
9430 if (bnx2x_stop_queue(bp, i)) in bnx2x_chip_cleanup()
9437 if (CNIC_LOADED(bp)) { in bnx2x_chip_cleanup()
9438 for_each_cnic_queue(bp, i) in bnx2x_chip_cleanup()
9439 if (bnx2x_stop_queue(bp, i)) in bnx2x_chip_cleanup()
9450 if (!bnx2x_wait_sp_comp(bp, ~0x0UL)) in bnx2x_chip_cleanup()
9456 rc = bnx2x_func_stop(bp); in bnx2x_chip_cleanup()
9469 if (bp->flags & PTP_SUPPORTED) { in bnx2x_chip_cleanup()
9470 bnx2x_stop_ptp(bp); in bnx2x_chip_cleanup()
9471 if (bp->ptp_clock) { in bnx2x_chip_cleanup()
9472 ptp_clock_unregister(bp->ptp_clock); in bnx2x_chip_cleanup()
9473 bp->ptp_clock = NULL; in bnx2x_chip_cleanup()
9477 if (!bp->nic_stopped) { in bnx2x_chip_cleanup()
9479 bnx2x_netif_stop(bp, 1); in bnx2x_chip_cleanup()
9481 bnx2x_del_all_napi(bp); in bnx2x_chip_cleanup()
9482 if (CNIC_LOADED(bp)) in bnx2x_chip_cleanup()
9483 bnx2x_del_all_napi_cnic(bp); in bnx2x_chip_cleanup()
9486 bnx2x_free_irq(bp); in bnx2x_chip_cleanup()
9487 bp->nic_stopped = true; in bnx2x_chip_cleanup()
9495 if (!pci_channel_offline(bp->pdev)) { in bnx2x_chip_cleanup()
9496 rc = bnx2x_reset_hw(bp, reset_code); in bnx2x_chip_cleanup()
9502 bnx2x_send_unload_done(bp, keep_link); in bnx2x_chip_cleanup()
9505 void bnx2x_disable_close_the_gate(struct bnx2x *bp) in bnx2x_disable_close_the_gate() argument
9511 if (CHIP_IS_E1(bp)) { in bnx2x_disable_close_the_gate()
9512 int port = BP_PORT(bp); in bnx2x_disable_close_the_gate()
9516 val = REG_RD(bp, addr); in bnx2x_disable_close_the_gate()
9518 REG_WR(bp, addr, val); in bnx2x_disable_close_the_gate()
9520 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK); in bnx2x_disable_close_the_gate()
9523 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val); in bnx2x_disable_close_the_gate()
9528 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close) in bnx2x_set_234_gates() argument
9533 if (!CHIP_IS_E1(bp)) { in bnx2x_set_234_gates()
9535 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close); in bnx2x_set_234_gates()
9537 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close); in bnx2x_set_234_gates()
9541 if (CHIP_IS_E1x(bp)) { in bnx2x_set_234_gates()
9543 val = REG_RD(bp, HC_REG_CONFIG_1); in bnx2x_set_234_gates()
9544 REG_WR(bp, HC_REG_CONFIG_1, in bnx2x_set_234_gates()
9548 val = REG_RD(bp, HC_REG_CONFIG_0); in bnx2x_set_234_gates()
9549 REG_WR(bp, HC_REG_CONFIG_0, in bnx2x_set_234_gates()
9554 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); in bnx2x_set_234_gates()
9556 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, in bnx2x_set_234_gates()
9568 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val) in bnx2x_clp_reset_prep() argument
9571 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); in bnx2x_clp_reset_prep()
9573 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC); in bnx2x_clp_reset_prep()
9582 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val) in bnx2x_clp_reset_done() argument
9585 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); in bnx2x_clp_reset_done()
9586 MF_CFG_WR(bp, shared_mf_config.clp_mb, in bnx2x_clp_reset_done()
9598 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val) in bnx2x_reset_mcp_prep() argument
9606 if (!CHIP_IS_E1(bp)) in bnx2x_reset_mcp_prep()
9607 bnx2x_clp_reset_prep(bp, magic_val); in bnx2x_reset_mcp_prep()
9610 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); in bnx2x_reset_mcp_prep()
9612 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]); in bnx2x_reset_mcp_prep()
9616 REG_WR(bp, shmem + validity_offset, 0); in bnx2x_reset_mcp_prep()
9627 static void bnx2x_mcp_wait_one(struct bnx2x *bp) in bnx2x_mcp_wait_one() argument
9631 if (CHIP_REV_IS_SLOW(bp)) in bnx2x_mcp_wait_one()
9640 static int bnx2x_init_shmem(struct bnx2x *bp) in bnx2x_init_shmem() argument
9646 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); in bnx2x_init_shmem()
9651 if (bp->common.shmem_base == 0xFFFFFFFF) { in bnx2x_init_shmem()
9652 bp->flags |= NO_MCP_FLAG; in bnx2x_init_shmem()
9656 if (bp->common.shmem_base) { in bnx2x_init_shmem()
9657 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]); in bnx2x_init_shmem()
9662 bnx2x_mcp_wait_one(bp); in bnx2x_init_shmem()
9671 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val) in bnx2x_reset_mcp_comp() argument
9673 int rc = bnx2x_init_shmem(bp); in bnx2x_reset_mcp_comp()
9676 if (!CHIP_IS_E1(bp)) in bnx2x_reset_mcp_comp()
9677 bnx2x_clp_reset_done(bp, magic_val); in bnx2x_reset_mcp_comp()
9682 static void bnx2x_pxp_prep(struct bnx2x *bp) in bnx2x_pxp_prep() argument
9684 if (!CHIP_IS_E1(bp)) { in bnx2x_pxp_prep()
9685 REG_WR(bp, PXP2_REG_RD_START_INIT, 0); in bnx2x_pxp_prep()
9686 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0); in bnx2x_pxp_prep()
9700 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global) in bnx2x_process_kill_chip_reset() argument
9752 if (CHIP_IS_E1(bp)) in bnx2x_process_kill_chip_reset()
9754 else if (CHIP_IS_E1H(bp)) in bnx2x_process_kill_chip_reset()
9756 else if (CHIP_IS_E2(bp)) in bnx2x_process_kill_chip_reset()
9779 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in bnx2x_process_kill_chip_reset()
9782 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, in bnx2x_process_kill_chip_reset()
9787 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, in bnx2x_process_kill_chip_reset()
9792 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1); in bnx2x_process_kill_chip_reset()
9804 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp) in bnx2x_er_poll_igu_vq() argument
9810 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS); in bnx2x_er_poll_igu_vq()
9827 static int bnx2x_process_kill(struct bnx2x *bp, bool global) in bnx2x_process_kill() argument
9836 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT); in bnx2x_process_kill()
9837 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT); in bnx2x_process_kill()
9838 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0); in bnx2x_process_kill()
9839 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1); in bnx2x_process_kill()
9840 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2); in bnx2x_process_kill()
9841 if (CHIP_IS_E3(bp)) in bnx2x_process_kill()
9842 tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32); in bnx2x_process_kill()
9848 (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff))) in bnx2x_process_kill()
9864 bnx2x_set_234_gates(bp, true); in bnx2x_process_kill()
9867 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp)) in bnx2x_process_kill()
9873 REG_WR(bp, MISC_REG_UNPREPARED, 0); in bnx2x_process_kill()
9884 bnx2x_reset_mcp_prep(bp, &val); in bnx2x_process_kill()
9887 bnx2x_pxp_prep(bp); in bnx2x_process_kill()
9891 bnx2x_process_kill_chip_reset(bp, global); in bnx2x_process_kill()
9895 if (!CHIP_IS_E1x(bp)) in bnx2x_process_kill()
9896 REG_WR(bp, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f); in bnx2x_process_kill()
9900 if (global && bnx2x_reset_mcp_comp(bp, val)) in bnx2x_process_kill()
9906 bnx2x_set_234_gates(bp, false); in bnx2x_process_kill()
9914 static int bnx2x_leader_reset(struct bnx2x *bp) in bnx2x_leader_reset() argument
9917 bool global = bnx2x_reset_is_global(bp); in bnx2x_leader_reset()
9923 if (!global && !BP_NOMCP(bp)) { in bnx2x_leader_reset()
9924 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ, in bnx2x_leader_reset()
9937 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0); in bnx2x_leader_reset()
9946 if (bnx2x_process_kill(bp, global)) { in bnx2x_leader_reset()
9948 BP_PATH(bp)); in bnx2x_leader_reset()
9957 bnx2x_set_reset_done(bp); in bnx2x_leader_reset()
9959 bnx2x_clear_reset_global(bp); in bnx2x_leader_reset()
9963 if (!global && !BP_NOMCP(bp)) { in bnx2x_leader_reset()
9964 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0); in bnx2x_leader_reset()
9965 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); in bnx2x_leader_reset()
9968 bp->is_leader = 0; in bnx2x_leader_reset()
9969 bnx2x_release_leader_lock(bp); in bnx2x_leader_reset()
9974 static void bnx2x_recovery_failed(struct bnx2x *bp) in bnx2x_recovery_failed() argument
9976 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n"); in bnx2x_recovery_failed()
9979 netif_device_detach(bp->dev); in bnx2x_recovery_failed()
9985 bnx2x_set_reset_in_progress(bp); in bnx2x_recovery_failed()
9988 bnx2x_set_power_state(bp, PCI_D3hot); in bnx2x_recovery_failed()
9990 bp->recovery_state = BNX2X_RECOVERY_FAILED; in bnx2x_recovery_failed()
10000 static void bnx2x_parity_recover(struct bnx2x *bp) in bnx2x_parity_recover() argument
10007 for (vf_idx = 0; vf_idx < bp->requested_nr_virtfn; vf_idx++) { in bnx2x_parity_recover()
10008 struct bnx2x_virtf *vf = BP_VF(bp, vf_idx); in bnx2x_parity_recover()
10016 switch (bp->recovery_state) { in bnx2x_parity_recover()
10019 is_parity = bnx2x_chk_parity_attn(bp, &global, false); in bnx2x_parity_recover()
10023 if (bnx2x_trylock_leader_lock(bp)) { in bnx2x_parity_recover()
10024 bnx2x_set_reset_in_progress(bp); in bnx2x_parity_recover()
10032 bnx2x_set_reset_global(bp); in bnx2x_parity_recover()
10034 bp->is_leader = 1; in bnx2x_parity_recover()
10039 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false)) in bnx2x_parity_recover()
10042 bp->recovery_state = BNX2X_RECOVERY_WAIT; in bnx2x_parity_recover()
10053 if (bp->is_leader) { in bnx2x_parity_recover()
10054 int other_engine = BP_PATH(bp) ? 0 : 1; in bnx2x_parity_recover()
10056 bnx2x_get_load_status(bp, other_engine); in bnx2x_parity_recover()
10058 bnx2x_get_load_status(bp, BP_PATH(bp)); in bnx2x_parity_recover()
10059 global = bnx2x_reset_is_global(bp); in bnx2x_parity_recover()
10074 schedule_delayed_work(&bp->sp_rtnl_task, in bnx2x_parity_recover()
10083 if (bnx2x_leader_reset(bp)) { in bnx2x_parity_recover()
10084 bnx2x_recovery_failed(bp); in bnx2x_parity_recover()
10096 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) { in bnx2x_parity_recover()
10103 if (bnx2x_trylock_leader_lock(bp)) { in bnx2x_parity_recover()
10107 bp->is_leader = 1; in bnx2x_parity_recover()
10111 schedule_delayed_work(&bp->sp_rtnl_task, in bnx2x_parity_recover()
10120 if (bnx2x_reset_is_global(bp)) { in bnx2x_parity_recover()
10122 &bp->sp_rtnl_task, in bnx2x_parity_recover()
10128 bp->eth_stats.recoverable_error; in bnx2x_parity_recover()
10130 bp->eth_stats.unrecoverable_error; in bnx2x_parity_recover()
10131 bp->recovery_state = in bnx2x_parity_recover()
10133 if (bnx2x_nic_load(bp, LOAD_NORMAL)) { in bnx2x_parity_recover()
10135 netdev_err(bp->dev, in bnx2x_parity_recover()
10138 netif_device_detach(bp->dev); in bnx2x_parity_recover()
10141 bp, PCI_D3hot); in bnx2x_parity_recover()
10144 bp->recovery_state = in bnx2x_parity_recover()
10149 bp->eth_stats.recoverable_error = in bnx2x_parity_recover()
10151 bp->eth_stats.unrecoverable_error = in bnx2x_parity_recover()
10163 static int bnx2x_udp_port_update(struct bnx2x *bp) in bnx2x_udp_port_update() argument
10176 func_params.f_obj = &bp->func_obj; in bnx2x_udp_port_update()
10183 if (bp->udp_tunnel_ports[BNX2X_UDP_PORT_GENEVE]) { in bnx2x_udp_port_update()
10184 geneve_port = bp->udp_tunnel_ports[BNX2X_UDP_PORT_GENEVE]; in bnx2x_udp_port_update()
10188 if (bp->udp_tunnel_ports[BNX2X_UDP_PORT_VXLAN]) { in bnx2x_udp_port_update()
10189 vxlan_port = bp->udp_tunnel_ports[BNX2X_UDP_PORT_VXLAN]; in bnx2x_udp_port_update()
10197 rc = bnx2x_func_state_change(bp, &func_params); in bnx2x_udp_port_update()
10211 struct bnx2x *bp = netdev_priv(netdev); in bnx2x_udp_tunnel_sync() local
10215 bp->udp_tunnel_ports[table] = be16_to_cpu(ti.port); in bnx2x_udp_tunnel_sync()
10217 return bnx2x_udp_port_update(bp); in bnx2x_udp_tunnel_sync()
10237 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work); in bnx2x_sp_rtnl_task() local
10241 if (!netif_running(bp->dev)) { in bnx2x_sp_rtnl_task()
10246 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) { in bnx2x_sp_rtnl_task()
10256 bp->sp_rtnl_state = 0; in bnx2x_sp_rtnl_task()
10259 bnx2x_parity_recover(bp); in bnx2x_sp_rtnl_task()
10265 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) { in bnx2x_sp_rtnl_task()
10276 bp->sp_rtnl_state = 0; in bnx2x_sp_rtnl_task()
10280 bp->link_vars.link_up = 0; in bnx2x_sp_rtnl_task()
10281 bp->force_link_down = true; in bnx2x_sp_rtnl_task()
10282 netif_carrier_off(bp->dev); in bnx2x_sp_rtnl_task()
10285 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true); in bnx2x_sp_rtnl_task()
10290 if (bnx2x_nic_load(bp, LOAD_NORMAL) == -ENOMEM) { in bnx2x_sp_rtnl_task()
10291 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true); in bnx2x_sp_rtnl_task()
10292 if (bnx2x_nic_load(bp, LOAD_NORMAL)) in bnx2x_sp_rtnl_task()
10301 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state)) in bnx2x_sp_rtnl_task()
10302 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos); in bnx2x_sp_rtnl_task()
10303 if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state)) in bnx2x_sp_rtnl_task()
10304 bnx2x_after_function_update(bp); in bnx2x_sp_rtnl_task()
10310 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) { in bnx2x_sp_rtnl_task()
10312 netif_device_detach(bp->dev); in bnx2x_sp_rtnl_task()
10313 bnx2x_close(bp->dev); in bnx2x_sp_rtnl_task()
10318 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) { in bnx2x_sp_rtnl_task()
10321 bnx2x_vfpf_set_mcast(bp->dev); in bnx2x_sp_rtnl_task()
10324 &bp->sp_rtnl_state)){ in bnx2x_sp_rtnl_task()
10325 if (netif_carrier_ok(bp->dev)) { in bnx2x_sp_rtnl_task()
10326 bnx2x_tx_disable(bp); in bnx2x_sp_rtnl_task()
10331 if (test_and_clear_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state)) { in bnx2x_sp_rtnl_task()
10333 bnx2x_set_rx_mode_inner(bp); in bnx2x_sp_rtnl_task()
10337 &bp->sp_rtnl_state)) in bnx2x_sp_rtnl_task()
10338 bnx2x_pf_set_vfs_vlan(bp); in bnx2x_sp_rtnl_task()
10340 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP, &bp->sp_rtnl_state)) { in bnx2x_sp_rtnl_task()
10341 bnx2x_dcbx_stop_hw_tx(bp); in bnx2x_sp_rtnl_task()
10342 bnx2x_dcbx_resume_hw_tx(bp); in bnx2x_sp_rtnl_task()
10346 &bp->sp_rtnl_state)) in bnx2x_sp_rtnl_task()
10347 bnx2x_update_mng_version(bp); in bnx2x_sp_rtnl_task()
10349 if (test_and_clear_bit(BNX2X_SP_RTNL_UPDATE_SVID, &bp->sp_rtnl_state)) in bnx2x_sp_rtnl_task()
10350 bnx2x_handle_update_svid_cmd(bp); in bnx2x_sp_rtnl_task()
10358 if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV, in bnx2x_sp_rtnl_task()
10359 &bp->sp_rtnl_state)) { in bnx2x_sp_rtnl_task()
10360 bnx2x_disable_sriov(bp); in bnx2x_sp_rtnl_task()
10361 bnx2x_enable_sriov(bp); in bnx2x_sp_rtnl_task()
10367 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work); in bnx2x_period_task() local
10369 if (!netif_running(bp->dev)) in bnx2x_period_task()
10372 if (CHIP_REV_IS_SLOW(bp)) { in bnx2x_period_task()
10377 bnx2x_acquire_phy_lock(bp); in bnx2x_period_task()
10384 if (bp->port.pmf) { in bnx2x_period_task()
10385 bnx2x_period_func(&bp->link_params, &bp->link_vars); in bnx2x_period_task()
10388 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ); in bnx2x_period_task()
10391 bnx2x_release_phy_lock(bp); in bnx2x_period_task()
10400 static u32 bnx2x_get_pretend_reg(struct bnx2x *bp) in bnx2x_get_pretend_reg() argument
10404 return base + (BP_ABS_FUNC(bp)) * stride; in bnx2x_get_pretend_reg()
10407 static bool bnx2x_prev_unload_close_umac(struct bnx2x *bp, in bnx2x_prev_unload_close_umac() argument
10420 vals->umac_val[port] = REG_RD(bp, vals->umac_addr[port]); in bnx2x_prev_unload_close_umac()
10421 REG_WR(bp, vals->umac_addr[port], 0); in bnx2x_prev_unload_close_umac()
10426 static void bnx2x_prev_unload_close_mac(struct bnx2x *bp, in bnx2x_prev_unload_close_mac() argument
10431 u8 port = BP_PORT(bp); in bnx2x_prev_unload_close_mac()
10436 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2); in bnx2x_prev_unload_close_mac()
10438 if (!CHIP_IS_E3(bp)) { in bnx2x_prev_unload_close_mac()
10439 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4); in bnx2x_prev_unload_close_mac()
10444 base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM in bnx2x_prev_unload_close_mac()
10446 offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL in bnx2x_prev_unload_close_mac()
10455 wb_data[0] = REG_RD(bp, base_addr + offset); in bnx2x_prev_unload_close_mac()
10456 wb_data[1] = REG_RD(bp, base_addr + offset + 0x4); in bnx2x_prev_unload_close_mac()
10461 REG_WR(bp, vals->bmac_addr, wb_data[0]); in bnx2x_prev_unload_close_mac()
10462 REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]); in bnx2x_prev_unload_close_mac()
10465 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4; in bnx2x_prev_unload_close_mac()
10466 vals->emac_val = REG_RD(bp, vals->emac_addr); in bnx2x_prev_unload_close_mac()
10467 REG_WR(bp, vals->emac_addr, 0); in bnx2x_prev_unload_close_mac()
10472 base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; in bnx2x_prev_unload_close_mac()
10473 val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI); in bnx2x_prev_unload_close_mac()
10474 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI, in bnx2x_prev_unload_close_mac()
10476 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI, in bnx2x_prev_unload_close_mac()
10479 vals->xmac_val = REG_RD(bp, vals->xmac_addr); in bnx2x_prev_unload_close_mac()
10480 REG_WR(bp, vals->xmac_addr, 0); in bnx2x_prev_unload_close_mac()
10484 mac_stopped |= bnx2x_prev_unload_close_umac(bp, 0, in bnx2x_prev_unload_close_mac()
10486 mac_stopped |= bnx2x_prev_unload_close_umac(bp, 1, in bnx2x_prev_unload_close_mac()
10505 static bool bnx2x_prev_is_after_undi(struct bnx2x *bp) in bnx2x_prev_is_after_undi() argument
10510 if (!(REG_RD(bp, MISC_REG_RESET_REG_1) & in bnx2x_prev_is_after_undi()
10514 if (REG_RD(bp, DORQ_REG_NORM_CID_OFST) == 0x7) { in bnx2x_prev_is_after_undi()
10522 static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 inc) in bnx2x_prev_unload_undi_inc() argument
10527 if (BP_FUNC(bp) < 2) in bnx2x_prev_unload_undi_inc()
10528 addr = BNX2X_PREV_UNDI_PROD_ADDR(BP_PORT(bp)); in bnx2x_prev_unload_undi_inc()
10530 addr = BNX2X_PREV_UNDI_PROD_ADDR_H(BP_FUNC(bp) - 2); in bnx2x_prev_unload_undi_inc()
10532 tmp_reg = REG_RD(bp, addr); in bnx2x_prev_unload_undi_inc()
10537 REG_WR(bp, addr, tmp_reg); in bnx2x_prev_unload_undi_inc()
10540 BP_PORT(bp), BP_FUNC(bp), addr, bd, rcq); in bnx2x_prev_unload_undi_inc()
10543 static int bnx2x_prev_mcp_done(struct bnx2x *bp) in bnx2x_prev_mcp_done() argument
10545 u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, in bnx2x_prev_mcp_done()
10556 bnx2x_prev_path_get_entry(struct bnx2x *bp) in bnx2x_prev_path_get_entry() argument
10561 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot && in bnx2x_prev_path_get_entry()
10562 bp->pdev->bus->number == tmp_list->bus && in bnx2x_prev_path_get_entry()
10563 BP_PATH(bp) == tmp_list->path) in bnx2x_prev_path_get_entry()
10569 static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp) in bnx2x_prev_path_mark_eeh() argument
10580 tmp_list = bnx2x_prev_path_get_entry(bp); in bnx2x_prev_path_mark_eeh()
10586 BP_PATH(bp)); in bnx2x_prev_path_mark_eeh()
10594 static bool bnx2x_prev_is_path_marked(struct bnx2x *bp) in bnx2x_prev_is_path_marked() argument
10602 tmp_list = bnx2x_prev_path_get_entry(bp); in bnx2x_prev_is_path_marked()
10606 BP_PATH(bp)); in bnx2x_prev_is_path_marked()
10610 BP_PATH(bp)); in bnx2x_prev_is_path_marked()
10619 bool bnx2x_port_after_undi(struct bnx2x *bp) in bnx2x_port_after_undi() argument
10626 entry = bnx2x_prev_path_get_entry(bp); in bnx2x_port_after_undi()
10627 val = !!(entry && (entry->undi & (1 << BP_PORT(bp)))); in bnx2x_port_after_undi()
10634 static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi) in bnx2x_prev_mark_path() argument
10646 tmp_list = bnx2x_prev_path_get_entry(bp); in bnx2x_prev_mark_path()
10652 BP_PATH(bp)); in bnx2x_prev_mark_path()
10667 tmp_list->bus = bp->pdev->bus->number; in bnx2x_prev_mark_path()
10668 tmp_list->slot = PCI_SLOT(bp->pdev->devfn); in bnx2x_prev_mark_path()
10669 tmp_list->path = BP_PATH(bp); in bnx2x_prev_mark_path()
10671 tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0; in bnx2x_prev_mark_path()
10679 BP_PATH(bp)); in bnx2x_prev_mark_path()
10687 static int bnx2x_do_flr(struct bnx2x *bp) in bnx2x_do_flr() argument
10689 struct pci_dev *dev = bp->pdev; in bnx2x_do_flr()
10691 if (CHIP_IS_E1x(bp)) { in bnx2x_do_flr()
10697 if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) { in bnx2x_do_flr()
10699 bp->common.bc_ver); in bnx2x_do_flr()
10707 bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0); in bnx2x_do_flr()
10712 static int bnx2x_prev_unload_uncommon(struct bnx2x *bp) in bnx2x_prev_unload_uncommon() argument
10719 if (bnx2x_prev_is_path_marked(bp)) in bnx2x_prev_unload_uncommon()
10720 return bnx2x_prev_mcp_done(bp); in bnx2x_prev_unload_uncommon()
10725 if (bnx2x_prev_is_after_undi(bp)) in bnx2x_prev_unload_uncommon()
10732 rc = bnx2x_compare_fw_ver(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION, false); in bnx2x_prev_unload_uncommon()
10737 rc = bnx2x_do_flr(bp); in bnx2x_prev_unload_uncommon()
10750 rc = bnx2x_prev_mcp_done(bp); in bnx2x_prev_unload_uncommon()
10757 static int bnx2x_prev_unload_common(struct bnx2x *bp) in bnx2x_prev_unload_common() argument
10771 if (bnx2x_prev_is_path_marked(bp)) in bnx2x_prev_unload_common()
10772 return bnx2x_prev_mcp_done(bp); in bnx2x_prev_unload_common()
10774 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1); in bnx2x_prev_unload_common()
10781 bnx2x_prev_unload_close_mac(bp, &mac_vals); in bnx2x_prev_unload_common()
10784 bnx2x_set_rx_filter(&bp->link_params, 0); in bnx2x_prev_unload_common()
10785 bp->link_params.port ^= 1; in bnx2x_prev_unload_common()
10786 bnx2x_set_rx_filter(&bp->link_params, 0); in bnx2x_prev_unload_common()
10787 bp->link_params.port ^= 1; in bnx2x_prev_unload_common()
10790 if (bnx2x_prev_is_after_undi(bp)) { in bnx2x_prev_unload_common()
10793 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0); in bnx2x_prev_unload_common()
10795 REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0); in bnx2x_prev_unload_common()
10797 if (!CHIP_IS_E1x(bp)) in bnx2x_prev_unload_common()
10799 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); in bnx2x_prev_unload_common()
10802 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS); in bnx2x_prev_unload_common()
10806 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS); in bnx2x_prev_unload_common()
10820 bnx2x_prev_unload_undi_inc(bp, 1); in bnx2x_prev_unload_common()
10830 bnx2x_reset_common(bp); in bnx2x_prev_unload_common()
10833 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val); in bnx2x_prev_unload_common()
10835 REG_WR(bp, mac_vals.umac_addr[0], mac_vals.umac_val[0]); in bnx2x_prev_unload_common()
10837 REG_WR(bp, mac_vals.umac_addr[1], mac_vals.umac_val[1]); in bnx2x_prev_unload_common()
10839 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val); in bnx2x_prev_unload_common()
10841 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]); in bnx2x_prev_unload_common()
10842 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]); in bnx2x_prev_unload_common()
10845 rc = bnx2x_prev_mark_path(bp, prev_undi); in bnx2x_prev_unload_common()
10847 bnx2x_prev_mcp_done(bp); in bnx2x_prev_unload_common()
10851 return bnx2x_prev_mcp_done(bp); in bnx2x_prev_unload_common()
10854 static int bnx2x_prev_unload(struct bnx2x *bp) in bnx2x_prev_unload() argument
10863 bnx2x_clean_pglue_errors(bp); in bnx2x_prev_unload()
10866 hw_lock_reg = (BP_FUNC(bp) <= 5) ? in bnx2x_prev_unload()
10867 (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) : in bnx2x_prev_unload()
10868 (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8); in bnx2x_prev_unload()
10870 hw_lock_val = REG_RD(bp, hw_lock_reg); in bnx2x_prev_unload()
10874 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, in bnx2x_prev_unload()
10875 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp))); in bnx2x_prev_unload()
10879 REG_WR(bp, hw_lock_reg, 0xffffffff); in bnx2x_prev_unload()
10883 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) { in bnx2x_prev_unload()
10885 bnx2x_release_alr(bp); in bnx2x_prev_unload()
10891 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0); in bnx2x_prev_unload()
10904 aer = !!(bnx2x_prev_path_get_entry(bp) && in bnx2x_prev_unload()
10905 bnx2x_prev_path_get_entry(bp)->aer); in bnx2x_prev_unload()
10910 rc = bnx2x_prev_unload_common(bp); in bnx2x_prev_unload()
10915 rc = bnx2x_prev_unload_uncommon(bp); in bnx2x_prev_unload()
10928 if (bnx2x_port_after_undi(bp)) in bnx2x_prev_unload()
10929 bp->link_params.feature_config_flags |= in bnx2x_prev_unload()
10937 static void bnx2x_get_common_hwinfo(struct bnx2x *bp) in bnx2x_get_common_hwinfo() argument
10944 val = REG_RD(bp, MISC_REG_CHIP_NUM); in bnx2x_get_common_hwinfo()
10946 val = REG_RD(bp, MISC_REG_CHIP_REV); in bnx2x_get_common_hwinfo()
10952 val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3); in bnx2x_get_common_hwinfo()
10954 val = REG_RD(bp, MISC_REG_BOND_ID); in bnx2x_get_common_hwinfo()
10956 bp->common.chip_id = id; in bnx2x_get_common_hwinfo()
10959 if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) { in bnx2x_get_common_hwinfo()
10960 if (CHIP_IS_57810(bp)) in bnx2x_get_common_hwinfo()
10961 bp->common.chip_id = (CHIP_NUM_57811 << 16) | in bnx2x_get_common_hwinfo()
10962 (bp->common.chip_id & 0x0000FFFF); in bnx2x_get_common_hwinfo()
10963 else if (CHIP_IS_57810_MF(bp)) in bnx2x_get_common_hwinfo()
10964 bp->common.chip_id = (CHIP_NUM_57811_MF << 16) | in bnx2x_get_common_hwinfo()
10965 (bp->common.chip_id & 0x0000FFFF); in bnx2x_get_common_hwinfo()
10966 bp->common.chip_id |= 0x1; in bnx2x_get_common_hwinfo()
10970 bp->db_size = (1 << BNX2X_DB_SHIFT); in bnx2x_get_common_hwinfo()
10972 if (!CHIP_IS_E1x(bp)) { in bnx2x_get_common_hwinfo()
10973 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR); in bnx2x_get_common_hwinfo()
10975 val = REG_RD(bp, MISC_REG_PORT4MODE_EN); in bnx2x_get_common_hwinfo()
10980 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE : in bnx2x_get_common_hwinfo()
10983 if (CHIP_MODE_IS_4_PORT(bp)) in bnx2x_get_common_hwinfo()
10984 bp->pfid = (bp->pf_num >> 1); /* 0..3 */ in bnx2x_get_common_hwinfo()
10986 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */ in bnx2x_get_common_hwinfo()
10988 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */ in bnx2x_get_common_hwinfo()
10989 bp->pfid = bp->pf_num; /* 0..7 */ in bnx2x_get_common_hwinfo()
10992 BNX2X_DEV_INFO("pf_id: %x", bp->pfid); in bnx2x_get_common_hwinfo()
10994 bp->link_params.chip_id = bp->common.chip_id; in bnx2x_get_common_hwinfo()
10997 val = (REG_RD(bp, 0x2874) & 0x55); in bnx2x_get_common_hwinfo()
10998 if ((bp->common.chip_id & 0x1) || in bnx2x_get_common_hwinfo()
10999 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) { in bnx2x_get_common_hwinfo()
11000 bp->flags |= ONE_PORT_FLAG; in bnx2x_get_common_hwinfo()
11004 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4); in bnx2x_get_common_hwinfo()
11005 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE << in bnx2x_get_common_hwinfo()
11008 bp->common.flash_size, bp->common.flash_size); in bnx2x_get_common_hwinfo()
11010 bnx2x_init_shmem(bp); in bnx2x_get_common_hwinfo()
11012 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ? in bnx2x_get_common_hwinfo()
11016 bp->link_params.shmem_base = bp->common.shmem_base; in bnx2x_get_common_hwinfo()
11017 bp->link_params.shmem2_base = bp->common.shmem2_base; in bnx2x_get_common_hwinfo()
11018 if (SHMEM2_RD(bp, size) > in bnx2x_get_common_hwinfo()
11019 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)])) in bnx2x_get_common_hwinfo()
11020 bp->link_params.lfa_base = in bnx2x_get_common_hwinfo()
11021 REG_RD(bp, bp->common.shmem2_base + in bnx2x_get_common_hwinfo()
11023 lfa_host_addr[BP_PORT(bp)])); in bnx2x_get_common_hwinfo()
11025 bp->link_params.lfa_base = 0; in bnx2x_get_common_hwinfo()
11027 bp->common.shmem_base, bp->common.shmem2_base); in bnx2x_get_common_hwinfo()
11029 if (!bp->common.shmem_base) { in bnx2x_get_common_hwinfo()
11031 bp->flags |= NO_MCP_FLAG; in bnx2x_get_common_hwinfo()
11035 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config); in bnx2x_get_common_hwinfo()
11036 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config); in bnx2x_get_common_hwinfo()
11038 bp->link_params.hw_led_mode = ((bp->common.hw_config & in bnx2x_get_common_hwinfo()
11042 bp->link_params.feature_config_flags = 0; in bnx2x_get_common_hwinfo()
11043 val = SHMEM_RD(bp, dev_info.shared_feature_config.config); in bnx2x_get_common_hwinfo()
11045 bp->link_params.feature_config_flags |= in bnx2x_get_common_hwinfo()
11048 bp->link_params.feature_config_flags &= in bnx2x_get_common_hwinfo()
11051 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8; in bnx2x_get_common_hwinfo()
11052 bp->common.bc_ver = val; in bnx2x_get_common_hwinfo()
11060 bp->link_params.feature_config_flags |= in bnx2x_get_common_hwinfo()
11064 bp->link_params.feature_config_flags |= in bnx2x_get_common_hwinfo()
11067 bp->link_params.feature_config_flags |= in bnx2x_get_common_hwinfo()
11070 bp->link_params.feature_config_flags |= in bnx2x_get_common_hwinfo()
11074 bp->link_params.feature_config_flags |= in bnx2x_get_common_hwinfo()
11078 bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ? in bnx2x_get_common_hwinfo()
11081 bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ? in bnx2x_get_common_hwinfo()
11084 bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ? in bnx2x_get_common_hwinfo()
11087 bp->flags |= (val >= REQ_BC_VER_4_RMMOD_CMD) ? in bnx2x_get_common_hwinfo()
11090 boot_mode = SHMEM_RD(bp, in bnx2x_get_common_hwinfo()
11091 dev_info.port_feature_config[BP_PORT(bp)].mba_config) & in bnx2x_get_common_hwinfo()
11095 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE; in bnx2x_get_common_hwinfo()
11098 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI; in bnx2x_get_common_hwinfo()
11101 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE; in bnx2x_get_common_hwinfo()
11104 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE; in bnx2x_get_common_hwinfo()
11108 pci_read_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_PMC, &pmc); in bnx2x_get_common_hwinfo()
11109 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG; in bnx2x_get_common_hwinfo()
11112 (bp->flags & NO_WOL_FLAG) ? "not " : ""); in bnx2x_get_common_hwinfo()
11114 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num); in bnx2x_get_common_hwinfo()
11115 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]); in bnx2x_get_common_hwinfo()
11116 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]); in bnx2x_get_common_hwinfo()
11117 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]); in bnx2x_get_common_hwinfo()
11119 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n", in bnx2x_get_common_hwinfo()
11126 static int bnx2x_get_igu_cam_info(struct bnx2x *bp) in bnx2x_get_igu_cam_info() argument
11128 int pfid = BP_FUNC(bp); in bnx2x_get_igu_cam_info()
11133 bp->igu_base_sb = 0xff; in bnx2x_get_igu_cam_info()
11134 if (CHIP_INT_MODE_IS_BC(bp)) { in bnx2x_get_igu_cam_info()
11135 int vn = BP_VN(bp); in bnx2x_get_igu_cam_info()
11136 igu_sb_cnt = bp->igu_sb_cnt; in bnx2x_get_igu_cam_info()
11137 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) * in bnx2x_get_igu_cam_info()
11140 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x + in bnx2x_get_igu_cam_info()
11141 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn); in bnx2x_get_igu_cam_info()
11149 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4); in bnx2x_get_igu_cam_info()
11158 bp->igu_dsb_id = igu_sb_id; in bnx2x_get_igu_cam_info()
11160 if (bp->igu_base_sb == 0xff) in bnx2x_get_igu_cam_info()
11161 bp->igu_base_sb = igu_sb_id; in bnx2x_get_igu_cam_info()
11174 bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt); in bnx2x_get_igu_cam_info()
11185 static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg) in bnx2x_link_settings_supported() argument
11187 int cfg_size = 0, idx, port = BP_PORT(bp); in bnx2x_link_settings_supported()
11190 bp->port.supported[0] = 0; in bnx2x_link_settings_supported()
11191 bp->port.supported[1] = 0; in bnx2x_link_settings_supported()
11192 switch (bp->link_params.num_phys) { in bnx2x_link_settings_supported()
11194 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported; in bnx2x_link_settings_supported()
11198 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported; in bnx2x_link_settings_supported()
11202 if (bp->link_params.multi_phy_config & in bnx2x_link_settings_supported()
11204 bp->port.supported[1] = in bnx2x_link_settings_supported()
11205 bp->link_params.phy[EXT_PHY1].supported; in bnx2x_link_settings_supported()
11206 bp->port.supported[0] = in bnx2x_link_settings_supported()
11207 bp->link_params.phy[EXT_PHY2].supported; in bnx2x_link_settings_supported()
11209 bp->port.supported[0] = in bnx2x_link_settings_supported()
11210 bp->link_params.phy[EXT_PHY1].supported; in bnx2x_link_settings_supported()
11211 bp->port.supported[1] = in bnx2x_link_settings_supported()
11212 bp->link_params.phy[EXT_PHY2].supported; in bnx2x_link_settings_supported()
11218 if (!(bp->port.supported[0] || bp->port.supported[1])) { in bnx2x_link_settings_supported()
11220 SHMEM_RD(bp, in bnx2x_link_settings_supported()
11222 SHMEM_RD(bp, in bnx2x_link_settings_supported()
11227 if (CHIP_IS_E3(bp)) in bnx2x_link_settings_supported()
11228 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR); in bnx2x_link_settings_supported()
11232 bp->port.phy_addr = REG_RD( in bnx2x_link_settings_supported()
11233 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10); in bnx2x_link_settings_supported()
11236 bp->port.phy_addr = REG_RD( in bnx2x_link_settings_supported()
11237 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18); in bnx2x_link_settings_supported()
11241 bp->port.link_config[0]); in bnx2x_link_settings_supported()
11245 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr); in bnx2x_link_settings_supported()
11248 if (!(bp->link_params.speed_cap_mask[idx] & in bnx2x_link_settings_supported()
11250 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half; in bnx2x_link_settings_supported()
11252 if (!(bp->link_params.speed_cap_mask[idx] & in bnx2x_link_settings_supported()
11254 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full; in bnx2x_link_settings_supported()
11256 if (!(bp->link_params.speed_cap_mask[idx] & in bnx2x_link_settings_supported()
11258 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half; in bnx2x_link_settings_supported()
11260 if (!(bp->link_params.speed_cap_mask[idx] & in bnx2x_link_settings_supported()
11262 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full; in bnx2x_link_settings_supported()
11264 if (!(bp->link_params.speed_cap_mask[idx] & in bnx2x_link_settings_supported()
11266 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half | in bnx2x_link_settings_supported()
11269 if (!(bp->link_params.speed_cap_mask[idx] & in bnx2x_link_settings_supported()
11271 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full; in bnx2x_link_settings_supported()
11273 if (!(bp->link_params.speed_cap_mask[idx] & in bnx2x_link_settings_supported()
11275 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full; in bnx2x_link_settings_supported()
11277 if (!(bp->link_params.speed_cap_mask[idx] & in bnx2x_link_settings_supported()
11279 bp->port.supported[idx] &= ~SUPPORTED_20000baseKR2_Full; in bnx2x_link_settings_supported()
11282 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0], in bnx2x_link_settings_supported()
11283 bp->port.supported[1]); in bnx2x_link_settings_supported()
11286 static void bnx2x_link_settings_requested(struct bnx2x *bp) in bnx2x_link_settings_requested() argument
11289 bp->port.advertising[0] = 0; in bnx2x_link_settings_requested()
11290 bp->port.advertising[1] = 0; in bnx2x_link_settings_requested()
11291 switch (bp->link_params.num_phys) { in bnx2x_link_settings_requested()
11301 bp->link_params.req_duplex[idx] = DUPLEX_FULL; in bnx2x_link_settings_requested()
11302 link_config = bp->port.link_config[idx]; in bnx2x_link_settings_requested()
11305 if (bp->port.supported[idx] & SUPPORTED_Autoneg) { in bnx2x_link_settings_requested()
11306 bp->link_params.req_line_speed[idx] = in bnx2x_link_settings_requested()
11308 bp->port.advertising[idx] |= in bnx2x_link_settings_requested()
11309 bp->port.supported[idx]; in bnx2x_link_settings_requested()
11310 if (bp->link_params.phy[EXT_PHY1].type == in bnx2x_link_settings_requested()
11312 bp->port.advertising[idx] |= in bnx2x_link_settings_requested()
11317 bp->link_params.req_line_speed[idx] = in bnx2x_link_settings_requested()
11319 bp->port.advertising[idx] |= in bnx2x_link_settings_requested()
11327 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) { in bnx2x_link_settings_requested()
11328 bp->link_params.req_line_speed[idx] = in bnx2x_link_settings_requested()
11330 bp->port.advertising[idx] |= in bnx2x_link_settings_requested()
11336 bp->link_params.speed_cap_mask[idx]); in bnx2x_link_settings_requested()
11342 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) { in bnx2x_link_settings_requested()
11343 bp->link_params.req_line_speed[idx] = in bnx2x_link_settings_requested()
11345 bp->link_params.req_duplex[idx] = in bnx2x_link_settings_requested()
11347 bp->port.advertising[idx] |= in bnx2x_link_settings_requested()
11353 bp->link_params.speed_cap_mask[idx]); in bnx2x_link_settings_requested()
11359 if (bp->port.supported[idx] & in bnx2x_link_settings_requested()
11361 bp->link_params.req_line_speed[idx] = in bnx2x_link_settings_requested()
11363 bp->port.advertising[idx] |= in bnx2x_link_settings_requested()
11369 bp->link_params.speed_cap_mask[idx]); in bnx2x_link_settings_requested()
11375 if (bp->port.supported[idx] & in bnx2x_link_settings_requested()
11377 bp->link_params.req_line_speed[idx] = in bnx2x_link_settings_requested()
11379 bp->link_params.req_duplex[idx] = in bnx2x_link_settings_requested()
11381 bp->port.advertising[idx] |= in bnx2x_link_settings_requested()
11387 bp->link_params.speed_cap_mask[idx]); in bnx2x_link_settings_requested()
11393 if (bp->port.supported[idx] & in bnx2x_link_settings_requested()
11395 bp->link_params.req_line_speed[idx] = in bnx2x_link_settings_requested()
11397 bp->port.advertising[idx] |= in bnx2x_link_settings_requested()
11400 } else if (bp->port.supported[idx] & in bnx2x_link_settings_requested()
11402 bp->link_params.req_line_speed[idx] = in bnx2x_link_settings_requested()
11404 bp->port.advertising[idx] |= in bnx2x_link_settings_requested()
11409 bp->link_params.speed_cap_mask[idx]); in bnx2x_link_settings_requested()
11415 if (bp->port.supported[idx] & in bnx2x_link_settings_requested()
11417 bp->link_params.req_line_speed[idx] = in bnx2x_link_settings_requested()
11419 bp->port.advertising[idx] |= in bnx2x_link_settings_requested()
11425 bp->link_params.speed_cap_mask[idx]); in bnx2x_link_settings_requested()
11431 if (bp->port.supported[idx] & in bnx2x_link_settings_requested()
11433 bp->link_params.req_line_speed[idx] = in bnx2x_link_settings_requested()
11435 bp->port.advertising[idx] |= in bnx2x_link_settings_requested()
11438 } else if (bp->port.supported[idx] & in bnx2x_link_settings_requested()
11440 bp->link_params.req_line_speed[idx] = in bnx2x_link_settings_requested()
11442 bp->port.advertising[idx] |= in bnx2x_link_settings_requested()
11448 bp->link_params.speed_cap_mask[idx]); in bnx2x_link_settings_requested()
11453 bp->link_params.req_line_speed[idx] = SPEED_20000; in bnx2x_link_settings_requested()
11459 bp->link_params.req_line_speed[idx] = in bnx2x_link_settings_requested()
11461 bp->port.advertising[idx] = in bnx2x_link_settings_requested()
11462 bp->port.supported[idx]; in bnx2x_link_settings_requested()
11466 bp->link_params.req_flow_ctrl[idx] = (link_config & in bnx2x_link_settings_requested()
11468 if (bp->link_params.req_flow_ctrl[idx] == in bnx2x_link_settings_requested()
11470 if (!(bp->port.supported[idx] & SUPPORTED_Autoneg)) in bnx2x_link_settings_requested()
11471 bp->link_params.req_flow_ctrl[idx] = in bnx2x_link_settings_requested()
11474 bnx2x_set_requested_fc(bp); in bnx2x_link_settings_requested()
11478 bp->link_params.req_line_speed[idx], in bnx2x_link_settings_requested()
11479 bp->link_params.req_duplex[idx], in bnx2x_link_settings_requested()
11480 bp->link_params.req_flow_ctrl[idx], in bnx2x_link_settings_requested()
11481 bp->port.advertising[idx]); in bnx2x_link_settings_requested()
11493 static void bnx2x_get_port_hwinfo(struct bnx2x *bp) in bnx2x_get_port_hwinfo() argument
11495 int port = BP_PORT(bp); in bnx2x_get_port_hwinfo()
11499 bp->link_params.bp = bp; in bnx2x_get_port_hwinfo()
11500 bp->link_params.port = port; in bnx2x_get_port_hwinfo()
11502 bp->link_params.lane_config = in bnx2x_get_port_hwinfo()
11503 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config); in bnx2x_get_port_hwinfo()
11505 bp->link_params.speed_cap_mask[0] = in bnx2x_get_port_hwinfo()
11506 SHMEM_RD(bp, in bnx2x_get_port_hwinfo()
11509 bp->link_params.speed_cap_mask[1] = in bnx2x_get_port_hwinfo()
11510 SHMEM_RD(bp, in bnx2x_get_port_hwinfo()
11513 bp->port.link_config[0] = in bnx2x_get_port_hwinfo()
11514 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config); in bnx2x_get_port_hwinfo()
11516 bp->port.link_config[1] = in bnx2x_get_port_hwinfo()
11517 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2); in bnx2x_get_port_hwinfo()
11519 bp->link_params.multi_phy_config = in bnx2x_get_port_hwinfo()
11520 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config); in bnx2x_get_port_hwinfo()
11524 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config); in bnx2x_get_port_hwinfo()
11525 bp->wol = (!(bp->flags & NO_WOL_FLAG) && in bnx2x_get_port_hwinfo()
11529 PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp)) in bnx2x_get_port_hwinfo()
11530 bp->flags |= NO_ISCSI_FLAG; in bnx2x_get_port_hwinfo()
11532 PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp))) in bnx2x_get_port_hwinfo()
11533 bp->flags |= NO_FCOE_FLAG; in bnx2x_get_port_hwinfo()
11536 bp->link_params.lane_config, in bnx2x_get_port_hwinfo()
11537 bp->link_params.speed_cap_mask[0], in bnx2x_get_port_hwinfo()
11538 bp->port.link_config[0]); in bnx2x_get_port_hwinfo()
11540 bp->link_params.switch_cfg = (bp->port.link_config[0] & in bnx2x_get_port_hwinfo()
11542 bnx2x_phy_probe(&bp->link_params); in bnx2x_get_port_hwinfo()
11543 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg); in bnx2x_get_port_hwinfo()
11545 bnx2x_link_settings_requested(bp); in bnx2x_get_port_hwinfo()
11552 SHMEM_RD(bp, in bnx2x_get_port_hwinfo()
11556 bp->mdio.prtad = bp->port.phy_addr; in bnx2x_get_port_hwinfo()
11560 bp->mdio.prtad = in bnx2x_get_port_hwinfo()
11564 eee_mode = (((SHMEM_RD(bp, dev_info. in bnx2x_get_port_hwinfo()
11569 bp->link_params.eee_mode = EEE_MODE_ADV_LPI | in bnx2x_get_port_hwinfo()
11573 bp->link_params.eee_mode = 0; in bnx2x_get_port_hwinfo()
11577 void bnx2x_get_iscsi_info(struct bnx2x *bp) in bnx2x_get_iscsi_info() argument
11580 int port = BP_PORT(bp); in bnx2x_get_iscsi_info()
11581 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, in bnx2x_get_iscsi_info()
11584 if (!CNIC_SUPPORT(bp)) { in bnx2x_get_iscsi_info()
11585 bp->flags |= no_flags; in bnx2x_get_iscsi_info()
11590 bp->cnic_eth_dev.max_iscsi_conn = in bnx2x_get_iscsi_info()
11595 bp->cnic_eth_dev.max_iscsi_conn); in bnx2x_get_iscsi_info()
11601 if (!bp->cnic_eth_dev.max_iscsi_conn) in bnx2x_get_iscsi_info()
11602 bp->flags |= no_flags; in bnx2x_get_iscsi_info()
11605 static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func) in bnx2x_get_ext_wwn_info() argument
11608 bp->cnic_eth_dev.fcoe_wwn_port_name_hi = in bnx2x_get_ext_wwn_info()
11609 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper); in bnx2x_get_ext_wwn_info()
11610 bp->cnic_eth_dev.fcoe_wwn_port_name_lo = in bnx2x_get_ext_wwn_info()
11611 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower); in bnx2x_get_ext_wwn_info()
11614 bp->cnic_eth_dev.fcoe_wwn_node_name_hi = in bnx2x_get_ext_wwn_info()
11615 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper); in bnx2x_get_ext_wwn_info()
11616 bp->cnic_eth_dev.fcoe_wwn_node_name_lo = in bnx2x_get_ext_wwn_info()
11617 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower); in bnx2x_get_ext_wwn_info()
11620 static int bnx2x_shared_fcoe_funcs(struct bnx2x *bp) in bnx2x_shared_fcoe_funcs() argument
11624 if (IS_MF(bp)) { in bnx2x_shared_fcoe_funcs()
11628 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX * 2; fid += 2) { in bnx2x_shared_fcoe_funcs()
11629 if (IS_MF_SD(bp)) { in bnx2x_shared_fcoe_funcs()
11630 u32 cfg = MF_CFG_RD(bp, in bnx2x_shared_fcoe_funcs()
11638 u32 cfg = MF_CFG_RD(bp, in bnx2x_shared_fcoe_funcs()
11648 int port, port_cnt = CHIP_MODE_IS_4_PORT(bp) ? 2 : 1; in bnx2x_shared_fcoe_funcs()
11651 u32 lic = SHMEM_RD(bp, in bnx2x_shared_fcoe_funcs()
11662 static void bnx2x_get_fcoe_info(struct bnx2x *bp) in bnx2x_get_fcoe_info() argument
11664 int port = BP_PORT(bp); in bnx2x_get_fcoe_info()
11665 int func = BP_ABS_FUNC(bp); in bnx2x_get_fcoe_info()
11666 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, in bnx2x_get_fcoe_info()
11668 u8 num_fcoe_func = bnx2x_shared_fcoe_funcs(bp); in bnx2x_get_fcoe_info()
11670 if (!CNIC_SUPPORT(bp)) { in bnx2x_get_fcoe_info()
11671 bp->flags |= NO_FCOE_FLAG; in bnx2x_get_fcoe_info()
11676 bp->cnic_eth_dev.max_fcoe_conn = in bnx2x_get_fcoe_info()
11681 bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE; in bnx2x_get_fcoe_info()
11685 bp->cnic_eth_dev.max_fcoe_exchanges /= num_fcoe_func; in bnx2x_get_fcoe_info()
11688 if (!IS_MF(bp)) { in bnx2x_get_fcoe_info()
11690 bp->cnic_eth_dev.fcoe_wwn_port_name_hi = in bnx2x_get_fcoe_info()
11691 SHMEM_RD(bp, in bnx2x_get_fcoe_info()
11694 bp->cnic_eth_dev.fcoe_wwn_port_name_lo = in bnx2x_get_fcoe_info()
11695 SHMEM_RD(bp, in bnx2x_get_fcoe_info()
11700 bp->cnic_eth_dev.fcoe_wwn_node_name_hi = in bnx2x_get_fcoe_info()
11701 SHMEM_RD(bp, in bnx2x_get_fcoe_info()
11704 bp->cnic_eth_dev.fcoe_wwn_node_name_lo = in bnx2x_get_fcoe_info()
11705 SHMEM_RD(bp, in bnx2x_get_fcoe_info()
11708 } else if (!IS_MF_SD(bp)) { in bnx2x_get_fcoe_info()
11712 if (BNX2X_HAS_MF_EXT_PROTOCOL_FCOE(bp)) in bnx2x_get_fcoe_info()
11713 bnx2x_get_ext_wwn_info(bp, func); in bnx2x_get_fcoe_info()
11715 if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp)) in bnx2x_get_fcoe_info()
11716 bnx2x_get_ext_wwn_info(bp, func); in bnx2x_get_fcoe_info()
11719 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn); in bnx2x_get_fcoe_info()
11725 if (!bp->cnic_eth_dev.max_fcoe_conn) { in bnx2x_get_fcoe_info()
11726 bp->flags |= NO_FCOE_FLAG; in bnx2x_get_fcoe_info()
11727 eth_zero_addr(bp->fip_mac); in bnx2x_get_fcoe_info()
11731 static void bnx2x_get_cnic_info(struct bnx2x *bp) in bnx2x_get_cnic_info() argument
11738 bnx2x_get_iscsi_info(bp); in bnx2x_get_cnic_info()
11739 bnx2x_get_fcoe_info(bp); in bnx2x_get_cnic_info()
11742 static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp) in bnx2x_get_cnic_mac_hwinfo() argument
11745 int func = BP_ABS_FUNC(bp); in bnx2x_get_cnic_mac_hwinfo()
11746 int port = BP_PORT(bp); in bnx2x_get_cnic_mac_hwinfo()
11747 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac; in bnx2x_get_cnic_mac_hwinfo()
11748 u8 *fip_mac = bp->fip_mac; in bnx2x_get_cnic_mac_hwinfo()
11750 if (IS_MF(bp)) { in bnx2x_get_cnic_mac_hwinfo()
11756 if (!IS_MF_SD(bp)) { in bnx2x_get_cnic_mac_hwinfo()
11757 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg); in bnx2x_get_cnic_mac_hwinfo()
11759 val2 = MF_CFG_RD(bp, func_ext_config[func]. in bnx2x_get_cnic_mac_hwinfo()
11761 val = MF_CFG_RD(bp, func_ext_config[func]. in bnx2x_get_cnic_mac_hwinfo()
11767 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG; in bnx2x_get_cnic_mac_hwinfo()
11771 val2 = MF_CFG_RD(bp, func_ext_config[func]. in bnx2x_get_cnic_mac_hwinfo()
11773 val = MF_CFG_RD(bp, func_ext_config[func]. in bnx2x_get_cnic_mac_hwinfo()
11779 bp->flags |= NO_FCOE_FLAG; in bnx2x_get_cnic_mac_hwinfo()
11782 bp->mf_ext_config = cfg; in bnx2x_get_cnic_mac_hwinfo()
11785 if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) { in bnx2x_get_cnic_mac_hwinfo()
11787 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN); in bnx2x_get_cnic_mac_hwinfo()
11792 } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) { in bnx2x_get_cnic_mac_hwinfo()
11794 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN); in bnx2x_get_cnic_mac_hwinfo()
11805 if (IS_MF_FCOE_AFEX(bp)) in bnx2x_get_cnic_mac_hwinfo()
11806 eth_hw_addr_set(bp->dev, fip_mac); in bnx2x_get_cnic_mac_hwinfo()
11808 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. in bnx2x_get_cnic_mac_hwinfo()
11810 val = SHMEM_RD(bp, dev_info.port_hw_config[port]. in bnx2x_get_cnic_mac_hwinfo()
11814 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. in bnx2x_get_cnic_mac_hwinfo()
11816 val = SHMEM_RD(bp, dev_info.port_hw_config[port]. in bnx2x_get_cnic_mac_hwinfo()
11823 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG; in bnx2x_get_cnic_mac_hwinfo()
11829 bp->flags |= NO_FCOE_FLAG; in bnx2x_get_cnic_mac_hwinfo()
11830 eth_zero_addr(bp->fip_mac); in bnx2x_get_cnic_mac_hwinfo()
11834 static void bnx2x_get_mac_hwinfo(struct bnx2x *bp) in bnx2x_get_mac_hwinfo() argument
11837 int func = BP_ABS_FUNC(bp); in bnx2x_get_mac_hwinfo()
11838 int port = BP_PORT(bp); in bnx2x_get_mac_hwinfo()
11842 eth_hw_addr_set(bp->dev, addr); in bnx2x_get_mac_hwinfo()
11844 if (BP_NOMCP(bp)) { in bnx2x_get_mac_hwinfo()
11846 eth_hw_addr_random(bp->dev); in bnx2x_get_mac_hwinfo()
11847 } else if (IS_MF(bp)) { in bnx2x_get_mac_hwinfo()
11848 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper); in bnx2x_get_mac_hwinfo()
11849 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower); in bnx2x_get_mac_hwinfo()
11853 eth_hw_addr_set(bp->dev, addr); in bnx2x_get_mac_hwinfo()
11856 if (CNIC_SUPPORT(bp)) in bnx2x_get_mac_hwinfo()
11857 bnx2x_get_cnic_mac_hwinfo(bp); in bnx2x_get_mac_hwinfo()
11860 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper); in bnx2x_get_mac_hwinfo()
11861 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower); in bnx2x_get_mac_hwinfo()
11863 eth_hw_addr_set(bp->dev, addr); in bnx2x_get_mac_hwinfo()
11865 if (CNIC_SUPPORT(bp)) in bnx2x_get_mac_hwinfo()
11866 bnx2x_get_cnic_mac_hwinfo(bp); in bnx2x_get_mac_hwinfo()
11869 if (!BP_NOMCP(bp)) { in bnx2x_get_mac_hwinfo()
11871 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper); in bnx2x_get_mac_hwinfo()
11872 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower); in bnx2x_get_mac_hwinfo()
11873 bnx2x_set_mac_buf(bp->phys_port_id, val, val2); in bnx2x_get_mac_hwinfo()
11874 bp->flags |= HAS_PHYS_PORT_ID; in bnx2x_get_mac_hwinfo()
11877 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN); in bnx2x_get_mac_hwinfo()
11879 if (!is_valid_ether_addr(bp->dev->dev_addr)) in bnx2x_get_mac_hwinfo()
11880 dev_err(&bp->pdev->dev, in bnx2x_get_mac_hwinfo()
11883 bp->dev->dev_addr); in bnx2x_get_mac_hwinfo()
11886 static bool bnx2x_get_dropless_info(struct bnx2x *bp) in bnx2x_get_dropless_info() argument
11891 if (IS_VF(bp)) in bnx2x_get_dropless_info()
11894 if (IS_MF(bp) && !CHIP_IS_E1x(bp)) { in bnx2x_get_dropless_info()
11896 tmp = BP_ABS_FUNC(bp); in bnx2x_get_dropless_info()
11897 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg); in bnx2x_get_dropless_info()
11901 tmp = BP_PORT(bp); in bnx2x_get_dropless_info()
11902 cfg = SHMEM_RD(bp, in bnx2x_get_dropless_info()
11909 static void validate_set_si_mode(struct bnx2x *bp) in validate_set_si_mode() argument
11911 u8 func = BP_ABS_FUNC(bp); in validate_set_si_mode()
11914 val = MF_CFG_RD(bp, func_mf_config[func].mac_upper); in validate_set_si_mode()
11918 bp->mf_mode = MULTI_FUNCTION_SI; in validate_set_si_mode()
11919 bp->mf_config[BP_VN(bp)] = in validate_set_si_mode()
11920 MF_CFG_RD(bp, func_mf_config[func].config); in validate_set_si_mode()
11925 static int bnx2x_get_hwinfo(struct bnx2x *bp) in bnx2x_get_hwinfo() argument
11927 int /*abs*/func = BP_ABS_FUNC(bp); in bnx2x_get_hwinfo()
11933 if (REG_RD(bp, MISC_REG_CHIP_NUM) == 0xffffffff) { in bnx2x_get_hwinfo()
11934 dev_err(&bp->pdev->dev, in bnx2x_get_hwinfo()
11939 bnx2x_get_common_hwinfo(bp); in bnx2x_get_hwinfo()
11944 if (CHIP_IS_E1x(bp)) { in bnx2x_get_hwinfo()
11945 bp->common.int_block = INT_BLOCK_HC; in bnx2x_get_hwinfo()
11947 bp->igu_dsb_id = DEF_SB_IGU_ID; in bnx2x_get_hwinfo()
11948 bp->igu_base_sb = 0; in bnx2x_get_hwinfo()
11950 bp->common.int_block = INT_BLOCK_IGU; in bnx2x_get_hwinfo()
11953 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); in bnx2x_get_hwinfo()
11955 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); in bnx2x_get_hwinfo()
11963 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val); in bnx2x_get_hwinfo()
11964 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f); in bnx2x_get_hwinfo()
11966 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) { in bnx2x_get_hwinfo()
11971 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) { in bnx2x_get_hwinfo()
11972 dev_err(&bp->pdev->dev, in bnx2x_get_hwinfo()
11974 bnx2x_release_hw_lock(bp, in bnx2x_get_hwinfo()
11982 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP; in bnx2x_get_hwinfo()
11986 rc = bnx2x_get_igu_cam_info(bp); in bnx2x_get_hwinfo()
11987 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); in bnx2x_get_hwinfo()
11997 if (CHIP_IS_E1x(bp)) in bnx2x_get_hwinfo()
11998 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp); in bnx2x_get_hwinfo()
12004 bp->base_fw_ndsb = bp->igu_base_sb; in bnx2x_get_hwinfo()
12007 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb, in bnx2x_get_hwinfo()
12008 bp->igu_sb_cnt, bp->base_fw_ndsb); in bnx2x_get_hwinfo()
12013 bp->mf_ov = 0; in bnx2x_get_hwinfo()
12014 bp->mf_mode = 0; in bnx2x_get_hwinfo()
12015 bp->mf_sub_mode = 0; in bnx2x_get_hwinfo()
12016 vn = BP_VN(bp); in bnx2x_get_hwinfo()
12018 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) { in bnx2x_get_hwinfo()
12020 bp->common.shmem2_base, SHMEM2_RD(bp, size), in bnx2x_get_hwinfo()
12023 if (SHMEM2_HAS(bp, mf_cfg_addr)) in bnx2x_get_hwinfo()
12024 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr); in bnx2x_get_hwinfo()
12026 bp->common.mf_cfg_base = bp->common.shmem_base + in bnx2x_get_hwinfo()
12037 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { in bnx2x_get_hwinfo()
12039 val = SHMEM_RD(bp, in bnx2x_get_hwinfo()
12045 validate_set_si_mode(bp); in bnx2x_get_hwinfo()
12048 if ((!CHIP_IS_E1x(bp)) && in bnx2x_get_hwinfo()
12049 (MF_CFG_RD(bp, func_mf_config[func]. in bnx2x_get_hwinfo()
12051 (SHMEM2_HAS(bp, in bnx2x_get_hwinfo()
12053 bp->mf_mode = MULTI_FUNCTION_AFEX; in bnx2x_get_hwinfo()
12054 bp->mf_config[vn] = MF_CFG_RD(bp, in bnx2x_get_hwinfo()
12062 val = MF_CFG_RD(bp, in bnx2x_get_hwinfo()
12067 bp->mf_mode = MULTI_FUNCTION_SD; in bnx2x_get_hwinfo()
12068 bp->mf_config[vn] = MF_CFG_RD(bp, in bnx2x_get_hwinfo()
12074 bp->mf_mode = MULTI_FUNCTION_SD; in bnx2x_get_hwinfo()
12075 bp->mf_sub_mode = SUB_MF_MODE_BD; in bnx2x_get_hwinfo()
12076 bp->mf_config[vn] = in bnx2x_get_hwinfo()
12077 MF_CFG_RD(bp, in bnx2x_get_hwinfo()
12080 if (SHMEM2_HAS(bp, mtu_size)) { in bnx2x_get_hwinfo()
12081 int mtu_idx = BP_FW_MB_IDX(bp); in bnx2x_get_hwinfo()
12085 mtu = SHMEM2_RD(bp, mtu_size[mtu_idx]); in bnx2x_get_hwinfo()
12094 bp->dev->mtu = mtu_size; in bnx2x_get_hwinfo()
12098 bp->mf_mode = MULTI_FUNCTION_SD; in bnx2x_get_hwinfo()
12099 bp->mf_sub_mode = SUB_MF_MODE_UFP; in bnx2x_get_hwinfo()
12100 bp->mf_config[vn] = in bnx2x_get_hwinfo()
12101 MF_CFG_RD(bp, in bnx2x_get_hwinfo()
12105 bp->mf_config[vn] = 0; in bnx2x_get_hwinfo()
12108 val2 = SHMEM_RD(bp, in bnx2x_get_hwinfo()
12113 validate_set_si_mode(bp); in bnx2x_get_hwinfo()
12114 bp->mf_sub_mode = in bnx2x_get_hwinfo()
12119 bp->mf_config[vn] = 0; in bnx2x_get_hwinfo()
12126 bp->mf_config[vn] = 0; in bnx2x_get_hwinfo()
12132 IS_MF(bp) ? "multi" : "single"); in bnx2x_get_hwinfo()
12134 switch (bp->mf_mode) { in bnx2x_get_hwinfo()
12136 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & in bnx2x_get_hwinfo()
12139 bp->mf_ov = val; in bnx2x_get_hwinfo()
12140 bp->path_has_ovlan = true; in bnx2x_get_hwinfo()
12143 func, bp->mf_ov, bp->mf_ov); in bnx2x_get_hwinfo()
12144 } else if ((bp->mf_sub_mode == SUB_MF_MODE_UFP) || in bnx2x_get_hwinfo()
12145 (bp->mf_sub_mode == SUB_MF_MODE_BD)) { in bnx2x_get_hwinfo()
12146 dev_err(&bp->pdev->dev, in bnx2x_get_hwinfo()
12149 bp->path_has_ovlan = true; in bnx2x_get_hwinfo()
12151 dev_err(&bp->pdev->dev, in bnx2x_get_hwinfo()
12166 dev_err(&bp->pdev->dev, in bnx2x_get_hwinfo()
12179 if (CHIP_MODE_IS_4_PORT(bp) && in bnx2x_get_hwinfo()
12180 !bp->path_has_ovlan && in bnx2x_get_hwinfo()
12181 !IS_MF(bp) && in bnx2x_get_hwinfo()
12182 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { in bnx2x_get_hwinfo()
12183 u8 other_port = !BP_PORT(bp); in bnx2x_get_hwinfo()
12184 u8 other_func = BP_PATH(bp) + 2*other_port; in bnx2x_get_hwinfo()
12185 val = MF_CFG_RD(bp, in bnx2x_get_hwinfo()
12188 bp->path_has_ovlan = true; in bnx2x_get_hwinfo()
12193 if (CHIP_IS_E1H(bp) && IS_MF(bp)) in bnx2x_get_hwinfo()
12194 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt, E1H_MAX_MF_SB_COUNT); in bnx2x_get_hwinfo()
12197 bnx2x_get_port_hwinfo(bp); in bnx2x_get_hwinfo()
12200 bnx2x_get_mac_hwinfo(bp); in bnx2x_get_hwinfo()
12202 bnx2x_get_cnic_info(bp); in bnx2x_get_hwinfo()
12207 static void bnx2x_read_fwinfo(struct bnx2x *bp) in bnx2x_read_fwinfo() argument
12214 memset(bp->fw_ver, 0, sizeof(bp->fw_ver)); in bnx2x_read_fwinfo()
12216 vpd_data = pci_vpd_alloc(bp->pdev, &vpd_len); in bnx2x_read_fwinfo()
12231 if (rodi >= 0 && kw_len < sizeof(bp->fw_ver)) { in bnx2x_read_fwinfo()
12232 memcpy(bp->fw_ver, &vpd_data[rodi], kw_len); in bnx2x_read_fwinfo()
12233 bp->fw_ver[kw_len] = ' '; in bnx2x_read_fwinfo()
12240 static void bnx2x_set_modes_bitmap(struct bnx2x *bp) in bnx2x_set_modes_bitmap() argument
12244 if (CHIP_REV_IS_FPGA(bp)) in bnx2x_set_modes_bitmap()
12246 else if (CHIP_REV_IS_EMUL(bp)) in bnx2x_set_modes_bitmap()
12251 if (CHIP_MODE_IS_4_PORT(bp)) in bnx2x_set_modes_bitmap()
12256 if (CHIP_IS_E2(bp)) in bnx2x_set_modes_bitmap()
12258 else if (CHIP_IS_E3(bp)) { in bnx2x_set_modes_bitmap()
12260 if (CHIP_REV(bp) == CHIP_REV_Ax) in bnx2x_set_modes_bitmap()
12266 if (IS_MF(bp)) { in bnx2x_set_modes_bitmap()
12268 switch (bp->mf_mode) { in bnx2x_set_modes_bitmap()
12287 INIT_MODE_FLAGS(bp) = flags; in bnx2x_set_modes_bitmap()
12290 static int bnx2x_init_bp(struct bnx2x *bp) in bnx2x_init_bp() argument
12295 mutex_init(&bp->port.phy_mutex); in bnx2x_init_bp()
12296 mutex_init(&bp->fw_mb_mutex); in bnx2x_init_bp()
12297 mutex_init(&bp->drv_info_mutex); in bnx2x_init_bp()
12298 sema_init(&bp->stats_lock, 1); in bnx2x_init_bp()
12299 bp->drv_info_mng_owner = false; in bnx2x_init_bp()
12300 INIT_LIST_HEAD(&bp->vlan_reg); in bnx2x_init_bp()
12302 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task); in bnx2x_init_bp()
12303 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task); in bnx2x_init_bp()
12304 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task); in bnx2x_init_bp()
12305 INIT_DELAYED_WORK(&bp->iov_task, bnx2x_iov_task); in bnx2x_init_bp()
12306 if (IS_PF(bp)) { in bnx2x_init_bp()
12307 rc = bnx2x_get_hwinfo(bp); in bnx2x_init_bp()
12313 eth_hw_addr_set(bp->dev, zero_addr); in bnx2x_init_bp()
12316 bnx2x_set_modes_bitmap(bp); in bnx2x_init_bp()
12318 rc = bnx2x_alloc_mem_bp(bp); in bnx2x_init_bp()
12322 bnx2x_read_fwinfo(bp); in bnx2x_init_bp()
12324 func = BP_FUNC(bp); in bnx2x_init_bp()
12327 if (IS_PF(bp) && !BP_NOMCP(bp)) { in bnx2x_init_bp()
12329 bp->fw_seq = in bnx2x_init_bp()
12330 SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & in bnx2x_init_bp()
12332 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq); in bnx2x_init_bp()
12334 rc = bnx2x_prev_unload(bp); in bnx2x_init_bp()
12336 bnx2x_free_mem_bp(bp); in bnx2x_init_bp()
12341 if (CHIP_REV_IS_FPGA(bp)) in bnx2x_init_bp()
12342 dev_err(&bp->pdev->dev, "FPGA detected\n"); in bnx2x_init_bp()
12344 if (BP_NOMCP(bp) && (func == 0)) in bnx2x_init_bp()
12345 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n"); in bnx2x_init_bp()
12347 bp->disable_tpa = disable_tpa; in bnx2x_init_bp()
12348 bp->disable_tpa |= !!IS_MF_STORAGE_ONLY(bp); in bnx2x_init_bp()
12350 bp->disable_tpa |= is_kdump_kernel(); in bnx2x_init_bp()
12353 if (bp->disable_tpa) { in bnx2x_init_bp()
12354 bp->dev->hw_features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW); in bnx2x_init_bp()
12355 bp->dev->features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW); in bnx2x_init_bp()
12358 if (CHIP_IS_E1(bp)) in bnx2x_init_bp()
12359 bp->dropless_fc = false; in bnx2x_init_bp()
12361 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp); in bnx2x_init_bp()
12363 bp->mrrs = mrrs; in bnx2x_init_bp()
12365 bp->tx_ring_size = IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL; in bnx2x_init_bp()
12366 if (IS_VF(bp)) in bnx2x_init_bp()
12367 bp->rx_ring_size = MAX_RX_AVAIL; in bnx2x_init_bp()
12370 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR; in bnx2x_init_bp()
12371 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR; in bnx2x_init_bp()
12373 bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ; in bnx2x_init_bp()
12375 timer_setup(&bp->timer, bnx2x_timer, 0); in bnx2x_init_bp()
12376 bp->timer.expires = jiffies + bp->current_interval; in bnx2x_init_bp()
12378 if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) && in bnx2x_init_bp()
12379 SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) && in bnx2x_init_bp()
12380 SHMEM2_HAS(bp, dcbx_en) && in bnx2x_init_bp()
12381 SHMEM2_RD(bp, dcbx_lldp_params_offset) && in bnx2x_init_bp()
12382 SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset) && in bnx2x_init_bp()
12383 SHMEM2_RD(bp, dcbx_en[BP_PORT(bp)])) { in bnx2x_init_bp()
12384 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON); in bnx2x_init_bp()
12385 bnx2x_dcbx_init_params(bp); in bnx2x_init_bp()
12387 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF); in bnx2x_init_bp()
12390 if (CHIP_IS_E1x(bp)) in bnx2x_init_bp()
12391 bp->cnic_base_cl_id = FP_SB_MAX_E1x; in bnx2x_init_bp()
12393 bp->cnic_base_cl_id = FP_SB_MAX_E2; in bnx2x_init_bp()
12396 if (IS_VF(bp)) in bnx2x_init_bp()
12397 bp->max_cos = 1; in bnx2x_init_bp()
12398 else if (CHIP_IS_E1x(bp)) in bnx2x_init_bp()
12399 bp->max_cos = BNX2X_MULTI_TX_COS_E1X; in bnx2x_init_bp()
12400 else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp)) in bnx2x_init_bp()
12401 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0; in bnx2x_init_bp()
12402 else if (CHIP_IS_E3B0(bp)) in bnx2x_init_bp()
12403 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0; in bnx2x_init_bp()
12406 CHIP_NUM(bp), CHIP_REV(bp)); in bnx2x_init_bp()
12407 BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos); in bnx2x_init_bp()
12413 if (IS_VF(bp)) in bnx2x_init_bp()
12414 bp->min_msix_vec_cnt = 1; in bnx2x_init_bp()
12415 else if (CNIC_SUPPORT(bp)) in bnx2x_init_bp()
12416 bp->min_msix_vec_cnt = 3; in bnx2x_init_bp()
12418 bp->min_msix_vec_cnt = 2; in bnx2x_init_bp()
12419 BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt); in bnx2x_init_bp()
12421 bp->dump_preset_idx = 1; in bnx2x_init_bp()
12437 struct bnx2x *bp = netdev_priv(dev); in bnx2x_open() local
12440 bp->stats_init = true; in bnx2x_open()
12444 bnx2x_set_power_state(bp, PCI_D0); in bnx2x_open()
12452 if (IS_PF(bp)) { in bnx2x_open()
12453 int other_engine = BP_PATH(bp) ? 0 : 1; in bnx2x_open()
12457 other_load_status = bnx2x_get_load_status(bp, other_engine); in bnx2x_open()
12458 load_status = bnx2x_get_load_status(bp, BP_PATH(bp)); in bnx2x_open()
12459 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) || in bnx2x_open()
12460 bnx2x_chk_parity_attn(bp, &global, true)) { in bnx2x_open()
12468 bnx2x_set_reset_global(bp); in bnx2x_open()
12477 bnx2x_trylock_leader_lock(bp) && in bnx2x_open()
12478 !bnx2x_leader_reset(bp)) { in bnx2x_open()
12479 netdev_info(bp->dev, in bnx2x_open()
12485 bnx2x_set_power_state(bp, PCI_D3hot); in bnx2x_open()
12486 bp->recovery_state = BNX2X_RECOVERY_FAILED; in bnx2x_open()
12496 bp->recovery_state = BNX2X_RECOVERY_DONE; in bnx2x_open()
12497 rc = bnx2x_nic_load(bp, LOAD_OPEN); in bnx2x_open()
12507 struct bnx2x *bp = netdev_priv(dev); in bnx2x_close() local
12510 bnx2x_nic_unload(bp, UNLOAD_CLOSE, false); in bnx2x_close()
12538 static int bnx2x_init_mcast_macs_list(struct bnx2x *bp, in bnx2x_init_mcast_macs_list() argument
12545 int mc_count = netdev_mc_count(bp->dev); in bnx2x_init_mcast_macs_list()
12549 netdev_for_each_mc_addr(ha, bp->dev) { in bnx2x_init_mcast_macs_list()
12580 static int bnx2x_set_uc_list(struct bnx2x *bp) in bnx2x_set_uc_list() argument
12583 struct net_device *dev = bp->dev; in bnx2x_set_uc_list()
12585 struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj; in bnx2x_set_uc_list()
12589 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false); in bnx2x_set_uc_list()
12596 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true, in bnx2x_set_uc_list()
12614 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */, in bnx2x_set_uc_list()
12618 static int bnx2x_set_mc_list_e1x(struct bnx2x *bp) in bnx2x_set_mc_list_e1x() argument
12621 struct net_device *dev = bp->dev; in bnx2x_set_mc_list_e1x()
12625 rparam.mcast_obj = &bp->mcast_obj; in bnx2x_set_mc_list_e1x()
12628 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); in bnx2x_set_mc_list_e1x()
12636 rc = bnx2x_init_mcast_macs_list(bp, &rparam, &mcast_group_list); in bnx2x_set_mc_list_e1x()
12641 rc = bnx2x_config_mcast(bp, &rparam, in bnx2x_set_mc_list_e1x()
12653 static int bnx2x_set_mc_list(struct bnx2x *bp) in bnx2x_set_mc_list() argument
12657 struct net_device *dev = bp->dev; in bnx2x_set_mc_list()
12661 if (CHIP_IS_E1x(bp)) in bnx2x_set_mc_list()
12662 return bnx2x_set_mc_list_e1x(bp); in bnx2x_set_mc_list()
12664 rparam.mcast_obj = &bp->mcast_obj; in bnx2x_set_mc_list()
12667 rc = bnx2x_init_mcast_macs_list(bp, &rparam, &mcast_group_list); in bnx2x_set_mc_list()
12672 rc = bnx2x_config_mcast(bp, &rparam, in bnx2x_set_mc_list()
12681 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); in bnx2x_set_mc_list()
12693 struct bnx2x *bp = netdev_priv(dev); in bnx2x_set_rx_mode() local
12695 if (bp->state != BNX2X_STATE_OPEN) { in bnx2x_set_rx_mode()
12696 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state); in bnx2x_set_rx_mode()
12700 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_RX_MODE, in bnx2x_set_rx_mode()
12705 void bnx2x_set_rx_mode_inner(struct bnx2x *bp) in bnx2x_set_rx_mode_inner() argument
12709 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags); in bnx2x_set_rx_mode_inner()
12711 netif_addr_lock_bh(bp->dev); in bnx2x_set_rx_mode_inner()
12713 if (bp->dev->flags & IFF_PROMISC) { in bnx2x_set_rx_mode_inner()
12715 } else if ((bp->dev->flags & IFF_ALLMULTI) || in bnx2x_set_rx_mode_inner()
12716 ((netdev_mc_count(bp->dev) > BNX2X_MAX_MULTICAST) && in bnx2x_set_rx_mode_inner()
12717 CHIP_IS_E1(bp))) { in bnx2x_set_rx_mode_inner()
12720 if (IS_PF(bp)) { in bnx2x_set_rx_mode_inner()
12722 if (bnx2x_set_mc_list(bp) < 0) in bnx2x_set_rx_mode_inner()
12726 netif_addr_unlock_bh(bp->dev); in bnx2x_set_rx_mode_inner()
12727 if (bnx2x_set_uc_list(bp) < 0) in bnx2x_set_rx_mode_inner()
12729 netif_addr_lock_bh(bp->dev); in bnx2x_set_rx_mode_inner()
12734 bnx2x_schedule_sp_rtnl(bp, in bnx2x_set_rx_mode_inner()
12739 bp->rx_mode = rx_mode; in bnx2x_set_rx_mode_inner()
12741 if (IS_MF_ISCSI_ONLY(bp)) in bnx2x_set_rx_mode_inner()
12742 bp->rx_mode = BNX2X_RX_MODE_NONE; in bnx2x_set_rx_mode_inner()
12745 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) { in bnx2x_set_rx_mode_inner()
12746 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); in bnx2x_set_rx_mode_inner()
12747 netif_addr_unlock_bh(bp->dev); in bnx2x_set_rx_mode_inner()
12751 if (IS_PF(bp)) { in bnx2x_set_rx_mode_inner()
12752 bnx2x_set_storm_rx_mode(bp); in bnx2x_set_rx_mode_inner()
12753 netif_addr_unlock_bh(bp->dev); in bnx2x_set_rx_mode_inner()
12759 netif_addr_unlock_bh(bp->dev); in bnx2x_set_rx_mode_inner()
12760 bnx2x_vfpf_storm_rx_mode(bp); in bnx2x_set_rx_mode_inner()
12768 struct bnx2x *bp = netdev_priv(netdev); in bnx2x_mdio_read() local
12778 bnx2x_acquire_phy_lock(bp); in bnx2x_mdio_read()
12779 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value); in bnx2x_mdio_read()
12780 bnx2x_release_phy_lock(bp); in bnx2x_mdio_read()
12792 struct bnx2x *bp = netdev_priv(netdev); in bnx2x_mdio_write() local
12802 bnx2x_acquire_phy_lock(bp); in bnx2x_mdio_write()
12803 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value); in bnx2x_mdio_write()
12804 bnx2x_release_phy_lock(bp); in bnx2x_mdio_write()
12811 struct bnx2x *bp = netdev_priv(dev); in bnx2x_ioctl() local
12819 return bnx2x_hwtstamp_ioctl(bp, ifr); in bnx2x_ioctl()
12823 return mdio_mii_ioctl(&bp->mdio, mdio, cmd); in bnx2x_ioctl()
12829 struct bnx2x *bp = netdev_priv(dev); in bnx2x_validate_addr() local
12832 if (IS_VF(bp)) in bnx2x_validate_addr()
12833 bnx2x_sample_bulletin(bp); in bnx2x_validate_addr()
12845 struct bnx2x *bp = netdev_priv(netdev); in bnx2x_get_phys_port_id() local
12847 if (!(bp->flags & HAS_PHYS_PORT_ID)) in bnx2x_get_phys_port_id()
12850 ppid->id_len = sizeof(bp->phys_port_id); in bnx2x_get_phys_port_id()
12851 memcpy(ppid->id, bp->phys_port_id, ppid->id_len); in bnx2x_get_phys_port_id()
12882 static int __bnx2x_vlan_configure_vid(struct bnx2x *bp, u16 vid, bool add) in __bnx2x_vlan_configure_vid() argument
12886 if (IS_PF(bp)) { in __bnx2x_vlan_configure_vid()
12890 rc = bnx2x_set_vlan_one(bp, vid, &bp->sp_objs->vlan_obj, in __bnx2x_vlan_configure_vid()
12893 rc = bnx2x_vfpf_update_vlan(bp, vid, bp->fp->index, add); in __bnx2x_vlan_configure_vid()
12899 static int bnx2x_vlan_configure_vid_list(struct bnx2x *bp) in bnx2x_vlan_configure_vid_list() argument
12905 list_for_each_entry(vlan, &bp->vlan_reg, link) { in bnx2x_vlan_configure_vid_list()
12909 if (bp->vlan_cnt >= bp->vlan_credit) in bnx2x_vlan_configure_vid_list()
12912 rc = __bnx2x_vlan_configure_vid(bp, vlan->vid, true); in bnx2x_vlan_configure_vid_list()
12920 bp->vlan_cnt++; in bnx2x_vlan_configure_vid_list()
12926 static void bnx2x_vlan_configure(struct bnx2x *bp, bool set_rx_mode) in bnx2x_vlan_configure() argument
12930 need_accept_any_vlan = !!bnx2x_vlan_configure_vid_list(bp); in bnx2x_vlan_configure()
12932 if (bp->accept_any_vlan != need_accept_any_vlan) { in bnx2x_vlan_configure()
12933 bp->accept_any_vlan = need_accept_any_vlan; in bnx2x_vlan_configure()
12935 bp->accept_any_vlan ? "raised" : "cleared"); in bnx2x_vlan_configure()
12937 if (IS_PF(bp)) in bnx2x_vlan_configure()
12938 bnx2x_set_rx_mode_inner(bp); in bnx2x_vlan_configure()
12940 bnx2x_vfpf_storm_rx_mode(bp); in bnx2x_vlan_configure()
12945 int bnx2x_vlan_reconfigure_vid(struct bnx2x *bp) in bnx2x_vlan_reconfigure_vid() argument
12948 bnx2x_vlan_configure(bp, false); in bnx2x_vlan_reconfigure_vid()
12955 struct bnx2x *bp = netdev_priv(dev); in bnx2x_vlan_rx_add_vid() local
12966 list_add_tail(&vlan->link, &bp->vlan_reg); in bnx2x_vlan_rx_add_vid()
12969 bnx2x_vlan_configure(bp, true); in bnx2x_vlan_rx_add_vid()
12976 struct bnx2x *bp = netdev_priv(dev); in bnx2x_vlan_rx_kill_vid() local
12983 list_for_each_entry(vlan, &bp->vlan_reg, link) in bnx2x_vlan_rx_kill_vid()
12995 rc = __bnx2x_vlan_configure_vid(bp, vid, false); in bnx2x_vlan_rx_kill_vid()
12997 bp->vlan_cnt--; in bnx2x_vlan_rx_kill_vid()
13004 bnx2x_vlan_configure(bp, true); in bnx2x_vlan_rx_kill_vid()
13042 static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev, in bnx2x_init_dev() argument
13053 bp->dev = dev; in bnx2x_init_dev()
13054 bp->pdev = pdev; in bnx2x_init_dev()
13058 dev_err(&bp->pdev->dev, in bnx2x_init_dev()
13064 dev_err(&bp->pdev->dev, in bnx2x_init_dev()
13070 if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { in bnx2x_init_dev()
13071 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n"); in bnx2x_init_dev()
13087 dev_err(&bp->pdev->dev, in bnx2x_init_dev()
13096 if (IS_PF(bp)) { in bnx2x_init_dev()
13098 dev_err(&bp->pdev->dev, in bnx2x_init_dev()
13106 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n"); in bnx2x_init_dev()
13111 rc = dma_set_mask_and_coherent(&bp->pdev->dev, DMA_BIT_MASK(64)); in bnx2x_init_dev()
13113 dev_err(&bp->pdev->dev, "System does not support DMA, aborting\n"); in bnx2x_init_dev()
13123 bp->regview = pci_ioremap_bar(pdev, 0); in bnx2x_init_dev()
13124 if (!bp->regview) { in bnx2x_init_dev()
13125 dev_err(&bp->pdev->dev, in bnx2x_init_dev()
13137 bp->pf_num = PCI_FUNC(pdev->devfn); in bnx2x_init_dev()
13140 pci_read_config_dword(bp->pdev, in bnx2x_init_dev()
13142 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >> in bnx2x_init_dev()
13145 BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num); in bnx2x_init_dev()
13148 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, in bnx2x_init_dev()
13158 if (IS_PF(bp)) { in bnx2x_init_dev()
13159 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0); in bnx2x_init_dev()
13160 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0); in bnx2x_init_dev()
13161 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0); in bnx2x_init_dev()
13162 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0); in bnx2x_init_dev()
13165 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0); in bnx2x_init_dev()
13166 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0); in bnx2x_init_dev()
13167 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0); in bnx2x_init_dev()
13168 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0); in bnx2x_init_dev()
13176 REG_WR(bp, in bnx2x_init_dev()
13183 bnx2x_set_ethtool_ops(bp, dev); in bnx2x_init_dev()
13209 if (IS_PF(bp)) in bnx2x_init_dev()
13216 if (IS_PF(bp)) { in bnx2x_init_dev()
13218 bp->accept_any_vlan = true; in bnx2x_init_dev()
13243 bp->mdio.prtad = MDIO_PRTAD_NONE; in bnx2x_init_dev()
13244 bp->mdio.mmds = 0; in bnx2x_init_dev()
13245 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; in bnx2x_init_dev()
13246 bp->mdio.dev = dev; in bnx2x_init_dev()
13247 bp->mdio.mdio_read = bnx2x_mdio_read; in bnx2x_init_dev()
13248 bp->mdio.mdio_write = bnx2x_mdio_write; in bnx2x_init_dev()
13263 static int bnx2x_check_firmware(struct bnx2x *bp) in bnx2x_check_firmware() argument
13265 const struct firmware *firmware = bp->firmware; in bnx2x_check_firmware()
13307 if (fw_ver[0] != bp->fw_major || fw_ver[1] != bp->fw_minor || in bnx2x_check_firmware()
13308 fw_ver[2] != bp->fw_rev || fw_ver[3] != bp->fw_eng) { in bnx2x_check_firmware()
13311 bp->fw_major, bp->fw_minor, bp->fw_rev, bp->fw_eng); in bnx2x_check_firmware()
13382 bp->arr = kmalloc(len, GFP_KERNEL); \
13383 if (!bp->arr) \
13385 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
13386 (u8 *)bp->arr, len); \
13389 static int bnx2x_init_firmware(struct bnx2x *bp) in bnx2x_init_firmware() argument
13395 if (bp->firmware) in bnx2x_init_firmware()
13398 if (CHIP_IS_E1(bp)) { in bnx2x_init_firmware()
13401 } else if (CHIP_IS_E1H(bp)) { in bnx2x_init_firmware()
13404 } else if (!CHIP_IS_E1x(bp)) { in bnx2x_init_firmware()
13414 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev); in bnx2x_init_firmware()
13419 rc = request_firmware(&bp->firmware, fw_file_name_v15, &bp->pdev->dev); in bnx2x_init_firmware()
13424 bp->fw_rev = BCM_5710_FW_REVISION_VERSION_V15; in bnx2x_init_firmware()
13426 bp->fw_cap |= FW_CAP_INVALIDATE_VF_FP_HSI; in bnx2x_init_firmware()
13427 bp->fw_rev = BCM_5710_FW_REVISION_VERSION; in bnx2x_init_firmware()
13430 bp->fw_major = BCM_5710_FW_MAJOR_VERSION; in bnx2x_init_firmware()
13431 bp->fw_minor = BCM_5710_FW_MINOR_VERSION; in bnx2x_init_firmware()
13432 bp->fw_eng = BCM_5710_FW_ENGINEERING_VERSION; in bnx2x_init_firmware()
13434 rc = bnx2x_check_firmware(bp); in bnx2x_init_firmware()
13440 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data; in bnx2x_init_firmware()
13455 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data + in bnx2x_init_firmware()
13457 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data + in bnx2x_init_firmware()
13459 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data + in bnx2x_init_firmware()
13461 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data + in bnx2x_init_firmware()
13463 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data + in bnx2x_init_firmware()
13465 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data + in bnx2x_init_firmware()
13467 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data + in bnx2x_init_firmware()
13469 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data + in bnx2x_init_firmware()
13477 kfree(bp->init_ops_offsets); in bnx2x_init_firmware()
13479 kfree(bp->init_ops); in bnx2x_init_firmware()
13481 kfree(bp->init_data); in bnx2x_init_firmware()
13483 release_firmware(bp->firmware); in bnx2x_init_firmware()
13484 bp->firmware = NULL; in bnx2x_init_firmware()
13489 static void bnx2x_release_firmware(struct bnx2x *bp) in bnx2x_release_firmware() argument
13491 kfree(bp->init_ops_offsets); in bnx2x_release_firmware()
13492 kfree(bp->init_ops); in bnx2x_release_firmware()
13493 kfree(bp->init_data); in bnx2x_release_firmware()
13494 release_firmware(bp->firmware); in bnx2x_release_firmware()
13495 bp->firmware = NULL; in bnx2x_release_firmware()
13515 void bnx2x__init_func_obj(struct bnx2x *bp) in bnx2x__init_func_obj() argument
13518 bnx2x_setup_dmae(bp); in bnx2x__init_func_obj()
13520 bnx2x_init_func_obj(bp, &bp->func_obj, in bnx2x__init_func_obj()
13521 bnx2x_sp(bp, func_rdata), in bnx2x__init_func_obj()
13522 bnx2x_sp_mapping(bp, func_rdata), in bnx2x__init_func_obj()
13523 bnx2x_sp(bp, func_afex_rdata), in bnx2x__init_func_obj()
13524 bnx2x_sp_mapping(bp, func_afex_rdata), in bnx2x__init_func_obj()
13529 static int bnx2x_set_qm_cid_count(struct bnx2x *bp) in bnx2x_set_qm_cid_count() argument
13531 int cid_count = BNX2X_L2_MAX_CID(bp); in bnx2x_set_qm_cid_count()
13533 if (IS_SRIOV(bp)) in bnx2x_set_qm_cid_count()
13536 if (CNIC_SUPPORT(bp)) in bnx2x_set_qm_cid_count()
13636 static int bnx2x_send_update_drift_ramrod(struct bnx2x *bp, int drift_dir, in bnx2x_send_update_drift_ramrod() argument
13647 func_params.f_obj = &bp->func_obj; in bnx2x_send_update_drift_ramrod()
13658 return bnx2x_func_state_change(bp, &func_params); in bnx2x_send_update_drift_ramrod()
13663 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info); in bnx2x_ptp_adjfine() local
13672 if (!netif_running(bp->dev)) { in bnx2x_ptp_adjfine()
13717 rc = bnx2x_send_update_drift_ramrod(bp, drift_dir, best_val, in bnx2x_ptp_adjfine()
13732 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info); in bnx2x_ptp_adjtime() local
13734 if (!netif_running(bp->dev)) { in bnx2x_ptp_adjtime()
13742 timecounter_adjtime(&bp->timecounter, delta); in bnx2x_ptp_adjtime()
13749 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info); in bnx2x_ptp_gettime() local
13752 if (!netif_running(bp->dev)) { in bnx2x_ptp_gettime()
13758 ns = timecounter_read(&bp->timecounter); in bnx2x_ptp_gettime()
13770 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info); in bnx2x_ptp_settime() local
13773 if (!netif_running(bp->dev)) { in bnx2x_ptp_settime()
13784 timecounter_init(&bp->timecounter, &bp->cyclecounter, ns); in bnx2x_ptp_settime()
13793 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info); in bnx2x_ptp_enable() local
13799 void bnx2x_register_phc(struct bnx2x *bp) in bnx2x_register_phc() argument
13802 bp->ptp_clock_info.owner = THIS_MODULE; in bnx2x_register_phc()
13803 snprintf(bp->ptp_clock_info.name, 16, "%s", bp->dev->name); in bnx2x_register_phc()
13804 bp->ptp_clock_info.max_adj = BNX2X_MAX_PHC_DRIFT; /* In PPB */ in bnx2x_register_phc()
13805 bp->ptp_clock_info.n_alarm = 0; in bnx2x_register_phc()
13806 bp->ptp_clock_info.n_ext_ts = 0; in bnx2x_register_phc()
13807 bp->ptp_clock_info.n_per_out = 0; in bnx2x_register_phc()
13808 bp->ptp_clock_info.pps = 0; in bnx2x_register_phc()
13809 bp->ptp_clock_info.adjfine = bnx2x_ptp_adjfine; in bnx2x_register_phc()
13810 bp->ptp_clock_info.adjtime = bnx2x_ptp_adjtime; in bnx2x_register_phc()
13811 bp->ptp_clock_info.gettime64 = bnx2x_ptp_gettime; in bnx2x_register_phc()
13812 bp->ptp_clock_info.settime64 = bnx2x_ptp_settime; in bnx2x_register_phc()
13813 bp->ptp_clock_info.enable = bnx2x_ptp_enable; in bnx2x_register_phc()
13815 bp->ptp_clock = ptp_clock_register(&bp->ptp_clock_info, &bp->pdev->dev); in bnx2x_register_phc()
13816 if (IS_ERR(bp->ptp_clock)) { in bnx2x_register_phc()
13817 bp->ptp_clock = NULL; in bnx2x_register_phc()
13826 struct bnx2x *bp; in bnx2x_init_one() local
13878 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count); in bnx2x_init_one()
13882 bp = netdev_priv(dev); in bnx2x_init_one()
13884 bp->flags = 0; in bnx2x_init_one()
13886 bp->flags |= IS_VF_FLAG; in bnx2x_init_one()
13888 bp->igu_sb_cnt = max_non_def_sbs; in bnx2x_init_one()
13889 bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM; in bnx2x_init_one()
13890 bp->msg_enable = debug; in bnx2x_init_one()
13891 bp->cnic_support = cnic_cnt; in bnx2x_init_one()
13892 bp->cnic_probe = bnx2x_cnic_probe; in bnx2x_init_one()
13896 rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data); in bnx2x_init_one()
13903 IS_PF(bp) ? "physical" : "virtual"); in bnx2x_init_one()
13904 BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off"); in bnx2x_init_one()
13909 rc = bnx2x_init_bp(bp); in bnx2x_init_one()
13917 if (IS_VF(bp)) { in bnx2x_init_one()
13918 bp->doorbells = bnx2x_vf_doorbells(bp); in bnx2x_init_one()
13919 rc = bnx2x_vf_pci_alloc(bp); in bnx2x_init_one()
13923 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT); in bnx2x_init_one()
13925 dev_err(&bp->pdev->dev, in bnx2x_init_one()
13930 bp->doorbells = ioremap(pci_resource_start(pdev, 2), in bnx2x_init_one()
13933 if (!bp->doorbells) { in bnx2x_init_one()
13934 dev_err(&bp->pdev->dev, in bnx2x_init_one()
13940 if (IS_VF(bp)) { in bnx2x_init_one()
13941 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count); in bnx2x_init_one()
13947 if (bp->acquire_resp.pfdev_info.pf_cap & PFVF_CAP_VLAN_FILTER) { in bnx2x_init_one()
13955 rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS); in bnx2x_init_one()
13960 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp); in bnx2x_init_one()
13961 BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count); in bnx2x_init_one()
13964 if (CHIP_IS_E1x(bp)) in bnx2x_init_one()
13965 bp->flags |= NO_FCOE_FLAG; in bnx2x_init_one()
13968 bnx2x_set_num_queues(bp); in bnx2x_init_one()
13973 rc = bnx2x_set_int_mode(bp); in bnx2x_init_one()
13988 if (!NO_FCOE(bp)) { in bnx2x_init_one()
13991 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); in bnx2x_init_one()
13997 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4), in bnx2x_init_one()
13998 dev->base_addr, bp->pdev->irq, dev->dev_addr); in bnx2x_init_one()
13999 pcie_print_link_status(bp->pdev); in bnx2x_init_one()
14001 if (!IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp)) in bnx2x_init_one()
14002 bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_DISABLED); in bnx2x_init_one()
14007 bnx2x_free_mem_bp(bp); in bnx2x_init_one()
14010 if (bp->regview) in bnx2x_init_one()
14011 iounmap(bp->regview); in bnx2x_init_one()
14013 if (IS_PF(bp) && bp->doorbells) in bnx2x_init_one()
14014 iounmap(bp->doorbells); in bnx2x_init_one()
14028 struct bnx2x *bp, in __bnx2x_remove() argument
14032 if (!NO_FCOE(bp)) { in __bnx2x_remove()
14034 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); in __bnx2x_remove()
14040 bnx2x_dcbnl_update_applist(bp, true); in __bnx2x_remove()
14043 if (IS_PF(bp) && in __bnx2x_remove()
14044 !BP_NOMCP(bp) && in __bnx2x_remove()
14045 (bp->flags & BC_SUPPORTS_RMMOD_CMD)) in __bnx2x_remove()
14046 bnx2x_fw_command(bp, DRV_MSG_CODE_RMMOD, 0); in __bnx2x_remove()
14057 bnx2x_iov_remove_one(bp); in __bnx2x_remove()
14060 if (IS_PF(bp)) { in __bnx2x_remove()
14061 bnx2x_set_power_state(bp, PCI_D0); in __bnx2x_remove()
14062 bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_NOT_LOADED); in __bnx2x_remove()
14067 bnx2x_reset_endianity(bp); in __bnx2x_remove()
14071 bnx2x_disable_msi(bp); in __bnx2x_remove()
14074 if (IS_PF(bp)) in __bnx2x_remove()
14075 bnx2x_set_power_state(bp, PCI_D3hot); in __bnx2x_remove()
14078 cancel_delayed_work_sync(&bp->sp_rtnl_task); in __bnx2x_remove()
14081 if (IS_VF(bp)) in __bnx2x_remove()
14082 bnx2x_vfpf_release(bp); in __bnx2x_remove()
14086 pci_wake_from_d3(pdev, bp->wol); in __bnx2x_remove()
14091 if (bp->regview) in __bnx2x_remove()
14092 iounmap(bp->regview); in __bnx2x_remove()
14097 if (IS_PF(bp)) { in __bnx2x_remove()
14098 if (bp->doorbells) in __bnx2x_remove()
14099 iounmap(bp->doorbells); in __bnx2x_remove()
14101 bnx2x_release_firmware(bp); in __bnx2x_remove()
14103 bnx2x_vf_pci_dealloc(bp); in __bnx2x_remove()
14105 bnx2x_free_mem_bp(bp); in __bnx2x_remove()
14119 struct bnx2x *bp; in bnx2x_remove_one() local
14125 bp = netdev_priv(dev); in bnx2x_remove_one()
14127 __bnx2x_remove(pdev, dev, bp, true); in bnx2x_remove_one()
14130 static int bnx2x_eeh_nic_unload(struct bnx2x *bp) in bnx2x_eeh_nic_unload() argument
14132 bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT; in bnx2x_eeh_nic_unload()
14134 bp->rx_mode = BNX2X_RX_MODE_NONE; in bnx2x_eeh_nic_unload()
14136 if (CNIC_LOADED(bp)) in bnx2x_eeh_nic_unload()
14137 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD); in bnx2x_eeh_nic_unload()
14140 bnx2x_tx_disable(bp); in bnx2x_eeh_nic_unload()
14141 netdev_reset_tc(bp->dev); in bnx2x_eeh_nic_unload()
14143 del_timer_sync(&bp->timer); in bnx2x_eeh_nic_unload()
14144 cancel_delayed_work_sync(&bp->sp_task); in bnx2x_eeh_nic_unload()
14145 cancel_delayed_work_sync(&bp->period_task); in bnx2x_eeh_nic_unload()
14147 if (!down_timeout(&bp->stats_lock, HZ / 10)) { in bnx2x_eeh_nic_unload()
14148 bp->stats_state = STATS_STATE_DISABLED; in bnx2x_eeh_nic_unload()
14149 up(&bp->stats_lock); in bnx2x_eeh_nic_unload()
14152 bnx2x_save_statistics(bp); in bnx2x_eeh_nic_unload()
14154 netif_carrier_off(bp->dev); in bnx2x_eeh_nic_unload()
14171 struct bnx2x *bp = netdev_priv(dev); in bnx2x_io_error_detected() local
14185 bnx2x_eeh_nic_unload(bp); in bnx2x_io_error_detected()
14187 bnx2x_prev_path_mark_eeh(bp); in bnx2x_io_error_detected()
14206 struct bnx2x *bp = netdev_priv(dev); in bnx2x_io_slot_reset() local
14223 bnx2x_set_power_state(bp, PCI_D0); in bnx2x_io_slot_reset()
14229 if (bnx2x_init_shmem(bp)) { in bnx2x_io_slot_reset()
14234 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) { in bnx2x_io_slot_reset()
14237 v = SHMEM2_RD(bp, in bnx2x_io_slot_reset()
14238 drv_capabilities_flag[BP_FW_MB_IDX(bp)]); in bnx2x_io_slot_reset()
14239 SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)], in bnx2x_io_slot_reset()
14242 bnx2x_drain_tx_queues(bp); in bnx2x_io_slot_reset()
14243 bnx2x_send_unload_req(bp, UNLOAD_RECOVERY); in bnx2x_io_slot_reset()
14244 if (!bp->nic_stopped) { in bnx2x_io_slot_reset()
14245 bnx2x_netif_stop(bp, 1); in bnx2x_io_slot_reset()
14246 bnx2x_del_all_napi(bp); in bnx2x_io_slot_reset()
14248 if (CNIC_LOADED(bp)) in bnx2x_io_slot_reset()
14249 bnx2x_del_all_napi_cnic(bp); in bnx2x_io_slot_reset()
14251 bnx2x_free_irq(bp); in bnx2x_io_slot_reset()
14252 bp->nic_stopped = true; in bnx2x_io_slot_reset()
14256 bnx2x_send_unload_done(bp, true); in bnx2x_io_slot_reset()
14258 bp->sp_state = 0; in bnx2x_io_slot_reset()
14259 bp->port.pmf = 0; in bnx2x_io_slot_reset()
14261 bnx2x_prev_unload(bp); in bnx2x_io_slot_reset()
14266 bnx2x_squeeze_objects(bp); in bnx2x_io_slot_reset()
14267 bnx2x_free_skbs(bp); in bnx2x_io_slot_reset()
14268 for_each_rx_queue(bp, i) in bnx2x_io_slot_reset()
14269 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE); in bnx2x_io_slot_reset()
14270 bnx2x_free_fp_mem(bp); in bnx2x_io_slot_reset()
14271 bnx2x_free_mem(bp); in bnx2x_io_slot_reset()
14273 bp->state = BNX2X_STATE_CLOSED; in bnx2x_io_slot_reset()
14291 struct bnx2x *bp = netdev_priv(dev); in bnx2x_io_resume() local
14293 if (bp->recovery_state != BNX2X_RECOVERY_DONE) { in bnx2x_io_resume()
14294 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n"); in bnx2x_io_resume()
14300 bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & in bnx2x_io_resume()
14304 if (bnx2x_nic_load(bp, LOAD_NORMAL)) { in bnx2x_io_resume()
14305 netdev_err(bp->dev, "Error during driver initialization, try unloading/reloading the driver\n"); in bnx2x_io_resume()
14325 struct bnx2x *bp; in bnx2x_shutdown() local
14330 bp = netdev_priv(dev); in bnx2x_shutdown()
14331 if (!bp) in bnx2x_shutdown()
14342 __bnx2x_remove(pdev, dev, bp, false); in bnx2x_shutdown()
14401 void bnx2x_notify_link_changed(struct bnx2x *bp) in bnx2x_notify_link_changed() argument
14403 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1); in bnx2x_notify_link_changed()
14416 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp) in bnx2x_set_iscsi_eth_mac_addr() argument
14421 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac, in bnx2x_set_iscsi_eth_mac_addr()
14422 &bp->iscsi_l2_mac_obj, true, in bnx2x_set_iscsi_eth_mac_addr()
14427 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count) in bnx2x_cnic_sp_post() argument
14433 if (unlikely(bp->panic)) in bnx2x_cnic_sp_post()
14437 spin_lock_bh(&bp->spq_lock); in bnx2x_cnic_sp_post()
14438 BUG_ON(bp->cnic_spq_pending < count); in bnx2x_cnic_sp_post()
14439 bp->cnic_spq_pending -= count; in bnx2x_cnic_sp_post()
14441 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) { in bnx2x_cnic_sp_post()
14442 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type) in bnx2x_cnic_sp_post()
14445 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data) in bnx2x_cnic_sp_post()
14453 cxt_index = BNX2X_ISCSI_ETH_CID(bp) / in bnx2x_cnic_sp_post()
14455 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) - in bnx2x_cnic_sp_post()
14457 bnx2x_set_ctx_validation(bp, in bnx2x_cnic_sp_post()
14458 &bp->context[cxt_index]. in bnx2x_cnic_sp_post()
14460 BNX2X_ISCSI_ETH_CID(bp)); in bnx2x_cnic_sp_post()
14471 if (!atomic_read(&bp->cq_spq_left)) in bnx2x_cnic_sp_post()
14474 atomic_dec(&bp->cq_spq_left); in bnx2x_cnic_sp_post()
14476 if (!atomic_read(&bp->eq_spq_left)) in bnx2x_cnic_sp_post()
14479 atomic_dec(&bp->eq_spq_left); in bnx2x_cnic_sp_post()
14482 if (bp->cnic_spq_pending >= in bnx2x_cnic_sp_post()
14483 bp->cnic_eth_dev.max_kwqe_pending) in bnx2x_cnic_sp_post()
14486 bp->cnic_spq_pending++; in bnx2x_cnic_sp_post()
14493 spe = bnx2x_sp_get_next(bp); in bnx2x_cnic_sp_post()
14494 *spe = *bp->cnic_kwq_cons; in bnx2x_cnic_sp_post()
14497 bp->cnic_spq_pending, bp->cnic_kwq_pending, count); in bnx2x_cnic_sp_post()
14499 if (bp->cnic_kwq_cons == bp->cnic_kwq_last) in bnx2x_cnic_sp_post()
14500 bp->cnic_kwq_cons = bp->cnic_kwq; in bnx2x_cnic_sp_post()
14502 bp->cnic_kwq_cons++; in bnx2x_cnic_sp_post()
14504 bnx2x_sp_prod_update(bp); in bnx2x_cnic_sp_post()
14505 spin_unlock_bh(&bp->spq_lock); in bnx2x_cnic_sp_post()
14511 struct bnx2x *bp = netdev_priv(dev); in bnx2x_cnic_sp_queue() local
14515 if (unlikely(bp->panic)) { in bnx2x_cnic_sp_queue()
14521 if ((bp->recovery_state != BNX2X_RECOVERY_DONE) && in bnx2x_cnic_sp_queue()
14522 (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) { in bnx2x_cnic_sp_queue()
14527 spin_lock_bh(&bp->spq_lock); in bnx2x_cnic_sp_queue()
14532 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT) in bnx2x_cnic_sp_queue()
14535 *bp->cnic_kwq_prod = *spe; in bnx2x_cnic_sp_queue()
14537 bp->cnic_kwq_pending++; in bnx2x_cnic_sp_queue()
14543 bp->cnic_kwq_pending); in bnx2x_cnic_sp_queue()
14545 if (bp->cnic_kwq_prod == bp->cnic_kwq_last) in bnx2x_cnic_sp_queue()
14546 bp->cnic_kwq_prod = bp->cnic_kwq; in bnx2x_cnic_sp_queue()
14548 bp->cnic_kwq_prod++; in bnx2x_cnic_sp_queue()
14551 spin_unlock_bh(&bp->spq_lock); in bnx2x_cnic_sp_queue()
14553 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending) in bnx2x_cnic_sp_queue()
14554 bnx2x_cnic_sp_post(bp, 0); in bnx2x_cnic_sp_queue()
14559 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl) in bnx2x_cnic_ctl_send() argument
14564 mutex_lock(&bp->cnic_mutex); in bnx2x_cnic_ctl_send()
14565 c_ops = rcu_dereference_protected(bp->cnic_ops, in bnx2x_cnic_ctl_send()
14566 lockdep_is_held(&bp->cnic_mutex)); in bnx2x_cnic_ctl_send()
14568 rc = c_ops->cnic_ctl(bp->cnic_data, ctl); in bnx2x_cnic_ctl_send()
14569 mutex_unlock(&bp->cnic_mutex); in bnx2x_cnic_ctl_send()
14574 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl) in bnx2x_cnic_ctl_send_bh() argument
14580 c_ops = rcu_dereference(bp->cnic_ops); in bnx2x_cnic_ctl_send_bh()
14582 rc = c_ops->cnic_ctl(bp->cnic_data, ctl); in bnx2x_cnic_ctl_send_bh()
14591 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd) in bnx2x_cnic_notify() argument
14597 return bnx2x_cnic_ctl_send(bp, &ctl); in bnx2x_cnic_notify()
14600 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err) in bnx2x_cnic_cfc_comp() argument
14609 bnx2x_cnic_ctl_send_bh(bp, &ctl); in bnx2x_cnic_cfc_comp()
14610 bnx2x_cnic_sp_post(bp, 0); in bnx2x_cnic_cfc_comp()
14618 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start) in bnx2x_set_iscsi_eth_rx_mode() argument
14621 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); in bnx2x_set_iscsi_eth_rx_mode()
14637 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state); in bnx2x_set_iscsi_eth_rx_mode()
14642 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state); in bnx2x_set_iscsi_eth_rx_mode()
14644 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) in bnx2x_set_iscsi_eth_rx_mode()
14645 set_bit(sched_state, &bp->sp_state); in bnx2x_set_iscsi_eth_rx_mode()
14648 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0, in bnx2x_set_iscsi_eth_rx_mode()
14655 struct bnx2x *bp = netdev_priv(dev); in bnx2x_drv_ctl() local
14663 bnx2x_ilt_wr(bp, index, addr); in bnx2x_drv_ctl()
14670 bnx2x_cnic_sp_post(bp, count); in bnx2x_drv_ctl()
14676 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; in bnx2x_drv_ctl()
14680 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj, in bnx2x_drv_ctl()
14682 cp->iscsi_l2_cid, BP_FUNC(bp), in bnx2x_drv_ctl()
14683 bnx2x_sp(bp, mac_rdata), in bnx2x_drv_ctl()
14684 bnx2x_sp_mapping(bp, mac_rdata), in bnx2x_drv_ctl()
14686 &bp->sp_state, BNX2X_OBJ_TYPE_RX, in bnx2x_drv_ctl()
14687 &bp->macs_pool); in bnx2x_drv_ctl()
14690 rc = bnx2x_set_iscsi_eth_mac_addr(bp); in bnx2x_drv_ctl()
14699 bnx2x_set_iscsi_eth_rx_mode(bp, true); in bnx2x_drv_ctl()
14706 if (!bnx2x_wait_sp_comp(bp, sp_bits)) in bnx2x_drv_ctl()
14718 bnx2x_set_iscsi_eth_rx_mode(bp, false); in bnx2x_drv_ctl()
14725 if (!bnx2x_wait_sp_comp(bp, sp_bits)) in bnx2x_drv_ctl()
14731 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj, in bnx2x_drv_ctl()
14739 atomic_add(count, &bp->cq_spq_left); in bnx2x_drv_ctl()
14746 if (CHIP_IS_E3(bp)) { in bnx2x_drv_ctl()
14747 int idx = BP_FW_MB_IDX(bp); in bnx2x_drv_ctl()
14748 u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); in bnx2x_drv_ctl()
14749 int path = BP_PATH(bp); in bnx2x_drv_ctl()
14750 int port = BP_PORT(bp); in bnx2x_drv_ctl()
14760 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap); in bnx2x_drv_ctl()
14763 (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) || in bnx2x_drv_ctl()
14764 (!(bp->flags & BC_SUPPORTS_FCOE_FEATURES))) in bnx2x_drv_ctl()
14768 scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr); in bnx2x_drv_ctl()
14777 REG_WR(bp, scratch_offset + i, in bnx2x_drv_ctl()
14780 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0); in bnx2x_drv_ctl()
14787 if (CHIP_IS_E3(bp)) { in bnx2x_drv_ctl()
14788 int idx = BP_FW_MB_IDX(bp); in bnx2x_drv_ctl()
14791 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); in bnx2x_drv_ctl()
14796 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap); in bnx2x_drv_ctl()
14798 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0); in bnx2x_drv_ctl()
14808 if (IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp)) { in bnx2x_drv_ctl()
14813 bnx2x_set_os_driver_state(bp, in bnx2x_drv_ctl()
14817 bnx2x_set_os_driver_state(bp, in bnx2x_drv_ctl()
14821 bnx2x_set_os_driver_state(bp, in bnx2x_drv_ctl()
14835 struct bnx2x *bp = netdev_priv(dev); in bnx2x_get_fc_npiv() local
14841 if (!SHMEM2_HAS(bp, fc_npiv_nvram_tbl_addr[0])) in bnx2x_get_fc_npiv()
14852 offset = SHMEM2_RD(bp, fc_npiv_nvram_tbl_addr[BP_PORT(bp)]); in bnx2x_get_fc_npiv()
14860 if (bnx2x_nvram_read(bp, offset, (u8 *)tbl, sizeof(*tbl))) { in bnx2x_get_fc_npiv()
14898 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp) in bnx2x_setup_cnic_irq_info() argument
14900 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; in bnx2x_setup_cnic_irq_info()
14902 if (bp->flags & USING_MSIX_FLAG) { in bnx2x_setup_cnic_irq_info()
14905 cp->irq_arr[0].vector = bp->msix_table[1].vector; in bnx2x_setup_cnic_irq_info()
14910 if (!CHIP_IS_E1x(bp)) in bnx2x_setup_cnic_irq_info()
14911 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb; in bnx2x_setup_cnic_irq_info()
14913 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb; in bnx2x_setup_cnic_irq_info()
14915 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp); in bnx2x_setup_cnic_irq_info()
14916 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp); in bnx2x_setup_cnic_irq_info()
14917 cp->irq_arr[1].status_blk = bp->def_status_blk; in bnx2x_setup_cnic_irq_info()
14924 void bnx2x_setup_cnic_info(struct bnx2x *bp) in bnx2x_setup_cnic_info() argument
14926 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; in bnx2x_setup_cnic_info()
14928 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) + in bnx2x_setup_cnic_info()
14929 bnx2x_cid_ilt_lines(bp); in bnx2x_setup_cnic_info()
14930 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS; in bnx2x_setup_cnic_info()
14931 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp); in bnx2x_setup_cnic_info()
14932 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp); in bnx2x_setup_cnic_info()
14935 BNX2X_1st_NON_L2_ETH_CID(bp), cp->starting_cid, cp->fcoe_init_cid, in bnx2x_setup_cnic_info()
14938 if (NO_ISCSI_OOO(bp)) in bnx2x_setup_cnic_info()
14945 struct bnx2x *bp = netdev_priv(dev); in bnx2x_register_cnic() local
14946 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; in bnx2x_register_cnic()
14956 if (!CNIC_SUPPORT(bp)) { in bnx2x_register_cnic()
14961 if (!CNIC_LOADED(bp)) { in bnx2x_register_cnic()
14962 rc = bnx2x_load_cnic(bp); in bnx2x_register_cnic()
14969 bp->cnic_enabled = true; in bnx2x_register_cnic()
14971 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL); in bnx2x_register_cnic()
14972 if (!bp->cnic_kwq) in bnx2x_register_cnic()
14975 bp->cnic_kwq_cons = bp->cnic_kwq; in bnx2x_register_cnic()
14976 bp->cnic_kwq_prod = bp->cnic_kwq; in bnx2x_register_cnic()
14977 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT; in bnx2x_register_cnic()
14979 bp->cnic_spq_pending = 0; in bnx2x_register_cnic()
14980 bp->cnic_kwq_pending = 0; in bnx2x_register_cnic()
14982 bp->cnic_data = data; in bnx2x_register_cnic()
14986 cp->iro_arr = bp->iro_arr; in bnx2x_register_cnic()
14988 bnx2x_setup_cnic_irq_info(bp); in bnx2x_register_cnic()
14990 rcu_assign_pointer(bp->cnic_ops, ops); in bnx2x_register_cnic()
14993 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0); in bnx2x_register_cnic()
15000 struct bnx2x *bp = netdev_priv(dev); in bnx2x_unregister_cnic() local
15001 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; in bnx2x_unregister_cnic()
15003 mutex_lock(&bp->cnic_mutex); in bnx2x_unregister_cnic()
15005 RCU_INIT_POINTER(bp->cnic_ops, NULL); in bnx2x_unregister_cnic()
15006 mutex_unlock(&bp->cnic_mutex); in bnx2x_unregister_cnic()
15008 bp->cnic_enabled = false; in bnx2x_unregister_cnic()
15009 kfree(bp->cnic_kwq); in bnx2x_unregister_cnic()
15010 bp->cnic_kwq = NULL; in bnx2x_unregister_cnic()
15017 struct bnx2x *bp = netdev_priv(dev); in bnx2x_cnic_probe() local
15018 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; in bnx2x_cnic_probe()
15024 if (NO_ISCSI(bp) && NO_FCOE(bp)) in bnx2x_cnic_probe()
15028 cp->chip_id = CHIP_ID(bp); in bnx2x_cnic_probe()
15029 cp->pdev = bp->pdev; in bnx2x_cnic_probe()
15030 cp->io_base = bp->regview; in bnx2x_cnic_probe()
15031 cp->io_base2 = bp->doorbells; in bnx2x_cnic_probe()
15034 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) + in bnx2x_cnic_probe()
15035 bnx2x_cid_ilt_lines(bp); in bnx2x_cnic_probe()
15037 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS; in bnx2x_cnic_probe()
15043 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp); in bnx2x_cnic_probe()
15045 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); in bnx2x_cnic_probe()
15046 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp); in bnx2x_cnic_probe()
15048 if (NO_ISCSI_OOO(bp)) in bnx2x_cnic_probe()
15051 if (NO_ISCSI(bp)) in bnx2x_cnic_probe()
15054 if (NO_FCOE(bp)) in bnx2x_cnic_probe()
15068 struct bnx2x *bp = fp->bp; in bnx2x_rx_ustorm_prods_offset() local
15071 if (IS_VF(bp)) in bnx2x_rx_ustorm_prods_offset()
15072 return bnx2x_vf_ustorm_prods_offset(bp, fp); in bnx2x_rx_ustorm_prods_offset()
15073 else if (!CHIP_IS_E1x(bp)) in bnx2x_rx_ustorm_prods_offset()
15076 offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id); in bnx2x_rx_ustorm_prods_offset()
15086 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val) in bnx2x_pretend_func() argument
15090 if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX) in bnx2x_pretend_func()
15094 pretend_reg = bnx2x_get_pretend_reg(bp); in bnx2x_pretend_func()
15095 REG_WR(bp, pretend_reg, pretend_func_val); in bnx2x_pretend_func()
15096 REG_RD(bp, pretend_reg); in bnx2x_pretend_func()
15102 struct bnx2x *bp = container_of(work, struct bnx2x, ptp_task); in bnx2x_ptp_task() local
15103 int port = BP_PORT(bp); in bnx2x_ptp_task()
15115 val_seq = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID : in bnx2x_ptp_task()
15126 timestamp = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_MSB : in bnx2x_ptp_task()
15129 timestamp |= REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_LSB : in bnx2x_ptp_task()
15132 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID : in bnx2x_ptp_task()
15134 ns = timecounter_cyc2time(&bp->timecounter, timestamp); in bnx2x_ptp_task()
15138 skb_tstamp_tx(bp->ptp_tx_skb, &shhwtstamps); in bnx2x_ptp_task()
15146 bp->eth_stats.ptp_skip_tx_ts++; in bnx2x_ptp_task()
15149 dev_kfree_skb_any(bp->ptp_tx_skb); in bnx2x_ptp_task()
15150 bp->ptp_tx_skb = NULL; in bnx2x_ptp_task()
15153 void bnx2x_set_rx_ts(struct bnx2x *bp, struct sk_buff *skb) in bnx2x_set_rx_ts() argument
15155 int port = BP_PORT(bp); in bnx2x_set_rx_ts()
15158 timestamp = REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB : in bnx2x_set_rx_ts()
15161 timestamp |= REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB : in bnx2x_set_rx_ts()
15165 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID : in bnx2x_set_rx_ts()
15168 ns = timecounter_cyc2time(&bp->timecounter, timestamp); in bnx2x_set_rx_ts()
15179 struct bnx2x *bp = container_of(cc, struct bnx2x, cyclecounter); in bnx2x_cyclecounter_read() local
15180 int port = BP_PORT(bp); in bnx2x_cyclecounter_read()
15184 REG_RD_DMAE(bp, port ? NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t1 : in bnx2x_cyclecounter_read()
15194 static void bnx2x_init_cyclecounter(struct bnx2x *bp) in bnx2x_init_cyclecounter() argument
15196 memset(&bp->cyclecounter, 0, sizeof(bp->cyclecounter)); in bnx2x_init_cyclecounter()
15197 bp->cyclecounter.read = bnx2x_cyclecounter_read; in bnx2x_init_cyclecounter()
15198 bp->cyclecounter.mask = CYCLECOUNTER_MASK(64); in bnx2x_init_cyclecounter()
15199 bp->cyclecounter.shift = 0; in bnx2x_init_cyclecounter()
15200 bp->cyclecounter.mult = 1; in bnx2x_init_cyclecounter()
15203 static int bnx2x_send_reset_timesync_ramrod(struct bnx2x *bp) in bnx2x_send_reset_timesync_ramrod() argument
15213 func_params.f_obj = &bp->func_obj; in bnx2x_send_reset_timesync_ramrod()
15220 return bnx2x_func_state_change(bp, &func_params); in bnx2x_send_reset_timesync_ramrod()
15223 static int bnx2x_enable_ptp_packets(struct bnx2x *bp) in bnx2x_enable_ptp_packets() argument
15238 for_each_eth_queue(bp, i) { in bnx2x_enable_ptp_packets()
15239 struct bnx2x_fastpath *fp = &bp->fp[i]; in bnx2x_enable_ptp_packets()
15242 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; in bnx2x_enable_ptp_packets()
15245 rc = bnx2x_queue_state_change(bp, &q_params); in bnx2x_enable_ptp_packets()
15268 int bnx2x_configure_ptp_filters(struct bnx2x *bp) in bnx2x_configure_ptp_filters() argument
15270 int port = BP_PORT(bp); in bnx2x_configure_ptp_filters()
15274 if (!bp->hwtstamp_ioctl_called) in bnx2x_configure_ptp_filters()
15281 switch (bp->tx_type) { in bnx2x_configure_ptp_filters()
15283 bp->flags |= TX_TIMESTAMPING_EN; in bnx2x_configure_ptp_filters()
15284 REG_WR(bp, param, BNX2X_PTP_TX_ON_PARAM_MASK); in bnx2x_configure_ptp_filters()
15285 REG_WR(bp, rule, BNX2X_PTP_TX_ON_RULE_MASK); in bnx2x_configure_ptp_filters()
15297 switch (bp->rx_filter) { in bnx2x_configure_ptp_filters()
15303 bp->rx_filter = HWTSTAMP_FILTER_NONE; in bnx2x_configure_ptp_filters()
15308 bp->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; in bnx2x_configure_ptp_filters()
15310 REG_WR(bp, param, BNX2X_PTP_V1_L4_PARAM_MASK); in bnx2x_configure_ptp_filters()
15311 REG_WR(bp, rule, BNX2X_PTP_V1_L4_RULE_MASK); in bnx2x_configure_ptp_filters()
15316 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; in bnx2x_configure_ptp_filters()
15318 REG_WR(bp, param, BNX2X_PTP_V2_L4_PARAM_MASK); in bnx2x_configure_ptp_filters()
15319 REG_WR(bp, rule, BNX2X_PTP_V2_L4_RULE_MASK); in bnx2x_configure_ptp_filters()
15324 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; in bnx2x_configure_ptp_filters()
15326 REG_WR(bp, param, BNX2X_PTP_V2_L2_PARAM_MASK); in bnx2x_configure_ptp_filters()
15327 REG_WR(bp, rule, BNX2X_PTP_V2_L2_RULE_MASK); in bnx2x_configure_ptp_filters()
15333 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; in bnx2x_configure_ptp_filters()
15335 REG_WR(bp, param, BNX2X_PTP_V2_PARAM_MASK); in bnx2x_configure_ptp_filters()
15336 REG_WR(bp, rule, BNX2X_PTP_V2_RULE_MASK); in bnx2x_configure_ptp_filters()
15341 rc = bnx2x_enable_ptp_packets(bp); in bnx2x_configure_ptp_filters()
15346 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST : in bnx2x_configure_ptp_filters()
15352 static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr) in bnx2x_hwtstamp_ioctl() argument
15365 bp->hwtstamp_ioctl_called = true; in bnx2x_hwtstamp_ioctl()
15366 bp->tx_type = config.tx_type; in bnx2x_hwtstamp_ioctl()
15367 bp->rx_filter = config.rx_filter; in bnx2x_hwtstamp_ioctl()
15369 rc = bnx2x_configure_ptp_filters(bp); in bnx2x_hwtstamp_ioctl()
15373 config.rx_filter = bp->rx_filter; in bnx2x_hwtstamp_ioctl()
15380 static int bnx2x_configure_ptp(struct bnx2x *bp) in bnx2x_configure_ptp() argument
15382 int rc, port = BP_PORT(bp); in bnx2x_configure_ptp()
15386 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : in bnx2x_configure_ptp()
15388 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK : in bnx2x_configure_ptp()
15390 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK : in bnx2x_configure_ptp()
15392 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK : in bnx2x_configure_ptp()
15396 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST : in bnx2x_configure_ptp()
15400 REG_WR(bp, port ? NIG_REG_P1_PTP_EN : in bnx2x_configure_ptp()
15406 REG_WR_DMAE(bp, NIG_REG_TIMESYNC_GEN_REG + tsgen_ctrl, wb_data, 2); in bnx2x_configure_ptp()
15409 rc = bnx2x_send_reset_timesync_ramrod(bp); in bnx2x_configure_ptp()
15416 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID : in bnx2x_configure_ptp()
15418 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID : in bnx2x_configure_ptp()
15425 void bnx2x_init_ptp(struct bnx2x *bp) in bnx2x_init_ptp() argument
15430 rc = bnx2x_configure_ptp(bp); in bnx2x_init_ptp()
15437 INIT_WORK(&bp->ptp_task, bnx2x_ptp_task); in bnx2x_init_ptp()
15443 if (!bp->timecounter_init_done) { in bnx2x_init_ptp()
15444 bnx2x_init_cyclecounter(bp); in bnx2x_init_ptp()
15445 timecounter_init(&bp->timecounter, &bp->cyclecounter, in bnx2x_init_ptp()
15447 bp->timecounter_init_done = true; in bnx2x_init_ptp()