617 	u32 src_clk_period, dst_clk_period; /* in picoseconds */  in tegra210_emc_r21021_set_clock()  local
652 	dst_clk_period = 1000000000 / next->rate;  in tegra210_emc_r21021_set_clock()
654 	if (dst_clk_period <= zqcal_before_cc_cutoff)  in tegra210_emc_r21021_set_clock()
659 	tZQCAL_lpddr4_fc_adj /= dst_clk_period;  in tegra210_emc_r21021_set_clock()
684 		src_clk_period, dst_clk_period);  in tegra210_emc_r21021_set_clock()
875 		zq_wait_long = max((u32)1, div_o3(1000000, dst_clk_period));  in tegra210_emc_r21021_set_clock()
878 				   div_o3(360000, dst_clk_period)) + 4;  in tegra210_emc_r21021_set_clock()
881 				   div_o3(320000, dst_clk_period) + 2);  in tegra210_emc_r21021_set_clock()
1269 		    dst_clk_period <= zqcal_before_cc_cutoff) {  in tegra210_emc_r21021_set_clock()
1383 	ramp_up_wait = tegra210_emc_dvfs_power_ramp_up(emc, dst_clk_period, 0);  in tegra210_emc_r21021_set_clock()
1409 	if (dst_clk_period <= zqcal_before_cc_cutoff) {  in tegra210_emc_r21021_set_clock()
1411 			(s32)dst_clk_period;  in tegra210_emc_r21021_set_clock()
1416 			       dst_clk_period);  in tegra210_emc_r21021_set_clock()
1421 		dst_clk_period);  in tegra210_emc_r21021_set_clock()
1429 			       dst_clk_period);  in tegra210_emc_r21021_set_clock()
1432 			if (dst_clk_period > zqcal_before_cc_cutoff)  in tegra210_emc_r21021_set_clock()
1447 			if (dst_clk_period > zqcal_before_cc_cutoff)  in tegra210_emc_r21021_set_clock()
1468 				      tZQCAL_lpddr4 / dst_clk_period);  in tegra210_emc_r21021_set_clock()
1470 			if (dst_clk_period > zqcal_before_cc_cutoff)  in tegra210_emc_r21021_set_clock()
1531 			value = div_o3(value, dst_clk_period);  in tegra210_emc_r21021_set_clock()
1572 			delay = (1250000 - ramp_up_wait) / dst_clk_period;  in tegra210_emc_r21021_set_clock()