Lines Matching +full:lpddr4 +full:- +full:channel
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
14 #include "tegra210-emc.h"
15 #include "tegra210-mc.h"
36 #define emc_dbg(emc, flags, ...) dev_dbg(emc->dev, __VA_ARGS__)
53 * PTFV defines - basically just indexes into the per table PTFV array.
78 ({ next->ptfv_list[PTFV_DQSOSC_MOVAVG_ ## dev ## _INDEX] = \
79 next->ptfv_list[PTFV_DQSOSC_MOVAVG_ ## dev ## _INDEX] / \
80 next->ptfv_list[PTFV_DVFS_SAMPLES_INDEX]; })
86 ({ next->ptfv_list[PTFV_DQSOSC_MOVAVG_ ## dev ## _INDEX] += \
93 ((timing)->ptfv_list[PTFV_DQSOSC_MOVAVG_ ## dev ## _INDEX] / \
102 next->ptfv_list[dqs] = \
104 (next->ptfv_list[dqs] * \
105 next->ptfv_list[w])) / \
106 (next->ptfv_list[w] + 1); \
109 __stringify(dev), nval, next->ptfv_list[dqs]); \
114 ((timing)->ptfv_list[PTFV_DQSOSC_MOVAVG_ ## dev ## _INDEX])
119 struct tegra210_emc_timing *last = emc->last; in update_clock_tree_delay()
120 struct tegra210_emc_timing *next = emc->next; in update_clock_tree_delay()
121 u32 last_timing_rate_mhz = last->rate / 1000; in update_clock_tree_delay()
122 u32 next_timing_rate_mhz = next->rate / 1000; in update_clock_tree_delay()
136 for (i = 0; i < emc->num_channels; i++) { in update_clock_tree_delay()
147 for (i = 0; i < emc->num_channels; i++) { in update_clock_tree_delay()
155 cval = tegra210_emc_actual_osc_clocks(last->run_clocks); in update_clock_tree_delay()
168 tdel = next->current_dram_clktree[C0D0U0] - in update_clock_tree_delay()
170 tmdel = (tdel < 0) ? -1 * tdel : tdel; in update_clock_tree_delay()
174 next->tree_margin) in update_clock_tree_delay()
175 next->current_dram_clktree[C0D0U0] = in update_clock_tree_delay()
180 cval = tegra210_emc_actual_osc_clocks(last->run_clocks); in update_clock_tree_delay()
193 tdel = next->current_dram_clktree[C0D0U1] - in update_clock_tree_delay()
195 tmdel = (tdel < 0) ? -1 * tdel : tdel; in update_clock_tree_delay()
201 next->tree_margin) in update_clock_tree_delay()
202 next->current_dram_clktree[C0D0U1] = in update_clock_tree_delay()
206 if (emc->num_channels > 1) { in update_clock_tree_delay()
208 cval = tegra210_emc_actual_osc_clocks(last->run_clocks); in update_clock_tree_delay()
221 tdel = next->current_dram_clktree[C1D0U0] - in update_clock_tree_delay()
223 tmdel = (tdel < 0) ? -1 * tdel : tdel; in update_clock_tree_delay()
229 next->tree_margin) in update_clock_tree_delay()
230 next->current_dram_clktree[C1D0U0] = in update_clock_tree_delay()
235 cval = tegra210_emc_actual_osc_clocks(last->run_clocks); in update_clock_tree_delay()
248 tdel = next->current_dram_clktree[C1D0U1] - in update_clock_tree_delay()
250 tmdel = (tdel < 0) ? -1 * tdel : tdel; in update_clock_tree_delay()
256 next->tree_margin) in update_clock_tree_delay()
257 next->current_dram_clktree[C1D0U1] = in update_clock_tree_delay()
262 if (emc->num_devices < 2) in update_clock_tree_delay()
271 for (i = 0; i < emc->num_channels; i++) { in update_clock_tree_delay()
282 for (i = 0; i < emc->num_channels; i++) { in update_clock_tree_delay()
290 cval = tegra210_emc_actual_osc_clocks(last->run_clocks); in update_clock_tree_delay()
303 tdel = next->current_dram_clktree[C0D1U0] - in update_clock_tree_delay()
305 tmdel = (tdel < 0) ? -1 * tdel : tdel; in update_clock_tree_delay()
311 next->tree_margin) in update_clock_tree_delay()
312 next->current_dram_clktree[C0D1U0] = in update_clock_tree_delay()
317 cval = tegra210_emc_actual_osc_clocks(last->run_clocks); in update_clock_tree_delay()
330 tdel = next->current_dram_clktree[C0D1U1] - in update_clock_tree_delay()
332 tmdel = (tdel < 0) ? -1 * tdel : tdel; in update_clock_tree_delay()
338 next->tree_margin) in update_clock_tree_delay()
339 next->current_dram_clktree[C0D1U1] = in update_clock_tree_delay()
343 if (emc->num_channels > 1) { in update_clock_tree_delay()
345 cval = tegra210_emc_actual_osc_clocks(last->run_clocks); in update_clock_tree_delay()
358 tdel = next->current_dram_clktree[C1D1U0] - in update_clock_tree_delay()
360 tmdel = (tdel < 0) ? -1 * tdel : tdel; in update_clock_tree_delay()
366 next->tree_margin) in update_clock_tree_delay()
367 next->current_dram_clktree[C1D1U0] = in update_clock_tree_delay()
372 cval = tegra210_emc_actual_osc_clocks(last->run_clocks); in update_clock_tree_delay()
385 tdel = next->current_dram_clktree[C1D1U1] - in update_clock_tree_delay()
387 tmdel = (tdel < 0) ? -1 * tdel : tdel; in update_clock_tree_delay()
393 next->tree_margin) in update_clock_tree_delay()
394 next->current_dram_clktree[C1D1U1] = in update_clock_tree_delay()
409 (nt)->ptfv_list[PTFV_DVFS_SAMPLES_INDEX]; }) in periodic_compensation_handler()
411 u32 i, adel = 0, samples = next->ptfv_list[PTFV_DVFS_SAMPLES_INDEX]; in periodic_compensation_handler()
414 delay = tegra210_emc_actual_osc_clocks(last->run_clocks); in periodic_compensation_handler()
416 delay = 2 + (delay / last->rate); in periodic_compensation_handler()
418 if (!next->periodic_training) in periodic_compensation_handler()
422 if (last->periodic_training && in periodic_compensation_handler()
423 (next->ptfv_list[PTFV_CONFIG_CTRL_INDEX] & in periodic_compensation_handler()
462 * 'if (last_timing->periodic_training)' conditional in periodic_compensation_handler()
493 struct tegra210_emc_timing *last = emc->last; in tegra210_emc_r21021_periodic_compensation()
497 if (last->periodic_training) { in tegra210_emc_r21021_periodic_compensation()
515 for (i = 0; i < emc->num_channels; i++) in tegra210_emc_r21021_periodic_compensation()
520 for (i = 0; i < emc->num_channels; i++) in tegra210_emc_r21021_periodic_compensation()
531 * 2. osc kick off - this assumes training and dvfs have set in tegra210_emc_r21021_periodic_compensation()
539 delay = tegra210_emc_actual_osc_clocks(last->run_clocks); in tegra210_emc_r21021_periodic_compensation()
541 delay /= last->rate + 1; in tegra210_emc_r21021_periodic_compensation()
556 if (last->tree_margin < ((del * 128 * (last->rate / 1000)) / 1000000)) { in tegra210_emc_r21021_periodic_compensation()
607 struct tegra210_emc_timing *fake, *last = emc->last, *next = emc->next; in tegra210_emc_r21021_set_clock()
612 u32 tFC_lpddr4 = 1000 * next->dram_timings[T_FC_LPDDR4]; in tegra210_emc_r21021_set_clock()
627 fake = tegra210_emc_find_timing(emc, last->rate * 1000UL); in tegra210_emc_r21021_set_clock()
633 if (last->burst_regs[EMC_ZCAL_WAIT_CNT_INDEX] & BIT(31)) in tegra210_emc_r21021_set_clock()
636 if ((next->burst_regs[EMC_ZCAL_INTERVAL_INDEX] != 0 && in tegra210_emc_r21021_set_clock()
637 last->burst_regs[EMC_ZCAL_INTERVAL_INDEX] == 0) || in tegra210_emc_r21021_set_clock()
644 if ((next->burst_regs[EMC_FBIO_CFG5_INDEX] & BIT(25)) && in tegra210_emc_r21021_set_clock()
651 src_clk_period = 1000000000 / last->rate; in tegra210_emc_r21021_set_clock()
652 dst_clk_period = 1000000000 / next->rate; in tegra210_emc_r21021_set_clock()
655 tZQCAL_lpddr4_fc_adj = tZQCAL_lpddr4 - tFC_lpddr4; in tegra210_emc_r21021_set_clock()
665 emc_cfg = next->burst_regs[EMC_CFG_INDEX]; in tegra210_emc_r21021_set_clock()
668 emc_sel_dpd_ctrl = next->emc_sel_dpd_ctrl; in tegra210_emc_r21021_set_clock()
678 emc_dbg(emc, INFO, "DRAM dev #: %u\n", emc->num_devices); in tegra210_emc_r21021_set_clock()
680 emc_dbg(emc, INFO, "DLL clksrc: 0x%08x\n", next->dll_clk_src); in tegra210_emc_r21021_set_clock()
681 emc_dbg(emc, INFO, "last rate: %u, next rate %u\n", last->rate, in tegra210_emc_r21021_set_clock()
682 next->rate); in tegra210_emc_r21021_set_clock()
686 emc_dbg(emc, INFO, " num_channels: %u\n", emc->num_channels); in tegra210_emc_r21021_set_clock()
702 for (i = 0; i < emc->num_channels; i++) in tegra210_emc_r21021_set_clock()
708 emc_auto_cal_config = next->emc_auto_cal_config; in tegra210_emc_r21021_set_clock()
724 if (next->periodic_training) { in tegra210_emc_r21021_set_clock()
727 for (i = 0; i < emc->num_channels; i++) in tegra210_emc_r21021_set_clock()
732 for (i = 0; i < emc->num_channels; i++) in tegra210_emc_r21021_set_clock()
739 delay = 1000 * tegra210_emc_actual_osc_clocks(last->run_clocks); in tegra210_emc_r21021_set_clock()
740 udelay((delay / last->rate) + 2); in tegra210_emc_r21021_set_clock()
744 value = (value * 128 * next->rate / 1000) / 1000000; in tegra210_emc_r21021_set_clock()
746 if (next->periodic_training && value > next->tree_margin) in tegra210_emc_r21021_set_clock()
756 emc_writel(emc, next->emc_fdpd_ctrl_cmd_no_ramp & in tegra210_emc_r21021_set_clock()
761 ((next->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] & in tegra210_emc_r21021_set_clock()
763 (last->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] & in tegra210_emc_r21021_set_clock()
765 ((next->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] & in tegra210_emc_r21021_set_clock()
767 (last->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] & in tegra210_emc_r21021_set_clock()
770 (next->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] & in tegra210_emc_r21021_set_clock()
773 (next->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] & in tegra210_emc_r21021_set_clock()
778 emc_writel(emc, last->burst_regs in tegra210_emc_r21021_set_clock()
784 emc_writel(emc, last->burst_regs in tegra210_emc_r21021_set_clock()
791 if ((((last->burst_regs[EMC_PMACRO_DATA_PAD_TX_CTRL_INDEX] & in tegra210_emc_r21021_set_clock()
793 ((next->burst_regs[EMC_PMACRO_DATA_PAD_TX_CTRL_INDEX] & in tegra210_emc_r21021_set_clock()
795 (((last->burst_regs[EMC_PMACRO_DATA_PAD_TX_CTRL_INDEX] & in tegra210_emc_r21021_set_clock()
797 ((next->burst_regs[EMC_PMACRO_DATA_PAD_TX_CTRL_INDEX] & in tegra210_emc_r21021_set_clock()
800 next->burst_regs[EMC_PMACRO_DATA_PAD_TX_CTRL_INDEX]; in tegra210_emc_r21021_set_clock()
802 last->burst_regs[EMC_PMACRO_DATA_PAD_TX_CTRL_INDEX]; in tegra210_emc_r21021_set_clock()
827 if (next->burst_regs[EMC_CFG_DIG_DLL_INDEX] & in tegra210_emc_r21021_set_clock()
844 emc_writel(emc, next->emc_auto_cal_config2, EMC_AUTO_CAL_CONFIG2); in tegra210_emc_r21021_set_clock()
845 emc_writel(emc, next->emc_auto_cal_config3, EMC_AUTO_CAL_CONFIG3); in tegra210_emc_r21021_set_clock()
846 emc_writel(emc, next->emc_auto_cal_config4, EMC_AUTO_CAL_CONFIG4); in tegra210_emc_r21021_set_clock()
847 emc_writel(emc, next->emc_auto_cal_config5, EMC_AUTO_CAL_CONFIG5); in tegra210_emc_r21021_set_clock()
848 emc_writel(emc, next->emc_auto_cal_config6, EMC_AUTO_CAL_CONFIG6); in tegra210_emc_r21021_set_clock()
849 emc_writel(emc, next->emc_auto_cal_config7, EMC_AUTO_CAL_CONFIG7); in tegra210_emc_r21021_set_clock()
850 emc_writel(emc, next->emc_auto_cal_config8, EMC_AUTO_CAL_CONFIG8); in tegra210_emc_r21021_set_clock()
866 emc_writel(emc, next->emc_cfg_2, EMC_CFG_2); in tegra210_emc_r21021_set_clock()
877 zq_wait_long = max(next->min_mrs_wait, in tegra210_emc_r21021_set_clock()
887 * Training code - removed. in tegra210_emc_r21021_set_clock()
896 emc_dbg(emc, SUB_STEPS, "Step 7.1: Bug 200024907 - Patch RP R2P"); in tegra210_emc_r21021_set_clock()
924 tRPST = (last->emc_mrw & 0x80) >> 7; in tegra210_emc_r21021_set_clock()
925 tRTM = fake->dram_timings[RL] + div_o3(3600, src_clk_period) + in tegra210_emc_r21021_set_clock()
930 next->burst_regs[EMC_RP_INDEX]); in tegra210_emc_r21021_set_clock()
932 if (last->burst_regs[EMC_RP_INDEX] < tRTM) { in tegra210_emc_r21021_set_clock()
933 if (tRTM > (last->burst_regs[EMC_R2P_INDEX] + in tegra210_emc_r21021_set_clock()
934 last->burst_regs[EMC_RP_INDEX])) { in tegra210_emc_r21021_set_clock()
935 R2P_war = tRTM - last->burst_regs[EMC_RP_INDEX]; in tegra210_emc_r21021_set_clock()
936 RP_war = last->burst_regs[EMC_RP_INDEX]; in tegra210_emc_r21021_set_clock()
937 TRPab_war = last->burst_regs[EMC_TRPAB_INDEX]; in tegra210_emc_r21021_set_clock()
941 last->burst_regs[EMC_RP_INDEX] - 63; in tegra210_emc_r21021_set_clock()
949 R2P_war = last->burst_regs[EMC_R2P_INDEX]; in tegra210_emc_r21021_set_clock()
950 RP_war = last->burst_regs[EMC_RP_INDEX]; in tegra210_emc_r21021_set_clock()
951 TRPab_war = last->burst_regs[EMC_TRPAB_INDEX]; in tegra210_emc_r21021_set_clock()
955 W2P_war = last->burst_regs[EMC_W2P_INDEX] in tegra210_emc_r21021_set_clock()
956 + deltaTWATM - RP_war; in tegra210_emc_r21021_set_clock()
958 RP_war = RP_war + W2P_war - 63; in tegra210_emc_r21021_set_clock()
964 W2P_war = last->burst_regs[ in tegra210_emc_r21021_set_clock()
968 if ((last->burst_regs[EMC_W2P_INDEX] ^ W2P_war) || in tegra210_emc_r21021_set_clock()
969 (last->burst_regs[EMC_R2P_INDEX] ^ R2P_war) || in tegra210_emc_r21021_set_clock()
970 (last->burst_regs[EMC_RP_INDEX] ^ RP_war) || in tegra210_emc_r21021_set_clock()
971 (last->burst_regs[EMC_TRPAB_INDEX] ^ TRPab_war)) { in tegra210_emc_r21021_set_clock()
985 mr13_flip_fspwr = (next->emc_mrw3 & 0xffffff3f) | 0x80; in tegra210_emc_r21021_set_clock()
986 mr13_flip_fspop = (next->emc_mrw3 & 0xffffff3f) | 0x00; in tegra210_emc_r21021_set_clock()
988 mr13_flip_fspwr = (next->emc_mrw3 & 0xffffff3f) | 0x40; in tegra210_emc_r21021_set_clock()
989 mr13_flip_fspop = (next->emc_mrw3 & 0xffffff3f) | 0xc0; in tegra210_emc_r21021_set_clock()
994 emc_writel(emc, next->emc_mrw, EMC_MRW); in tegra210_emc_r21021_set_clock()
995 emc_writel(emc, next->emc_mrw2, EMC_MRW2); in tegra210_emc_r21021_set_clock()
1005 for (i = 0; i < next->num_burst; i++) { in tegra210_emc_r21021_set_clock()
1006 const u16 *offsets = emc->offsets->burst; in tegra210_emc_r21021_set_clock()
1012 value = next->burst_regs[i]; in tegra210_emc_r21021_set_clock()
1077 (next->run_clocks & EMC_MRW_MRW_OP_MASK); in tegra210_emc_r21021_set_clock()
1081 /* Per channel burst registers. */ in tegra210_emc_r21021_set_clock()
1084 for (i = 0; i < next->num_burst_per_ch; i++) { in tegra210_emc_r21021_set_clock()
1086 emc->offsets->burst_per_channel; in tegra210_emc_r21021_set_clock()
1104 /* Filter out second channel if not in DUAL_CHANNEL mode. */ in tegra210_emc_r21021_set_clock()
1105 if (emc->num_channels < 2 && burst[i].bank >= 1) in tegra210_emc_r21021_set_clock()
1109 next->burst_reg_per_ch[i], burst[i].offset); in tegra210_emc_r21021_set_clock()
1111 next->burst_reg_per_ch[i], in tegra210_emc_r21021_set_clock()
1118 for (i = 0; i < next->vref_num; i++) { in tegra210_emc_r21021_set_clock()
1120 emc->offsets->vref_per_channel; in tegra210_emc_r21021_set_clock()
1125 if (emc->num_channels < 2 && vref[i].bank >= 1) in tegra210_emc_r21021_set_clock()
1129 next->vref_perch_regs[i], vref[i].offset); in tegra210_emc_r21021_set_clock()
1130 emc_channel_writel(emc, vref[i].bank, next->vref_perch_regs[i], in tegra210_emc_r21021_set_clock()
1137 for (i = 0; i < next->num_trim; i++) { in tegra210_emc_r21021_set_clock()
1138 const u16 *offsets = emc->offsets->trim; in tegra210_emc_r21021_set_clock()
1162 next->trim_regs[i], offsets[i]); in tegra210_emc_r21021_set_clock()
1163 emc_writel(emc, next->trim_regs[i], offsets[i]); in tegra210_emc_r21021_set_clock()
1167 /* Per channel trimmers. */ in tegra210_emc_r21021_set_clock()
1170 for (i = 0; i < next->num_trim_per_ch; i++) { in tegra210_emc_r21021_set_clock()
1172 &emc->offsets->trim_per_channel[0]; in tegra210_emc_r21021_set_clock()
1178 if (emc->num_channels < 2 && trim[i].bank >= 1) in tegra210_emc_r21021_set_clock()
1202 next->trim_perch_regs[i], offset); in tegra210_emc_r21021_set_clock()
1204 next->trim_perch_regs[i], offset); in tegra210_emc_r21021_set_clock()
1210 for (i = 0; i < next->num_mc_regs; i++) { in tegra210_emc_r21021_set_clock()
1211 const u16 *offsets = emc->offsets->burst_mc; in tegra210_emc_r21021_set_clock()
1212 u32 *values = next->burst_mc_regs; in tegra210_emc_r21021_set_clock()
1216 mc_writel(emc->mc, values[i], offsets[i]); in tegra210_emc_r21021_set_clock()
1220 if (next->rate < last->rate) { in tegra210_emc_r21021_set_clock()
1221 const u16 *la = emc->offsets->la_scale; in tegra210_emc_r21021_set_clock()
1225 for (i = 0; i < next->num_up_down; i++) { in tegra210_emc_r21021_set_clock()
1227 next->la_scale_regs[i], la[i]); in tegra210_emc_r21021_set_clock()
1228 mc_writel(emc->mc, next->la_scale_regs[i], la[i]); in tegra210_emc_r21021_set_clock()
1233 mc_readl(emc->mc, MC_EMEM_ADR_CFG); in tegra210_emc_r21021_set_clock()
1237 * LPDDR4 section A. in tegra210_emc_r21021_set_clock()
1241 value = next->burst_regs[EMC_ZCAL_WAIT_CNT_INDEX]; in tegra210_emc_r21021_set_clock()
1258 * LPDDR4 and DDR3 common section. in tegra210_emc_r21021_set_clock()
1271 ccfifo_writel(emc, (next->burst_regs[EMC_MRW6_INDEX] & in tegra210_emc_r21021_set_clock()
1273 (last->burst_regs[EMC_MRW6_INDEX] & in tegra210_emc_r21021_set_clock()
1275 ccfifo_writel(emc, (next->burst_regs[EMC_MRW14_INDEX] & in tegra210_emc_r21021_set_clock()
1277 (last->burst_regs[EMC_MRW14_INDEX] & in tegra210_emc_r21021_set_clock()
1280 if (emc->num_devices > 1) { in tegra210_emc_r21021_set_clock()
1282 (next->burst_regs[EMC_MRW7_INDEX] & in tegra210_emc_r21021_set_clock()
1284 (last->burst_regs[EMC_MRW7_INDEX] & in tegra210_emc_r21021_set_clock()
1287 (next->burst_regs[EMC_MRW15_INDEX] & in tegra210_emc_r21021_set_clock()
1289 (last->burst_regs[EMC_MRW15_INDEX] & in tegra210_emc_r21021_set_clock()
1294 if (emc->num_devices < 2) in tegra210_emc_r21021_set_clock()
1313 value = (1000 * fake->dram_timings[T_RP]) / src_clk_period; in tegra210_emc_r21021_set_clock()
1322 delay += (1000 * fake->dram_timings[T_RP]) / in tegra210_emc_r21021_set_clock()
1324 delay += 4000 * fake->dram_timings[T_RFC]; in tegra210_emc_r21021_set_clock()
1346 delay = ((1000 * fake->dram_timings[T_RP] / src_clk_period) + in tegra210_emc_r21021_set_clock()
1347 (1000 * fake->dram_timings[T_RFC] / src_clk_period)); in tegra210_emc_r21021_set_clock()
1369 * And finally - trigger the clock change. in tegra210_emc_r21021_set_clock()
1395 if (emc->num_devices <= 1) in tegra210_emc_r21021_set_clock()
1412 zq_latch_dvfs_wait_time = (s32)tZQCAL_lpddr4_fc_adj - t; in tegra210_emc_r21021_set_clock()
1414 zq_latch_dvfs_wait_time = tZQCAL_lpddr4_fc_adj - in tegra210_emc_r21021_set_clock()
1415 div_o3(1000 * next->dram_timings[T_PDEX], in tegra210_emc_r21021_set_clock()
1422 emc_dbg(emc, INFO, "next->dram_timings[T_PDEX] = %u\n", in tegra210_emc_r21021_set_clock()
1423 next->dram_timings[T_PDEX]); in tegra210_emc_r21021_set_clock()
1428 delay = div_o3(1000 * next->dram_timings[T_PDEX], in tegra210_emc_r21021_set_clock()
1431 if (emc->num_devices < 2) { in tegra210_emc_r21021_set_clock()
1489 * LPDDR4 Conditional Training Kickoff. Removed. in tegra210_emc_r21021_set_clock()
1508 ccfifo_writel(emc, next->emc_mrw2, EMC_MRW2, 0); in tegra210_emc_r21021_set_clock()
1509 ccfifo_writel(emc, next->emc_mrw, EMC_MRW, 0); in tegra210_emc_r21021_set_clock()
1511 ccfifo_writel(emc, next->emc_mrw4, EMC_MRW4, 0); in tegra210_emc_r21021_set_clock()
1514 ccfifo_writel(emc, next->emc_emrs & in tegra210_emc_r21021_set_clock()
1516 ccfifo_writel(emc, next->emc_emrs2 & in tegra210_emc_r21021_set_clock()
1518 ccfifo_writel(emc, next->emc_mrs | in tegra210_emc_r21021_set_clock()
1545 if (emc->num_devices > 1) { in tegra210_emc_r21021_set_clock()
1560 if (emc->num_devices > 1) { in tegra210_emc_r21021_set_clock()
1572 delay = (1250000 - ramp_up_wait) / dst_clk_period; in tegra210_emc_r21021_set_clock()
1577 next->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX], in tegra210_emc_r21021_set_clock()
1606 ccfifo_writel(emc, next->burst_regs[EMC_ZCAL_INTERVAL_INDEX], in tegra210_emc_r21021_set_clock()
1610 ccfifo_writel(emc, next->burst_regs[EMC_CFG_INDEX] & in tegra210_emc_r21021_set_clock()
1627 next->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] & in tegra210_emc_r21021_set_clock()
1632 next->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] & in tegra210_emc_r21021_set_clock()
1664 if (next->rate > last->rate) { in tegra210_emc_r21021_set_clock()
1665 for (i = 0; i < next->num_up_down; i++) in tegra210_emc_r21021_set_clock()
1666 mc_writel(emc->mc, next->la_scale_regs[i], in tegra210_emc_r21021_set_clock()
1667 emc->offsets->la_scale[i]); in tegra210_emc_r21021_set_clock()
1680 emc_writel(emc, next->burst_regs[EMC_ZCAL_WAIT_CNT_INDEX], in tegra210_emc_r21021_set_clock()
1682 emc_writel(emc, next->burst_regs[EMC_ZCAL_INTERVAL_INDEX], in tegra210_emc_r21021_set_clock()
1693 emc_writel(emc, next->burst_regs[EMC_MRS_WAIT_CNT_INDEX], in tegra210_emc_r21021_set_clock()
1696 emc_writel(emc, next->burst_regs[EMC_ZCAL_WAIT_CNT_INDEX], in tegra210_emc_r21021_set_clock()
1708 emc_writel(emc, next->burst_regs[EMC_CFG_INDEX], EMC_CFG); in tegra210_emc_r21021_set_clock()
1710 emc_writel(emc, next->emc_fdpd_ctrl_cmd_no_ramp, in tegra210_emc_r21021_set_clock()
1712 emc_writel(emc, next->emc_sel_dpd_ctrl, EMC_SEL_DPD_CTRL); in tegra210_emc_r21021_set_clock()
1722 next->burst_regs[EMC_PMACRO_AUTOCAL_CFG_COMMON_INDEX], in tegra210_emc_r21021_set_clock()
1749 * Re-enable autocal. in tegra210_emc_r21021_set_clock()
1751 emc_dbg(emc, STEPS, "Step 30: Re-enable DLL and AUTOCAL\n"); in tegra210_emc_r21021_set_clock()
1753 if (next->burst_regs[EMC_CFG_DIG_DLL_INDEX] & EMC_CFG_DIG_DLL_CFG_DLL_EN) { in tegra210_emc_r21021_set_clock()
1765 emc_writel(emc, next->emc_auto_cal_config, EMC_AUTO_CAL_CONFIG); in tegra210_emc_r21021_set_clock()