Lines Matching refs:CCI_REG8
31 #define IMX290_STANDBY CCI_REG8(0x3000)
32 #define IMX290_REGHOLD CCI_REG8(0x3001)
33 #define IMX290_XMSTA CCI_REG8(0x3002)
34 #define IMX290_ADBIT CCI_REG8(0x3005)
37 #define IMX290_CTRL_07 CCI_REG8(0x3007)
43 #define IMX290_FR_FDG_SEL CCI_REG8(0x3009)
45 #define IMX290_GAIN CCI_REG8(0x3014)
51 #define IMX290_WINWV_OB CCI_REG8(0x303a)
56 #define IMX290_OUT_CTRL CCI_REG8(0x3046)
63 #define IMX290_XSOUTSEL CCI_REG8(0x304b)
68 #define IMX290_INCKSEL1 CCI_REG8(0x305c)
69 #define IMX290_INCKSEL2 CCI_REG8(0x305d)
70 #define IMX290_INCKSEL3 CCI_REG8(0x305e)
71 #define IMX290_INCKSEL4 CCI_REG8(0x305f)
72 #define IMX290_PGCTRL CCI_REG8(0x308c)
73 #define IMX290_ADBIT1 CCI_REG8(0x3129)
76 #define IMX290_INCKSEL5 CCI_REG8(0x315e)
77 #define IMX290_INCKSEL6 CCI_REG8(0x3164)
78 #define IMX290_ADBIT2 CCI_REG8(0x317c)
82 #define IMX290_ADBIT3 CCI_REG8(0x31ec)
85 #define IMX290_REPETITION CCI_REG8(0x3405)
86 #define IMX290_PHY_LANE_NUM CCI_REG8(0x3407)
87 #define IMX290_OPB_SIZE_V CCI_REG8(0x3414)
92 #define IMX290_CSI_LANE_MODE CCI_REG8(0x3443)
103 #define IMX290_INCKSEL7 CCI_REG8(0x3480)
272 { CCI_REG8(0x3011), 0x02 },
273 { CCI_REG8(0x3012), 0x64 },
274 { CCI_REG8(0x3013), 0x00 },
278 { CCI_REG8(0x300f), 0x00 },
279 { CCI_REG8(0x3010), 0x21 },
280 { CCI_REG8(0x3016), 0x09 },
281 { CCI_REG8(0x3070), 0x02 },
282 { CCI_REG8(0x3071), 0x11 },
283 { CCI_REG8(0x309b), 0x10 },
284 { CCI_REG8(0x309c), 0x22 },
285 { CCI_REG8(0x30a2), 0x02 },
286 { CCI_REG8(0x30a6), 0x20 },
287 { CCI_REG8(0x30a8), 0x20 },
288 { CCI_REG8(0x30aa), 0x20 },
289 { CCI_REG8(0x30ac), 0x20 },
290 { CCI_REG8(0x30b0), 0x43 },
291 { CCI_REG8(0x3119), 0x9e },
292 { CCI_REG8(0x311c), 0x1e },
293 { CCI_REG8(0x311e), 0x08 },
294 { CCI_REG8(0x3128), 0x05 },
295 { CCI_REG8(0x313d), 0x83 },
296 { CCI_REG8(0x3150), 0x03 },
297 { CCI_REG8(0x317e), 0x00 },
298 { CCI_REG8(0x32b8), 0x50 },
299 { CCI_REG8(0x32b9), 0x10 },
300 { CCI_REG8(0x32ba), 0x00 },
301 { CCI_REG8(0x32bb), 0x04 },
302 { CCI_REG8(0x32c8), 0x50 },
303 { CCI_REG8(0x32c9), 0x10 },
304 { CCI_REG8(0x32ca), 0x00 },
305 { CCI_REG8(0x32cb), 0x04 },
306 { CCI_REG8(0x332c), 0xd3 },
307 { CCI_REG8(0x332d), 0x10 },
308 { CCI_REG8(0x332e), 0x0d },
309 { CCI_REG8(0x3358), 0x06 },
310 { CCI_REG8(0x3359), 0xe1 },
311 { CCI_REG8(0x335a), 0x11 },
312 { CCI_REG8(0x3360), 0x1e },
313 { CCI_REG8(0x3361), 0x61 },
314 { CCI_REG8(0x3362), 0x10 },
315 { CCI_REG8(0x33b0), 0x50 },
316 { CCI_REG8(0x33b2), 0x1a },
317 { CCI_REG8(0x33b3), 0x04 },
333 { CCI_REG8(0x309e), 0x4A },
334 { CCI_REG8(0x309f), 0x4A },
335 { CCI_REG8(0x313b), 0x61 },