357 #define UB960_IND_TARGET_RX_ANA(n)		(0x01 + (n))  macro
1271 	ub960_read_ind(priv, UB960_IND_TARGET_RX_ANA(nport),  in ub960_rxport_get_strobe_pos()
1277 	ub960_read_ind(priv, UB960_IND_TARGET_RX_ANA(nport),  in ub960_rxport_get_strobe_pos()
1317 	ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport),  in ub960_rxport_set_strobe_pos()
1320 	ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport),  in ub960_rxport_set_strobe_pos()
1956 	ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0xa8, 0x80);  in ub960_init_rx_port_ub9702_fpd3()
1959 	ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x0d, 0x7f);  in ub960_init_rx_port_ub9702_fpd3()
1962 	ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x2b, 0x04);  in ub960_init_rx_port_ub9702_fpd3()
1965 	ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0xa9, 0x23);  in ub960_init_rx_port_ub9702_fpd3()
1968 	ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0xaa, 0);  in ub960_init_rx_port_ub9702_fpd3()
1971 	ub960_ind_update_bits(priv, UB960_IND_TARGET_RX_ANA(nport), 0x1b,  in ub960_init_rx_port_ub9702_fpd3()
1989 		ub960_read_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x2c, &v);  in ub960_init_rx_port_ub9702_fpd4_aeq()
1991 		ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x27, v);  in ub960_init_rx_port_ub9702_fpd4_aeq()
1992 		ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x28, v + 1);  in ub960_init_rx_port_ub9702_fpd4_aeq()
1994 		ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x2b, 0x00);  in ub960_init_rx_port_ub9702_fpd4_aeq()
1998 	ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x9e, 0x00);  in ub960_init_rx_port_ub9702_fpd4_aeq()
2001 	ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x90, 0x40);  in ub960_init_rx_port_ub9702_fpd4_aeq()
2004 	ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x2e, 0x40);  in ub960_init_rx_port_ub9702_fpd4_aeq()
2007 	ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0xf0, 0x00);  in ub960_init_rx_port_ub9702_fpd4_aeq()
2010 	ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x71, 0x00);  in ub960_init_rx_port_ub9702_fpd4_aeq()
2051 	ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x2b, 0x04);  in ub960_init_rx_port_ub9702_fpd4()
2054 	ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x27, 0x0);  in ub960_init_rx_port_ub9702_fpd4()
2056 	ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x28, 0x23);  in ub960_init_rx_port_ub9702_fpd4()
2059 	ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x04, 0x00);  in ub960_init_rx_port_ub9702_fpd4()
2061 	ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x1b, 0x00);  in ub960_init_rx_port_ub9702_fpd4()
2064 	ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x21, 0x2f);  in ub960_init_rx_port_ub9702_fpd4()
2066 	ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x25, 0xc1);  in ub960_init_rx_port_ub9702_fpd4()
2129 		ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x25, 0x41);  in ub960_init_rx_port_ub9702()