111 #define pch_dbg(adap, fmt, arg...)  \  macro
230 		pch_dbg(adap, "Fast mode enabled\n");  in pch_i2c_init()
246 	pch_dbg(adap,  in pch_i2c_init()
267 			pch_dbg(adap, "I2CSR = %x\n", ioread32(p + PCH_I2CSR));  in pch_i2c_wait_for_bus_idle()
297 	pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));  in pch_i2c_start()
308 	pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));  in pch_i2c_stop()
340 		pch_dbg(adap, "Receive NACK for slave address setting\n");  in pch_i2c_wait_for_check_xfer()
354 	pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));  in pch_i2c_repstart()
388 	pch_dbg(adap, "I2CCTL = %x msgs->len = %d\n", ioread32(p + PCH_I2CCTL),  in pch_i2c_writebytes()
422 		pch_dbg(adap, "writing %x to Data register\n", buf[wrcount]);  in pch_i2c_writebytes()
438 	pch_dbg(adap, "return=%d\n", wrcount);  in pch_i2c_writebytes()
450 	pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));  in pch_i2c_sendack()
461 	pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));  in pch_i2c_sendnack()
474 	pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));  in pch_i2c_restart()
610 	pch_dbg(adap, "PCH_I2CSR = %x\n", ioread32(p + PCH_I2CSR));  in pch_i2c_cb()
673 	pch_dbg(adap, "adap->p_adapter_info->pch_i2c_suspended is %d\n",  in pch_i2c_xfer()
682 		pch_dbg(adap,  in pch_i2c_xfer()