21 #define PCH_EVENT_SET	0	/* I2C Interrupt Event Set Status */
24 #define PCH_BUFFER_MODE_ENABLE	0x0002	/* flag for Buffer mode enable */
25 #define PCH_EEPROM_SW_RST_MODE_ENABLE	0x0008	/* EEPROM SW RST enable flag */
27 #define PCH_I2CSADR	0x00	/* I2C slave address register */
28 #define PCH_I2CCTL	0x04	/* I2C control register */
29 #define PCH_I2CSR	0x08	/* I2C status register */
30 #define PCH_I2CDR	0x0C	/* I2C data register */
31 #define PCH_I2CMON	0x10	/* I2C bus monitor register */
32 #define PCH_I2CBC	0x14	/* I2C bus transfer rate setup counter */
33 #define PCH_I2CMOD	0x18	/* I2C mode register */
34 #define PCH_I2CBUFSLV	0x1C	/* I2C buffer mode slave address register */
35 #define PCH_I2CBUFSUB	0x20	/* I2C buffer mode subaddress register */
36 #define PCH_I2CBUFFOR	0x24	/* I2C buffer mode format register */
37 #define PCH_I2CBUFCTL	0x28	/* I2C buffer mode control register */
38 #define PCH_I2CBUFMSK	0x2C	/* I2C buffer mode interrupt mask register */
39 #define PCH_I2CBUFSTA	0x30	/* I2C buffer mode status register */
40 #define PCH_I2CBUFLEV	0x34	/* I2C buffer mode level register */
41 #define PCH_I2CESRFOR	0x38	/* EEPROM software reset mode format register */
42 #define PCH_I2CESRCTL	0x3C	/* EEPROM software reset mode ctrl register */
43 #define PCH_I2CESRMSK	0x40	/* EEPROM software reset mode */
44 #define PCH_I2CESRSTA	0x44	/* EEPROM software reset mode status register */
45 #define PCH_I2CTMR	0x48	/* I2C timer register */
46 #define PCH_I2CSRST	0xFC	/* I2C reset register */
47 #define PCH_I2CNF	0xF8	/* I2C noise filter register */
50 #define PCH_I2CCTL_I2CMEN	0x0080
51 #define TEN_BIT_ADDR_DEFAULT	0xF000
52 #define TEN_BIT_ADDR_MASK	0xF0
53 #define PCH_START		0x0020
54 #define PCH_RESTART		0x0004
55 #define PCH_ESR_START		0x0001
56 #define PCH_BUFF_START		0x1
57 #define PCH_REPSTART		0x0004
58 #define PCH_ACK			0x0008
59 #define PCH_GETACK		0x0001
60 #define CLR_REG			0x0
61 #define I2C_RD			0x1
62 #define I2CMCF_BIT		0x0080
63 #define I2CMIF_BIT		0x0002
64 #define I2CMAL_BIT		0x0010
65 #define I2CBMFI_BIT		0x0001
66 #define I2CBMAL_BIT		0x0002
67 #define I2CBMNA_BIT		0x0004
68 #define I2CBMTO_BIT		0x0008
69 #define I2CBMIS_BIT		0x0010
70 #define I2CESRFI_BIT		0X0001
71 #define I2CESRTO_BIT		0x0002
72 #define I2CESRFIIE_BIT		0x1
73 #define I2CESRTOIE_BIT		0x2
74 #define I2CBMDZ_BIT		0x0040
75 #define I2CBMAG_BIT		0x0020
76 #define I2CMBB_BIT		0x0020
79 #define I2C_ADDR_MSK		0xFF
80 #define I2C_MSB_2B_MSK		0x300
82 #define FAST_MODE_EN		0x0001
85 #define PCH_BUFFER_MODE		0x1
86 #define EEPROM_SW_RST_MODE	0x0002
87 #define NORMAL_INTR_ENBL	0x0300
89 #define EEPROM_RST_INTR_DISBL	0x0
90 #define BUFFER_MODE_INTR_ENBL	0x001F
91 #define BUFFER_MODE_INTR_DISBL	0x0
92 #define NORMAL_MODE		0x0
93 #define BUFFER_MODE		0x1
94 #define EEPROM_SR_MODE		0x2
95 #define I2C_TX_MODE		0x0010
96 #define PCH_BUF_TX		0xFFF7
97 #define PCH_BUF_RD		0x0008
100 #define I2CMAL_EVENT		0x0001
101 #define I2CMCF_EVENT		0x0002
102 #define I2CBMFI_EVENT		0x0004
103 #define I2CBMAL_EVENT		0x0008
104 #define I2CBMNA_EVENT		0x0010
105 #define I2CBMTO_EVENT		0x0020
106 #define I2CBMIS_EVENT		0x0040
107 #define I2CESRFI_EVENT		0x0080
108 #define I2CESRTO_EVENT		0x0100
109 #define PCI_DEVICE_ID_PCH_I2C	0x8817
172 #define PCI_DEVICE_ID_ML7213_I2C	0x802D
173 #define PCI_DEVICE_ID_ML7223_I2C	0x8010
174 #define PCI_DEVICE_ID_ML7831_I2C	0x8817
181 	{0,}
215 	iowrite32(0x01, p + PCH_I2CSRST);  in pch_i2c_init()
217 	iowrite32(0x0, p + PCH_I2CSRST);  in pch_i2c_init()
220 	iowrite32(0x21, p + PCH_I2CNF);  in pch_i2c_init()
262 	int schedule = 0;  in pch_i2c_wait_for_bus_idle()
285 	return 0;  in pch_i2c_wait_for_bus_idle()
319 			(adap->pch_event_flag != 0), msecs_to_jiffies(1000));  in pch_i2c_wait_for_check_xfer()
322 		adap->pch_event_flag = 0;  in pch_i2c_wait_for_check_xfer()
330 		adap->pch_event_flag = 0;  in pch_i2c_wait_for_check_xfer()
337 	adap->pch_event_flag = 0;  in pch_i2c_wait_for_check_xfer()
344 	return 0;  in pch_i2c_wait_for_check_xfer()
364  *		otherwise 0.
366  *		1 for first message otherwise 0.
397 		addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7) & 0x06;  in pch_i2c_writebytes()
409 		/* set 7 bit slave address and R/W bit as 0 */  in pch_i2c_writebytes()
419 	for (wrcount = 0; wrcount < length; ++wrcount) {  in pch_i2c_writebytes()
545 	if (length == 0) {  in pch_i2c_readbytes()
556 		for (loop = 1, read_index = 0; loop < length; loop++) {  in pch_i2c_readbytes()
629 	for (i = 0, flag = 0; i < adap_info->ch_num; i++) {  in pch_i2c_handler()
658 	u32 i = 0;  in pch_i2c_xfer()
678 	for (i = 0; i < num && ret >= 0; i++) {  in pch_i2c_xfer()
683 			"After invoking I2C_MODE_SEL :flag= 0x%x\n", status);  in pch_i2c_xfer()
687 						(i == 0));  in pch_i2c_xfer()
690 						 (i == 0));  in pch_i2c_xfer()
698 	return (ret < 0) ? ret : num;  in pch_i2c_xfer()
757 	base_addr = pci_iomap(pdev, 1, 0);  in pch_i2c_probe()
768 	for (i = 0; i < adap_info->ch_num; i++) {  in pch_i2c_probe()
781 		adap_info->pch_data[i].pch_base_address = base_addr + 0x100 * i;  in pch_i2c_probe()
794 	for (i = 0; i < adap_info->ch_num; i++) {  in pch_i2c_probe()
809 	return 0;  in pch_i2c_probe()
812 	for (j = 0; j < i; j++)  in pch_i2c_probe()
833 	for (i = 0; i < adap_info->ch_num; i++) {  in pch_i2c_remove()
838 	if (adap_info->pch_data[0].pch_base_address)  in pch_i2c_remove()
839 		pci_iounmap(pdev, adap_info->pch_data[0].pch_base_address);  in pch_i2c_remove()
841 	for (i = 0; i < adap_info->ch_num; i++)  in pch_i2c_remove()
855 	void __iomem *p = adap_info->pch_data[0].pch_base_address;  in pch_i2c_suspend()
859 	for (i = 0; i < adap_info->ch_num; i++) {  in pch_i2c_suspend()
867 	for (i = 0; i < adap_info->ch_num; i++)  in pch_i2c_suspend()
875 	return 0;  in pch_i2c_suspend()
883 	for (i = 0; i < adap_info->ch_num; i++)  in pch_i2c_resume()
888 	return 0;  in pch_i2c_resume()