Lines Matching refs:MAX_CHANNELS_PER_ENC
55 #define MAX_CHANNELS_PER_ENC 2 macro
180 struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
181 struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
1053 struct dpu_hw_blk *hw_pp[MAX_CHANNELS_PER_ENC]; in dpu_encoder_virt_atomic_mode_set()
1054 struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC]; in dpu_encoder_virt_atomic_mode_set()
1055 struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC]; in dpu_encoder_virt_atomic_mode_set()
1056 struct dpu_hw_blk *hw_dspp[MAX_CHANNELS_PER_ENC] = { NULL }; in dpu_encoder_virt_atomic_mode_set()
1057 struct dpu_hw_blk *hw_dsc[MAX_CHANNELS_PER_ENC]; in dpu_encoder_virt_atomic_mode_set()
1093 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) in dpu_encoder_virt_atomic_mode_set()
1173 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) { in _dpu_encoder_virt_enable_helper()
1836 struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC]; in dpu_encoder_prep_dsc()
1837 struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC]; in dpu_encoder_prep_dsc()
1845 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) { in dpu_encoder_prep_dsc()
1874 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) in dpu_encoder_prep_dsc()
2021 struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC]; in dpu_encoder_unprep_dsc()
2022 struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC]; in dpu_encoder_unprep_dsc()
2025 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) { in dpu_encoder_unprep_dsc()