msm/adreno/adreno_gpu.h

1 /* SPDX-License-Identifier: GPL-2.0-only */
33  * @enum adreno_family: identify generation and possibly sub-generation
35  * In some cases there are distinct sub-generations within a major revision
37  * necessary sub-generation.
88 	 * @chipids: Table of matching chip-ids
117  *      -----+---------
144 	 * of gpu firmware to linux-firmware, the fw files were
146 	 * android kernel.  But linux-firmware preferred they be
191 	int __ret = -ETIMEDOUT;                            \
208 	WARN_ON_ONCE(gpu->info->family >= ADRENO_6XX_GEN1);  in adreno_patchid()
209 	return gpu->chip_id & 0xff;  in adreno_patchid()
214 	if (WARN_ON_ONCE(!gpu->info))  in adreno_is_revn()
216 	return gpu->info->revn == revn;  in adreno_is_revn()
221 	return gpu->gmu_is_wrapper;  in adreno_has_gmu_wrapper()
226 	if (WARN_ON_ONCE(!gpu->info))  in adreno_is_a2xx()
228 	return gpu->info->family <= ADRENO_2XX_GEN2;  in adreno_is_a2xx()
233 	if (WARN_ON_ONCE(!gpu->info))  in adreno_is_a20x()
235 	return gpu->info->family == ADRENO_2XX_GEN1;  in adreno_is_a20x()
356 	return gpu->info->chip_ids[0] == 0x06030500;  in adreno_is_7c3()
371 	return gpu->info->chip_ids[0] == 0x06090000;  in adreno_is_a690()
377 	if (WARN_ON_ONCE(!gpu->info))  in adreno_is_a630_family()
379 	return gpu->info->family == ADRENO_6XX_GEN1;  in adreno_is_a630_family()
384 	if (WARN_ON_ONCE(!gpu->info))  in adreno_is_a660_family()
386 	return gpu->info->family == ADRENO_6XX_GEN4;  in adreno_is_a660_family()
392 	if (WARN_ON_ONCE(!gpu->info))  in adreno_is_a650_family()
394 	return gpu->info->family >= ADRENO_6XX_GEN3;  in adreno_is_a650_family()
399 	if (WARN_ON_ONCE(!gpu->info))  in adreno_is_a640_family()
401 	return gpu->info->family == ADRENO_6XX_GEN2;  in adreno_is_a640_family()
444  * Common helper function to initialize the default address space for arm-smmu
463  * For a5xx and a6xx targets load the zap shader that is used to pull the GPU
474 	OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF));  in OUT_PKT0()
477 /* no-op packet: */
489 	OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8));  in OUT_PKT3()
530 	return (ring->cur - ring->start) % (MSM_GPU_RINGBUFFER_SZ >> 2);  in get_wptr()
535  * REG_CP_PROTECT_REG(n) - this will block both reads and writes for _len
541  * (0x07-0x0A) the hardware will actually protect (0x04-0x07) which might
559 	readl_poll_timeout((gpu)->mmio + ((addr) << 2), val, cond, \