41 	gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, status);  in a6xx_gmu_irq()
65 	gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, status);  in a6xx_hfi_irq()
146 	gmu_write(gmu, REG_A6XX_GMU_DCVS_ACK_OPTION, 0);  in a6xx_gmu_set_freq()
148 	gmu_write(gmu, REG_A6XX_GMU_DCVS_PERF_SETTING,  in a6xx_gmu_set_freq()
155 	gmu_write(gmu, REG_A6XX_GMU_DCVS_BW_SETTING, 0xff);  in a6xx_gmu_set_freq()
218 	gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 1);  in a6xx_gmu_start()
223 	gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_RESP, 0);  in a6xx_gmu_start()
225 	gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 0);  in a6xx_gmu_start()
241 	gmu_write(gmu, REG_A6XX_GMU_HFI_CTRL_INIT, 1);  in a6xx_gmu_hfi_start()
322 	gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 1 << request);  in a6xx_gmu_set_oob()
335 	gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, 1 << ack);  in a6xx_gmu_set_oob()
355 	gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 1 << bit);  in a6xx_gmu_clear_oob()
367 	gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778000);  in a6xx_sptprac_enable()
392 	gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778001);  in a6xx_sptprac_disable()
408 	gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 0);  in a6xx_gmu_gfx_rail_on()
413 	gmu_write(gmu, REG_A6XX_GMU_GX_VOTE_IDX, vote & 0xff);  in a6xx_gmu_gfx_rail_on()
414 	gmu_write(gmu, REG_A6XX_GMU_MX_VOTE_IDX, (vote >> 8) & 0xff);  in a6xx_gmu_gfx_rail_on()
426 	gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 0);  in a6xx_gmu_notify_slumber()
438 	gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 1);  in a6xx_gmu_notify_slumber()
454 	gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0);  in a6xx_gmu_notify_slumber()
463 	gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1 << 1);  in a6xx_rpmh_start()
482 	gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0);  in a6xx_rpmh_start()
492 	gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1);  in a6xx_rpmh_stop()
499 	gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0);  in a6xx_rpmh_stop()
641 	gmu_write(gmu, REG_A6XX_GMU_SYS_BUS_CONFIG, 0x1);  in a6xx_gmu_power_config()
642 	gmu_write(gmu, REG_A6XX_GMU_ICACHE_CONFIG, 0x1);  in a6xx_gmu_power_config()
643 	gmu_write(gmu, REG_A6XX_GMU_DCACHE_CONFIG, 0x1);  in a6xx_gmu_power_config()
645 	gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0x9c40400);  in a6xx_gmu_power_config()
649 		gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_HYST,  in a6xx_gmu_power_config()
656 		gmu_write(gmu, REG_A6XX_GMU_PWR_COL_SPTPRAC_HYST,  in a6xx_gmu_power_config()
754 		gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF, 1);  in a6xx_gmu_fw_start()
755 		gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF, 1);  in a6xx_gmu_fw_start()
768 		gmu_write(gmu, REG_A6XX_GMU_GENERAL_7, 1);  in a6xx_gmu_fw_start()
779 	gmu_write(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, 0);  in a6xx_gmu_fw_start()
780 	gmu_write(gmu, REG_A6XX_GMU_CM3_BOOT_CONFIG, 0x02);  in a6xx_gmu_fw_start()
783 	gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_ADDR, gmu->hfi.iova);  in a6xx_gmu_fw_start()
784 	gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_INFO, 1);  in a6xx_gmu_fw_start()
786 	gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_RANGE_0,  in a6xx_gmu_fw_start()
793 	gmu_write(gmu, REG_A6XX_GMU_CM3_CFG, 0x4052);  in a6xx_gmu_fw_start()
806 	gmu_write(gmu, REG_A6XX_GMU_HFI_SFR_ADDR, chipid);  in a6xx_gmu_fw_start()
808 	gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_MSG,  in a6xx_gmu_fw_start()
854 	gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~0);  in a6xx_gmu_irq_disable()
855 	gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~0);  in a6xx_gmu_irq_disable()
884 	gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 0);  in a6xx_gmu_force_off()
899 	gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS_CLR, 0x7);  in a6xx_gmu_force_off()
900 	gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0);  in a6xx_gmu_force_off()
906 	gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 1);  in a6xx_gmu_force_off()
978 	gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, ~0);  in a6xx_gmu_resume()
979 	gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~A6XX_GMU_IRQ_MASK);  in a6xx_gmu_resume()
1005 	gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, ~0);  in a6xx_gmu_resume()
1006 	gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~A6XX_HFI_IRQ_MASK);  in a6xx_gmu_resume()