53 		dev_err_ratelimited(gmu->dev, "GMU fence error: 0x%x\n",  in a6xx_gmu_irq()
115 	int ret = 0;  in a6xx_gmu_set_freq()
122 	for (perf_index = 0; perf_index < gmu->nr_gpu_freqs - 1; perf_index++)  in a6xx_gmu_set_freq()
146 	gmu_write(gmu, REG_A6XX_GMU_DCVS_ACK_OPTION, 0);  in a6xx_gmu_set_freq()
149 			((3 & 0xf) << 28) | perf_index);  in a6xx_gmu_set_freq()
155 	gmu_write(gmu, REG_A6XX_GMU_DCVS_BW_SETTING, 0xff);  in a6xx_gmu_set_freq()
209 	val = gmu_read(gmu, REG_A6XX_GMU_CM3_DTCM_START + 0xff8);  in a6xx_gmu_start()
210 	if (val <= 0x20010004) {  in a6xx_gmu_start()
211 		mask = 0xffffffff;  in a6xx_gmu_start()
212 		reset_val = 0xbabeface;  in a6xx_gmu_start()
214 		mask = 0x1ff;  in a6xx_gmu_start()
215 		reset_val = 0x100;  in a6xx_gmu_start()
223 	gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_RESP, 0);  in a6xx_gmu_start()
225 	gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 0);  in a6xx_gmu_start()
330 			"Timeout waiting for GMU OOB set %s: 0x%x\n",  in a6xx_gmu_set_oob()
365 		return 0;  in a6xx_sptprac_enable()
367 	gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778000);  in a6xx_sptprac_enable()
370 		(val & 0x38) == 0x28, 1, 100);  in a6xx_sptprac_enable()
373 		DRM_DEV_ERROR(gmu->dev, "Unable to power on SPTPRAC: 0x%x\n",  in a6xx_sptprac_enable()
377 	return 0;  in a6xx_sptprac_enable()
390 	gmu_rmw(gmu, REG_A6XX_GPU_CC_GX_GDSCR, 0, (1 << 11));  in a6xx_sptprac_disable()
392 	gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778001);  in a6xx_sptprac_disable()
395 		(val & 0x04), 100, 10000);  in a6xx_sptprac_disable()
398 		DRM_DEV_ERROR(gmu->dev, "failed to power off SPTPRAC: 0x%x\n",  in a6xx_sptprac_disable()
408 	gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 0);  in a6xx_gmu_gfx_rail_on()
413 	gmu_write(gmu, REG_A6XX_GMU_GX_VOTE_IDX, vote & 0xff);  in a6xx_gmu_gfx_rail_on()
414 	gmu_write(gmu, REG_A6XX_GMU_MX_VOTE_IDX, (vote >> 8) & 0xff);  in a6xx_gmu_gfx_rail_on()
426 	gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 0);  in a6xx_gmu_notify_slumber()
446 			!= 0x0f) {  in a6xx_gmu_notify_slumber()
454 	gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0);  in a6xx_gmu_notify_slumber()
482 	gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0);  in a6xx_rpmh_start()
484 	return 0;  in a6xx_rpmh_start()
499 	gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0);  in a6xx_rpmh_stop()
526 		pdc_address_offset = 0x30090;  in a6xx_gmu_rpmh_init()
528 		pdc_address_offset = 0x300a0;  in a6xx_gmu_rpmh_init()
530 		pdc_address_offset = 0x30080;  in a6xx_gmu_rpmh_init()
543 	gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA, 0);  in a6xx_gmu_rpmh_init()
544 	gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR, 0);  in a6xx_gmu_rpmh_init()
545 	gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 2, 0);  in a6xx_gmu_rpmh_init()
546 	gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 2, 0);  in a6xx_gmu_rpmh_init()
547 	gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 4, 0x80000000);  in a6xx_gmu_rpmh_init()
548 	gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 4, 0);  in a6xx_gmu_rpmh_init()
549 	gmu_write_rscc(gmu, REG_A6XX_RSCC_OVERRIDE_START_ADDR, 0);  in a6xx_gmu_rpmh_init()
550 	gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_SEQ_START_ADDR, 0x4520);  in a6xx_gmu_rpmh_init()
551 	gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_LO, 0x4510);  in a6xx_gmu_rpmh_init()
552 	gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_HI, 0x4514);  in a6xx_gmu_rpmh_init()
556 		gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xeaaae5a0);  in a6xx_gmu_rpmh_init()
557 		gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xe1a1ebab);  in a6xx_gmu_rpmh_init()
558 		gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e0a581);  in a6xx_gmu_rpmh_init()
559 		gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xecac82e2);  in a6xx_gmu_rpmh_init()
560 		gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020edad);  in a6xx_gmu_rpmh_init()
562 		gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xa7a506a0);  in a6xx_gmu_rpmh_init()
563 		gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xa1e6a6e7);  in a6xx_gmu_rpmh_init()
564 		gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e081e1);  in a6xx_gmu_rpmh_init()
565 		gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xe9a982e2);  in a6xx_gmu_rpmh_init()
566 		gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020e8a8);  in a6xx_gmu_rpmh_init()
573 	pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0, 0xfebea1e1);  in a6xx_gmu_rpmh_init()
574 	pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 1, 0xa5a4a3a2);  in a6xx_gmu_rpmh_init()
575 	pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 2, 0x8382a6e0);  in a6xx_gmu_rpmh_init()
576 	pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 3, 0xbce3e284);  in a6xx_gmu_rpmh_init()
577 	pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 4, 0x002081fc);  in a6xx_gmu_rpmh_init()
581 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK, 0);  in a6xx_gmu_rpmh_init()
582 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CONTROL, 0);  in a6xx_gmu_rpmh_init()
583 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID, 0x10108);  in a6xx_gmu_rpmh_init()
584 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR, 0x30010);  in a6xx_gmu_rpmh_init()
586 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 4, 0x10108);  in a6xx_gmu_rpmh_init()
587 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 4, 0x30000);  in a6xx_gmu_rpmh_init()
588 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 4, 0x0);  in a6xx_gmu_rpmh_init()
590 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 8, 0x10108);  in a6xx_gmu_rpmh_init()
592 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 8, 0x0);  in a6xx_gmu_rpmh_init()
595 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK, 0);  in a6xx_gmu_rpmh_init()
596 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CONTROL, 0);  in a6xx_gmu_rpmh_init()
597 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID, 0x10108);  in a6xx_gmu_rpmh_init()
598 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR, 0x30010);  in a6xx_gmu_rpmh_init()
601 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 4, 0x10108);  in a6xx_gmu_rpmh_init()
602 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 4, 0x30000);  in a6xx_gmu_rpmh_init()
605 		pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x2);  in a6xx_gmu_rpmh_init()
607 		pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x3);  in a6xx_gmu_rpmh_init()
608 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 8, 0x10108);  in a6xx_gmu_rpmh_init()
610 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 8, 0x3);  in a6xx_gmu_rpmh_init()
614 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_SEQ_START_ADDR, 0);  in a6xx_gmu_rpmh_init()
615 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_ENABLE_PDC, 0x80000001);  in a6xx_gmu_rpmh_init()
631  * hysteresis which is set at 0x1680 cycles (300 us).  The higher 16 bits are
632  * for the shorter hysteresis that happens after main - this is 0xa (.5 us)
635 #define GMU_PWR_COL_HYST 0x000a1680
641 	gmu_write(gmu, REG_A6XX_GMU_SYS_BUS_CONFIG, 0x1);  in a6xx_gmu_power_config()
642 	gmu_write(gmu, REG_A6XX_GMU_ICACHE_CONFIG, 0x1);  in a6xx_gmu_power_config()
643 	gmu_write(gmu, REG_A6XX_GMU_DCACHE_CONFIG, 0x1);  in a6xx_gmu_power_config()
645 	gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0x9c40400);  in a6xx_gmu_power_config()
651 		gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0,  in a6xx_gmu_power_config()
658 		gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0,  in a6xx_gmu_power_config()
664 	gmu_rmw(gmu, REG_A6XX_GMU_RPMH_CTRL, 0,  in a6xx_gmu_power_config()
698 	u32 itcm_base = 0x00000000;  in a6xx_gmu_fw_load()
699 	u32 dtcm_base = 0x00040000;  in a6xx_gmu_fw_load()
702 		dtcm_base = 0x10004000;  in a6xx_gmu_fw_load()
706 		if (fw_image->size > 0x8000) {  in a6xx_gmu_fw_load()
714 		return 0;  in a6xx_gmu_fw_load()
721 		if (blk->size == 0)  in a6xx_gmu_fw_load()
738 				"failed to match fw block (addr=%.8x size=%d data[0]=%.8x)\n",  in a6xx_gmu_fw_load()
739 				blk->addr, blk->size, blk->data[0]);  in a6xx_gmu_fw_load()
743 	return 0;  in a6xx_gmu_fw_load()
779 	gmu_write(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, 0);  in a6xx_gmu_fw_start()
780 	gmu_write(gmu, REG_A6XX_GMU_CM3_BOOT_CONFIG, 0x02);  in a6xx_gmu_fw_start()
787 		(1 << 31) | (0xa << 18) | (0xa0));  in a6xx_gmu_fw_start()
793 	gmu_write(gmu, REG_A6XX_GMU_CM3_CFG, 0x4052);  in a6xx_gmu_fw_start()
802 	chipid  = adreno_gpu->chip_id & 0xffff0000;  in a6xx_gmu_fw_start()
803 	chipid |= (adreno_gpu->chip_id << 4) & 0xf000; /* minor */  in a6xx_gmu_fw_start()
804 	chipid |= (adreno_gpu->chip_id << 8) & 0x0f00; /* patchid */  in a6xx_gmu_fw_start()
838 	return 0;  in a6xx_gmu_fw_start()
854 	gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~0);  in a6xx_gmu_irq_disable()
855 	gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~0);  in a6xx_gmu_irq_disable()
884 	gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 0);  in a6xx_gmu_force_off()
899 	gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS_CLR, 0x7);  in a6xx_gmu_force_off()
900 	gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0);  in a6xx_gmu_force_off()
923 	gmu->freq = 0; /* so a6xx_gmu_set_freq() doesn't exit early */  in a6xx_gmu_set_initial_freq()
978 	gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, ~0);  in a6xx_gmu_resume()
1005 	gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, ~0);  in a6xx_gmu_resume()
1052 	if (val != 0xf) {  in a6xx_gmu_shutdown()
1082 				"Unable to slumber GMU: status = 0%x/0%x\n",  in a6xx_gmu_shutdown()
1106 		return 0;  in a6xx_gmu_stop()
1132 	return 0;  in a6xx_gmu_stop()
1160 		range_start = 0x60000000 + PAGE_SIZE; /* skip dummy page */  in a6xx_gmu_memory_alloc()
1161 		range_end = 0x80000000;  in a6xx_gmu_memory_alloc()
1186 	return 0;  in a6xx_gmu_memory_alloc()
1193 	mmu = msm_iommu_new(gmu->dev, 0);  in a6xx_gmu_memory_probe()
1199 	gmu->aspace = msm_gem_address_space_create(mmu, "gmu", 0x0, 0x80000000);  in a6xx_gmu_memory_probe()
1203 	return 0;  in a6xx_gmu_memory_probe()
1214 		return 0;  in a6xx_gmu_get_arc_level()
1218 		return 0;  in a6xx_gmu_get_arc_level()
1254 	for (i = 0; i < freqs_count; i++) {  in a6xx_gmu_rpmh_arc_votes_init()
1255 		u8 pindex = 0, sindex = 0;  in a6xx_gmu_rpmh_arc_votes_init()
1259 		for (j = 0; j < pri_count; j++) {  in a6xx_gmu_rpmh_arc_votes_init()
1271 			for (j = 0; j < pri_count; j++)  in a6xx_gmu_rpmh_arc_votes_init()
1282 		for (j = 0; j < sec_count; j++) {  in a6xx_gmu_rpmh_arc_votes_init()
1292 		votes[i] = ((pri[pindex] & 0xffff) << 16) |  in a6xx_gmu_rpmh_arc_votes_init()
1296 	return 0;  in a6xx_gmu_rpmh_arc_votes_init()
1328 	int i, index = 0;  in a6xx_gmu_build_freq_table()
1341 	freqs[index++] = 0;  in a6xx_gmu_build_freq_table()
1343 	for (i = 0; i < count; i++) {  in a6xx_gmu_build_freq_table()
1361 	int ret = 0;  in a6xx_gmu_pwrlevels_probe()
1404 	return 0;  in a6xx_gmu_clocks_probe()
1499 	return 0;  in cxpd_notifier_cb()
1551 	return 0;  in a6xx_gmu_wrapper_init()
1603 					    0x60400000, "debug");  in a6xx_gmu_init()
1612 				    0x60000000, "dummy");  in a6xx_gmu_init()
1619 			SZ_16M - SZ_16K, 0x04000, "icache");  in a6xx_gmu_init()
1630 			SZ_256K - SZ_16K, 0x04000, "icache");  in a6xx_gmu_init()
1635 			SZ_256K - SZ_16K, 0x44000, "dcache");  in a6xx_gmu_init()
1643 		ret = a6xx_gmu_memory_alloc(gmu, &gmu->debug, SZ_16K, 0, "debug");  in a6xx_gmu_init()
1649 	ret = a6xx_gmu_memory_alloc(gmu, &gmu->log, SZ_16K, 0, "log");  in a6xx_gmu_init()
1654 	ret = a6xx_gmu_memory_alloc(gmu, &gmu->hfi, SZ_16K, 0, "hfi");  in a6xx_gmu_init()
1672 		gmu->rscc = gmu->mmio + 0x23000;  in a6xx_gmu_init()
1679 	if (gmu->hfi_irq < 0 || gmu->gmu_irq < 0) {  in a6xx_gmu_init()
1717 	return 0;  in a6xx_gmu_init()