Lines Matching refs:handle
314 int (*pre_set_power_state)(void *handle);
315 int (*set_power_state)(void *handle);
316 void (*post_set_power_state)(void *handle);
317 void (*display_configuration_changed)(void *handle);
318 void (*print_power_state)(void *handle, void *ps);
319 bool (*vblank_too_short)(void *handle);
320 void (*enable_bapm)(void *handle, bool enable);
321 int (*check_state_equal)(void *handle,
326 int (*set_fan_control_mode)(void *handle, u32 mode);
327 int (*get_fan_control_mode)(void *handle, u32 *fan_mode);
328 int (*set_fan_speed_pwm)(void *handle, u32 speed);
329 int (*get_fan_speed_pwm)(void *handle, u32 *speed);
330 int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask);
331 int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf);
332 int (*emit_clock_levels)(void *handle, enum pp_clock_type type, char *buf, int *offset);
333 int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level);
334 int (*get_sclk_od)(void *handle);
335 int (*set_sclk_od)(void *handle, uint32_t value);
336 int (*get_mclk_od)(void *handle);
337 int (*set_mclk_od)(void *handle, uint32_t value);
338 int (*read_sensor)(void *handle, int idx, void *value, int *size);
339 int (*get_apu_thermal_limit)(void *handle, uint32_t *limit);
340 int (*set_apu_thermal_limit)(void *handle, uint32_t limit);
341 enum amd_dpm_forced_level (*get_performance_level)(void *handle);
342 enum amd_pm_state_type (*get_current_power_state)(void *handle);
343 int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm);
344 int (*set_fan_speed_rpm)(void *handle, uint32_t rpm);
345 int (*get_pp_num_states)(void *handle, struct pp_states_info *data);
346 int (*get_pp_table)(void *handle, char **table);
347 int (*set_pp_table)(void *handle, const char *buf, size_t size);
348 void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m);
349 int (*switch_power_profile)(void *handle, enum PP_SMC_POWER_PROFILE type, bool en);
351 struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx);
352 int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id,
354 int (*load_firmware)(void *handle);
355 int (*wait_for_fw_loading_complete)(void *handle);
356 int (*set_powergating_by_smu)(void *handle,
358 int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id);
359 int (*set_power_limit)(void *handle, uint32_t n);
360 int (*get_power_limit)(void *handle, uint32_t *limit,
363 int (*get_power_profile_mode)(void *handle, char *buf);
364 int (*set_power_profile_mode)(void *handle, long *input, uint32_t size);
365 int (*set_fine_grain_clk_vol)(void *handle, uint32_t type, long *input, uint32_t size);
366 int (*odn_edit_dpm_table)(void *handle, enum PP_OD_DPM_TABLE_COMMAND type,
368 int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state);
369 int (*smu_i2c_bus_access)(void *handle, bool acquire);
370 int (*gfx_state_change_set)(void *handle, uint32_t state);
372 u32 (*get_sclk)(void *handle, bool low);
373 u32 (*get_mclk)(void *handle, bool low);
374 int (*display_configuration_change)(void *handle,
376 int (*get_display_power_level)(void *handle,
378 int (*get_current_clocks)(void *handle,
380 int (*get_clock_by_type)(void *handle,
383 int (*get_clock_by_type_with_latency)(void *handle,
386 int (*get_clock_by_type_with_voltage)(void *handle,
389 int (*set_watermarks_for_clocks_ranges)(void *handle,
391 int (*display_clock_voltage_request)(void *handle,
393 int (*get_display_mode_validation_clocks)(void *handle,
395 int (*notify_smu_enable_pwe)(void *handle);
396 int (*enable_mgpu_fan_boost)(void *handle);
397 int (*set_active_display_count)(void *handle, uint32_t count);
398 int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock);
399 int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock);
400 int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock);
401 int (*get_asic_baco_capability)(void *handle, bool *cap);
402 int (*get_asic_baco_state)(void *handle, int *state);
403 int (*set_asic_baco_state)(void *handle, int state);
404 int (*get_ppfeature_status)(void *handle, char *buf);
405 int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks);
406 int (*asic_reset_mode_2)(void *handle);
407 int (*asic_reset_enable_gfx_features)(void *handle);
408 int (*set_df_cstate)(void *handle, enum pp_df_cstate state);
409 int (*set_xgmi_pstate)(void *handle, uint32_t pstate);
410 ssize_t (*get_gpu_metrics)(void *handle, void **table);
411 int (*set_watermarks_for_clock_ranges)(void *handle,
413 int (*display_disable_memory_clock_switch)(void *handle,
415 int (*get_max_sustainable_clocks_by_dc)(void *handle,
417 int (*get_uclk_dpm_states)(void *handle,
420 int (*get_dpm_clock_table)(void *handle,
422 int (*get_smu_prv_buf_details)(void *handle, void **addr, size_t *size);
423 void (*pm_compute_clocks)(void *handle);