33 static void jh71x0_clk_reg_rmw(struct jh71x0_clk *clk, u32 mask, u32 value)  in jh71x0_clk_reg_rmw()  argument
40 	value |= readl_relaxed(reg) & ~mask;  in jh71x0_clk_reg_rmw()
41 	writel_relaxed(value, reg);  in jh71x0_clk_reg_rmw()
154 	u32 value = ((div100 % 100) << JH71X0_CLK_FRAC_SHIFT) | (div100 / 100);  in jh71x0_clk_frac_set_rate()  local
156 	jh71x0_clk_reg_rmw(clk, JH71X0_CLK_DIV_MASK, value);  in jh71x0_clk_frac_set_rate()
163 	u32 value = jh71x0_clk_reg_get(clk);  in jh71x0_clk_get_parent()  local
165 	return (value & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT;  in jh71x0_clk_get_parent()
171 	u32 value = (u32)index << JH71X0_CLK_MUX_SHIFT;  in jh71x0_clk_set_parent()  local
173 	jh71x0_clk_reg_rmw(clk, JH71X0_CLK_MUX_MASK, value);  in jh71x0_clk_set_parent()
180 	u32 value = jh71x0_clk_reg_get(clk);  in jh71x0_clk_get_phase()  local
182 	return (value & JH71X0_CLK_INVERT) ? 180 : 0;  in jh71x0_clk_get_phase()
188 	u32 value;  in jh71x0_clk_set_phase()  local
191 		value = 0;  in jh71x0_clk_set_phase()
193 		value = JH71X0_CLK_INVERT;  in jh71x0_clk_set_phase()
197 	jh71x0_clk_reg_rmw(clk, JH71X0_CLK_INVERT, value);  in jh71x0_clk_set_phase()