118 #define imx_clk_gate_exclusive(name, parent, reg, shift, exclusive_mask) \  argument
119 	to_clk(imx_clk_hw_gate_exclusive(name, parent, reg, shift, exclusive_mask))
124 #define imx_clk_fixed_factor(name, parent, mult, div) \  argument
125 	to_clk(imx_clk_hw_fixed_factor(name, parent, mult, div))
127 #define imx_clk_divider(name, parent, reg, shift, width) \  argument
128 	to_clk(imx_clk_hw_divider(name, parent, reg, shift, width))
130 #define imx_clk_divider_flags(name, parent, reg, shift, width, flags) \  argument
131 	to_clk(imx_clk_hw_divider_flags(name, parent, reg, shift, width, flags))
133 #define imx_clk_gate(name, parent, reg, shift) \  argument
134 	to_clk(imx_clk_hw_gate(name, parent, reg, shift))
136 #define imx_clk_gate_dis(name, parent, reg, shift) \  argument
137 	to_clk(imx_clk_hw_gate_dis(name, parent, reg, shift))
139 #define imx_clk_gate2(name, parent, reg, shift) \  argument
140 	to_clk(imx_clk_hw_gate2(name, parent, reg, shift))
142 #define imx_clk_gate2_cgr(name, parent, reg, shift, cgr_val) \  argument
143 	to_clk(__imx_clk_hw_gate2(name, parent, reg, shift, cgr_val, 0, NULL))
145 #define imx_clk_gate2_flags(name, parent, reg, shift, flags) \  argument
146 	to_clk(imx_clk_hw_gate2_flags(name, parent, reg, shift, flags))
157 #define imx_clk_pllv1(type, name, parent, base) \  argument
158 	to_clk(imx_clk_hw_pllv1(type, name, parent, base))
160 #define imx_clk_pllv2(name, parent, base) \  argument
161 	to_clk(imx_clk_hw_pllv2(name, parent, base))
163 #define imx_clk_hw_gate(name, parent, reg, shift) \  argument
164 	imx_clk_hw_gate_flags(name, parent, reg, shift, 0)
166 #define imx_clk_hw_gate2(name, parent, reg, shift) \  argument
167 	imx_clk_hw_gate2_flags(name, parent, reg, shift, 0)
169 #define imx_clk_hw_gate_dis(name, parent, reg, shift) \  argument
170 	imx_clk_hw_gate_dis_flags(name, parent, reg, shift, 0)
172 #define imx_clk_hw_gate_dis_flags(name, parent, reg, shift, flags) \  argument
173 	__imx_clk_hw_gate(name, parent, reg, shift, flags, CLK_GATE_SET_TO_DISABLE)
175 #define imx_clk_hw_gate_flags(name, parent, reg, shift, flags) \  argument
176 	__imx_clk_hw_gate(name, parent, reg, shift, flags, 0)
178 #define imx_clk_hw_gate2_flags(name, parent, reg, shift, flags) \  argument
179 	__imx_clk_hw_gate2(name, parent, reg, shift, 0x3, flags, NULL)
181 #define imx_clk_hw_gate2_shared(name, parent, reg, shift, shared_count) \  argument
182 	__imx_clk_hw_gate2(name, parent, reg, shift, 0x3, 0, shared_count)
184 #define imx_clk_hw_gate2_shared2(name, parent, reg, shift, shared_count) \  argument
185 	__imx_clk_hw_gate2(name, parent, reg, shift, 0x3, CLK_OPS_PARENT_ENABLE, shared_count)
187 #define imx_clk_hw_gate3(name, parent, reg, shift) \  argument
188 	imx_clk_hw_gate3_flags(name, parent, reg, shift, 0)
190 #define imx_clk_hw_gate3_flags(name, parent, reg, shift, flags) \  argument
191 	__imx_clk_hw_gate(name, parent, reg, shift, flags | CLK_OPS_PARENT_ENABLE, 0)
193 #define imx_clk_hw_gate4(name, parent, reg, shift) \  argument
194 	imx_clk_hw_gate4_flags(name, parent, reg, shift, 0)
196 #define imx_clk_hw_gate4_flags(name, parent, reg, shift, flags) \  argument
197 	imx_clk_hw_gate2_flags(name, parent, reg, shift, flags | CLK_OPS_PARENT_ENABLE)
214 #define imx_clk_hw_divider(name, parent, reg, shift, width) \  argument
215 	__imx_clk_hw_divider(name, parent, reg, shift, width, CLK_SET_RATE_PARENT)
217 #define imx_clk_hw_divider2(name, parent, reg, shift, width) \  argument
218 	__imx_clk_hw_divider(name, parent, reg, shift, width, \
221 #define imx_clk_hw_divider_flags(name, parent, reg, shift, width, flags) \  argument
222 	__imx_clk_hw_divider(name, parent, reg, shift, width, flags)
232 		const char *parent, void __iomem *base);
234 struct clk_hw *imx_clk_hw_pllv2(const char *name, const char *parent,
243 				u8 parent, u8 bypass1, u8 bypass2,
300 struct clk_hw *imx_clk_hw_gate_exclusive(const char *name, const char *parent,
329 struct clk_hw *imx_clk_hw_fixup_divider(const char *name, const char *parent,
350 		const char *parent, unsigned int mult, unsigned int div)  in imx_clk_hw_fixed_factor()  argument
352 	return clk_hw_register_fixed_factor(NULL, name, parent,  in imx_clk_hw_fixed_factor()
357 						const char *parent,  in imx_clk_hw_divider_closest()  argument
361 	return clk_hw_register_divider(NULL, name, parent, 0,  in imx_clk_hw_divider_closest()
366 						   const char *parent,  in __imx_clk_hw_divider()  argument
370 	return clk_hw_register_divider(NULL, name, parent, flags,  in __imx_clk_hw_divider()
374 static inline struct clk_hw *__imx_clk_hw_gate(const char *name, const char *parent,  in __imx_clk_hw_gate()  argument
379 	return clk_hw_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,  in __imx_clk_hw_gate()
383 static inline struct clk_hw *__imx_clk_hw_gate2(const char *name, const char *parent,  in __imx_clk_hw_gate2()  argument
388 	return clk_hw_register_gate2(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,  in __imx_clk_hw_gate2()