163 	u32 stat;  in waitfor_idle()  local
165 	stat = readl(SAR_REG_STAT);  in waitfor_idle()
166 	while (stat & SAR_STAT_CMDBZ)  in waitfor_idle()
167 		stat = readl(SAR_REG_STAT);  in waitfor_idle()
1018 	u32 stat;  in dequeue_rx()  local
1021 	stat = le32_to_cpu(rsqe->word_4);  in dequeue_rx()
1023 	if (stat & SAR_RSQE_IDLE) {  in dequeue_rx()
1073 		for (i = (stat & SAR_RSQE_CELLCNT); i; i--) {  in dequeue_rx()
1089 			aal0 |= (stat & SAR_RSQE_EPDU) ? 0x00000002 : 0;  in dequeue_rx()
1090 			aal0 |= (stat & SAR_RSQE_CLP)  ? 0x00000001 : 0;  in dequeue_rx()
1113 	skb->len = (stat & SAR_RSQE_CELLCNT) * ATM_CELL_PAYLOAD;  in dequeue_rx()
1120 	if (stat & SAR_RSQE_EPDU) {  in dequeue_rx()
1139 		if (stat & SAR_RSQE_CRC) {  in dequeue_rx()
1410 	u32 conn, stat;  in idt77252_tx()  local
1424 	stat = le32_to_cpu(tsqe->word_2);  in idt77252_tx()
1426 	if (stat & SAR_TSQE_INVALID)  in idt77252_tx()
1434 		switch (stat & SAR_TSQE_TYPE) {  in idt77252_tx()
1443 			if (SAR_TSQE_TAG(stat) == 0x10) {  in idt77252_tx()
1518 		stat = le32_to_cpu(tsqe->word_2);  in idt77252_tx()
1520 	} while (!(stat & SAR_TSQE_INVALID));  in idt77252_tx()
2711 	u32 stat;  in idt77252_interrupt()  local
2713 	stat = readl(SAR_REG_STAT) & 0xffff;  in idt77252_interrupt()
2714 	if (!stat)	/* no interrupt for us */  in idt77252_interrupt()
2722 	writel(stat, SAR_REG_STAT);	/* reset interrupt */  in idt77252_interrupt()
2724 	if (stat & SAR_STAT_TSIF) {	/* entry written to TSQ  */  in idt77252_interrupt()
2729 	if (stat & SAR_STAT_TXICP) {	/* Incomplete CS-PDU has  */  in idt77252_interrupt()
2736 	if (stat & SAR_STAT_TSQF) {	/* TSQ 7/8 full           */  in idt77252_interrupt()
2741 	if (stat & SAR_STAT_TMROF) {	/* Timer overflow         */  in idt77252_interrupt()
2747 	if (stat & SAR_STAT_EPDU) {	/* Got complete CS-PDU    */  in idt77252_interrupt()
2752 	if (stat & SAR_STAT_RSQAF) {	/* RSQ is 7/8 full        */  in idt77252_interrupt()
2757 	if (stat & SAR_STAT_RSQF) {	/* RSQ is full            */  in idt77252_interrupt()
2762 	if (stat & SAR_STAT_RAWCF) {	/* Raw cell received      */  in idt77252_interrupt()
2768 	if (stat & SAR_STAT_PHYI) {	/* PHY device interrupt   */  in idt77252_interrupt()
2775 	if (stat & (SAR_STAT_FBQ0A | SAR_STAT_FBQ1A |  in idt77252_interrupt()
2780 		INTPRINTK("%s: FBQA: %04x\n", card->name, stat);  in idt77252_interrupt()
2782 		if (stat & SAR_STAT_FBQ0A)  in idt77252_interrupt()
2784 		if (stat & SAR_STAT_FBQ1A)  in idt77252_interrupt()
2786 		if (stat & SAR_STAT_FBQ2A)  in idt77252_interrupt()
2788 		if (stat & SAR_STAT_FBQ3A)  in idt77252_interrupt()
2804 	u32 stat;  in idt77252_softint()  local
2808 		stat = readl(SAR_REG_STAT) >> 16;  in idt77252_softint()
2810 		if ((stat & 0x0f) < SAR_FBQ0_HIGH) {  in idt77252_softint()
2815 		stat >>= 4;  in idt77252_softint()
2816 		if ((stat & 0x0f) < SAR_FBQ1_HIGH) {  in idt77252_softint()
2821 		stat >>= 4;  in idt77252_softint()
2822 		if ((stat & 0x0f) < SAR_FBQ2_HIGH) {  in idt77252_softint()
2827 		stat >>= 4;  in idt77252_softint()
2828 		if ((stat & 0x0f) < SAR_FBQ3_HIGH) {  in idt77252_softint()