Lines Matching refs:a4

171 	extui	a0, a4, INSN_OP0, 4	# get insn.op0 nibble
178 	bbsi.l	a4, OP1_SI_BIT + INSN_OP1, .Linvalid_instruction
203 	extui	a5, a4, INSN_OP1, 4
233 	extui	a5, a4, INSN_OP0, 4	# get insn.op0 nibble
241 	_bbci.l	a4, OP1_SI_BIT + INSN_OP1, .Lload
248 	extui	a6, a4, INSN_T, 4	# get source register
273 	extui	a5, a4, INSN_OP0, 4
281 	extui	a5, a4, INSN_OP1, 4
302 	extui	a4, a4, INSN_T, 4	# extract target register
304 	addx8	a4, a4, a5
305 	jx	a4			# jump to entry for target register
351 	movi	a4, 0
353 	s32i	a4, a3, EXC_TABLE_FIXUP
362 	l32i	a4, a2, PT_AREG4
377 	# a7: instruction pointer, a4: instruction, a3: value
384 	extui	a5, a4, INSN_OP0, 4	# extract OP0
393 	extui	a5, a4, INSN_OP1, 4	# extract OP1
404 	movi	a4, ~3
405 	and	a4, a4, a8		# align memory address
411 	addi	a4, a4, 8
418 	l32e	a5, a4, -8
420 	l32i	a5, a4, 0		# load lower address word
426 	s32e	a5, a4, -8
427 	l32e	a8, a4, -4
429 	s32i	a5, a4, 0		# store
430 	l32i	a8, a4, 4		# same for upper address word
436 	s32e	a6, a4, -4
438 	s32i	a6, a4, 4
444 	rsr	a4, lend		# check if we reached LEND
445 	bne	a7, a4, 1f
446 	rsr	a4, lcount		# and LCOUNT != 0
447 	beqz	a4, 1f
448 	addi	a4, a4, -1		# decrement LCOUNT and set
450 	wsr	a4, lcount
456 	rsr	a4, icountlevel
457 	beqz	a4, 1f
458 	bgeui	a4, LOCKLEVEL + 1, 1f
459 	rsr	a4, icount
460 	addi	a4, a4, 1
461 	wsr	a4, icount
463 	movi	a4, 0
465 	s32i	a4, a3, EXC_TABLE_FIXUP
474 	l32i	a4, a2, PT_AREG4
490 	s32i	a4, a2, PT_AREG4
496 	rsr	a4, depc
497 	s32i	a4, a2, PT_AREG2
503 	movi	a4, fast_unaligned_fixup
504 	s32i	a4, a3, EXC_TABLE_FIXUP
529 	l32i	a4, a3, 0	# load 2 words
533 	__src_b	a4, a4, a5	# a4 has the instruction
548 	l32i	a4, a2, PT_SAR
550 	wsr	a4, sar
552 	l32i	a4, a2, PT_AREG4