xtensa: fix unaligned and load/store configuration interaction

Unaligned exception handler is needed in configurations with hardware
support for unaligned access when the load/store exception handle

xtensa: fix unaligned and load/store configuration interaction

Unaligned exception handler is needed in configurations with hardware
support for unaligned access when the load/store exception handler is
enabled because such configurations would still raise an exception on
unaligned access through the instruction bus.

Fixes: f29cf77609cc ("xtensa: add load/store exception handler")
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

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xtensa: add load/store exception handler

Memory attached to instruction bus of the xtensa CPU is only accessible
for a limited subset of opcodes. Other opcodes generate an exception
with the load/st

xtensa: add load/store exception handler

Memory attached to instruction bus of the xtensa CPU is only accessible
for a limited subset of opcodes. Other opcodes generate an exception
with the load/store error cause code. This property complicates use of
such systems. Provide a handler that recognizes and transparently fixes
such exceptions. The following opcodes are recognized when used outside
of FLIX bundles: l32i, l32i.n, l16ui, l16si, l8ui.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

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xtensa: rearrange unaligned exception handler

- extract initialization part of the exception handler into a separate
function.
- use single label for invalid instruction instead of two labels, one

xtensa: rearrange unaligned exception handler

- extract initialization part of the exception handler into a separate
function.
- use single label for invalid instruction instead of two labels, one
for load and one for store, at one place.
- use sext instruction for sign extension when available.
- store SAR on the stack instead of in a0.
- replace numeric labels for load and store writeback with .Lload_w and
.Lstore_w respectively.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

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xtensa: use register window specific opcodes only when present

xtensa core may be configured without register windows support, don't
use register window specific opcodes in that case. Use window reg

xtensa: use register window specific opcodes only when present

xtensa core may be configured without register windows support, don't
use register window specific opcodes in that case. Use window register
specific opcodes to initialize hardware or reset core to a known state
regardless of the chosen ABI.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

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xtensa: clean up word alignment macros in assembly code

Remove duplicate definitions of ALIGN/src_b/__src_b and SSA8/ssa8/__ssa8
from assembly sources and put single definition into asm/asmmacro.h

xtensa: clean up word alignment macros in assembly code

Remove duplicate definitions of ALIGN/src_b/__src_b and SSA8/ssa8/__ssa8
from assembly sources and put single definition into asm/asmmacro.h

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

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xtensa: build kernel with text-section-literals

vmlinux.lds.S doesn't do anything special with literals, so instead of
keeping them separate put them into the corresponding text sections.
Drop expli

xtensa: build kernel with text-section-literals

vmlinux.lds.S doesn't do anything special with literals, so instead of
keeping them separate put them into the corresponding text sections.
Drop explicit .literal sections from the vmlinux.lds.S, use standard
section macros. Mark literal pool locations in the assembly sources.
Unfortunately assembler doesn't put literals into .init sections and
external libgcc may still have .literal sections, so sed transformation
to the linker script is still needed.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

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xtensa: allow single-stepping through unaligned load/store

Update icount when icountlevel is non-zero but not greater than EXCM level
when load/store instruction is successfully emulated. This allow

xtensa: allow single-stepping through unaligned load/store

Update icount when icountlevel is non-zero but not greater than EXCM level
when load/store instruction is successfully emulated. This allows
single-stepping over such instruction in userspace debugger.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

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xtensa: move invalid unaligned instruction handler closer to its users

With this change a threaded jump from .Linvalid_instruction_load to
.Linvalid_instruction can be removed and more code may be a

xtensa: move invalid unaligned instruction handler closer to its users

With this change a threaded jump from .Linvalid_instruction_load to
.Linvalid_instruction can be removed and more code may be added to
common load/store exit path.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

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xtensa: make fast_unaligned store restartable

fast_unaligned may encounter DTLB miss or SEGFAULT during the store
emulation. Don't update epc1 and lcount until after the store emulation
is complete,

xtensa: make fast_unaligned store restartable

fast_unaligned may encounter DTLB miss or SEGFAULT during the store
emulation. Don't update epc1 and lcount until after the store emulation
is complete, so that the faulting store instruction could be replayed.
Remove duplicate code handling zero overhead loops and calculate new
epc1 and lcount in one place.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

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xtensa: add double exception fixup handler for fast_unaligned

fast_unaligned_fixup restores user registers and runs normal exception
handler in the current stack frame. Unaligned load/store is retri

xtensa: add double exception fixup handler for fast_unaligned

fast_unaligned_fixup restores user registers and runs normal exception
handler in the current stack frame. Unaligned load/store is retried
after that.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

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xtensa: fix kernel/user jump out of fast_unaligned

Use correct register (a0, just read from the PS) to check user mode bit.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

xtensa: keep a3 and excsave1 on entry to exception handlers

Based on the SMP patch by Joe Taylor and subsequent fixes.
Preserve exception table pointer (normally stored in excsave1 SR) as it
cannot

xtensa: keep a3 and excsave1 on entry to exception handlers

Based on the SMP patch by Joe Taylor and subsequent fixes.
Preserve exception table pointer (normally stored in excsave1 SR) as it
cannot be easily restored in SMP environment.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>

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xtensa: clean up files to make them code-style compliant

Remove heading and trailing spaces, trim trailing lines, and wrap lines
that are longer than 80 characters.

Signed-off-by: Chris Zankel <chr

xtensa: clean up files to make them code-style compliant

Remove heading and trailing spaces, trim trailing lines, and wrap lines
that are longer than 80 characters.

Signed-off-by: Chris Zankel <chris@zankel.net>

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xtensa: provide proper assembler function boundaries with ENDPROC()

Use ENDPROC() to mark the end of assembler functions.

Signed-off-by: Chris Zankel <chris@zankel.net>

xtensa: reorganize SR referencing

- reference SRs by names where possible, not by numbers;
- get rid of __stringify around SR names where possible;
- remove unneeded SR names from asm/regs.h;
- add

xtensa: reorganize SR referencing

- reference SRs by names where possible, not by numbers;
- get rid of __stringify around SR names where possible;
- remove unneeded SR names from asm/regs.h;
- add SREG_ prefix to remaining SR names;

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>

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[PATCH] xtensa: remove extra header files

The Xtensa port contained many header files that were never needed. This
rather lengthy patch removes all those files. Unfortunately, there were
many depe

[PATCH] xtensa: remove extra header files

The Xtensa port contained many header files that were never needed. This
rather lengthy patch removes all those files. Unfortunately, there were
many dependencies that needed to be updated, so this patch touches quite a
few source files.

Signed-off-by: Chris Zankel <chris@zankel.net>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

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kbuild: m68k,parisc,ppc,ppc64,s390,xtensa use generic asm-offsets.h support

Delete obsoleted parts form arch makefiles and rename to asm-offsets.h

Signed-off-by: Sam Ravnborg <sam@ravnborg.org>

[PATCH] xtensa: Architecture support for Tensilica Xtensa Part 3

The attached patches provides part 3 of an architecture implementation for the
Tensilica Xtensa CPU series.

Signed-off-by: Chris Zan

[PATCH] xtensa: Architecture support for Tensilica Xtensa Part 3

The attached patches provides part 3 of an architecture implementation for the
Tensilica Xtensa CPU series.

Signed-off-by: Chris Zankel <chris@zankel.net>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

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xtensa: clean up word alignment macros in assembly code

Remove duplicate definitions of ALIGN/src_b/__src_b and SSA8/ssa8/__ssa8
from assembly sources and put single definition into asm/

xtensa: clean up word alignment macros in assembly code

Remove duplicate definitions of ALIGN/src_b/__src_b and SSA8/ssa8/__ssa8
from assembly sources and put single definition into asm/asmmacro.h

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

show more ...

xtensa: build kernel with text-section-literals

vmlinux.lds.S doesn't do anything special with literals, so instead of
keeping them separate put them into the corresponding text sections

xtensa: build kernel with text-section-literals

vmlinux.lds.S doesn't do anything special with literals, so instead of
keeping them separate put them into the corresponding text sections.
Drop explicit .literal sections from the vmlinux.lds.S, use standard
section macros. Mark literal pool locations in the assembly sources.
Unfortunately assembler doesn't put literals into .init sections and
external libgcc may still have .literal sections, so sed transformation
to the linker script is still needed.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

show more ...

xtensa: allow single-stepping through unaligned load/store

Update icount when icountlevel is non-zero but not greater than EXCM level
when load/store instruction is successfully emulated

xtensa: allow single-stepping through unaligned load/store

Update icount when icountlevel is non-zero but not greater than EXCM level
when load/store instruction is successfully emulated. This allows
single-stepping over such instruction in userspace debugger.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

show more ...

xtensa: move invalid unaligned instruction handler closer to its users

With this change a threaded jump from .Linvalid_instruction_load to
.Linvalid_instruction can be removed and more c

xtensa: move invalid unaligned instruction handler closer to its users

With this change a threaded jump from .Linvalid_instruction_load to
.Linvalid_instruction can be removed and more code may be added to
common load/store exit path.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

show more ...

xtensa: make fast_unaligned store restartable

fast_unaligned may encounter DTLB miss or SEGFAULT during the store
emulation. Don't update epc1 and lcount until after the store emulation

xtensa: make fast_unaligned store restartable

fast_unaligned may encounter DTLB miss or SEGFAULT during the store
emulation. Don't update epc1 and lcount until after the store emulation
is complete, so that the faulting store instruction could be replayed.
Remove duplicate code handling zero overhead loops and calculate new
epc1 and lcount in one place.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

show more ...

xtensa: add double exception fixup handler for fast_unaligned

fast_unaligned_fixup restores user registers and runs normal exception
handler in the current stack frame. Unaligned load/st

xtensa: add double exception fixup handler for fast_unaligned

fast_unaligned_fixup restores user registers and runs normal exception
handler in the current stack frame. Unaligned load/store is retried
after that.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

show more ...

xtensa: fix kernel/user jump out of fast_unaligned

Use correct register (a0, just read from the PS) to check user mode bit.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>