Lines Matching refs:CLKDEV_CON_ID

102 	CLKDEV_CON_ID("extal", &extal_clk),
103 	CLKDEV_CON_ID("pll_clk", &pll_clk),
106 	CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
107 	CLKDEV_CON_ID("shywaya_clk", &div4_clks[DIV4_SHA]),
108 	CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]),
109 	CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
110 	CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
111 	CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
119 	CLKDEV_CON_ID("h8ex_fck", &mstp_clks[MSTP003]),
120 	CLKDEV_CON_ID("csm_fck", &mstp_clks[MSTP002]),
121 	CLKDEV_CON_ID("fe1_fck", &mstp_clks[MSTP001]),
122 	CLKDEV_CON_ID("fe0_fck", &mstp_clks[MSTP000]),
127 	CLKDEV_CON_ID("hudi_fck", &mstp_clks[MSTP119]),
128 	CLKDEV_CON_ID("dmac_11_6_fck", &mstp_clks[MSTP105]),
129 	CLKDEV_CON_ID("dmac_5_0_fck", &mstp_clks[MSTP104]),