include/asm/pgtable-32.h

19 #include <asm-generic/pgtable-nopmd.h>
26  * Regarding 32-bit MIPS huge page support (and the tradeoff it entails):
28  *  We use the same huge page sizes as 64-bit MIPS. Assuming a 4KB page size,
29  * our 2-level table layout would normally have a PGD entry cover a contiguous
30  * 4MB virtual address region (pointing to a 4KB PTE page of 1,024 32-bit pte_t
37  * increases to match 64-bit MIPS, but PTE lookups remain CPU cache-friendly.
39  * NOTE: We don't yet support huge pages if extended-addressing is enabled
40  *       (i.e. EVA, XPA, 36-bit Alchemy/Netlogic).
46  * - add_temporary_entry() add a temporary TLB entry. We use TLB entries
56  * Basically we have the same two-level (which is the logical three level
63 /* PGDIR_SHIFT determines what a third-level page table entry can map */
65 # define PGDIR_SHIFT	(2 * PAGE_SHIFT - PTE_T_LOG2 - 1)
67 # define PGDIR_SHIFT	(2 * PAGE_SHIFT - PTE_T_LOG2)
71 #define PGDIR_MASK	(~(PGDIR_SIZE-1))
74  * Entries per page directory level: we use two-level, so
78 # define __PGD_TABLE_ORDER (32 - 3 * PAGE_SHIFT + PGD_T_LOG2 + PTE_T_LOG2 + 1)
80 # define __PGD_TABLE_ORDER (32 - 3 * PAGE_SHIFT + PGD_T_LOG2 + PTE_T_LOG2)
98 #define PKMAP_END	((FIXADDR_START) & ~((LAST_PKMAP << PAGE_SHIFT)-1))
99 #define PKMAP_BASE	(PKMAP_END - PAGE_SIZE * LAST_PKMAP)
102 # define VMALLOC_END	(PKMAP_BASE-2*PAGE_SIZE)
104 # define VMALLOC_END	(FIXADDR_START-2*PAGE_SIZE)
108 #define pte_ERROR(e) \  argument
109 	printk("%s:%d: bad pte %016Lx.\n", __FILE__, __LINE__, pte_val(e))
111 #define pte_ERROR(e) \  argument
112 	printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
114 #define pgd_ERROR(e) \  argument
115 	printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
172 #define pte_pfn(x)		((unsigned long)((x).pte_high >> 6))
178 	pte.pte_high = (pfn << 6) | (pgprot_val(prot) & 0x3f);  in pfn_pte()
204  *   1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
205  *   <----------- offset ------------> < type -> V G E 0 0 0 0 0 0 P
207  *   E is the exclusive marker that is not stored in swap entries.
217 /* We borrow bit 7 to store the exclusive marker in swap PTEs. */
218 #define _PAGE_SWP_EXCLUSIVE	(1 << 7)
227  *   6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3
228  *   3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2
229  *   0 0 0 0 0 0 E P <------------------ zeroes ------------------->
232  *   1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
233  *   <----------------- offset ------------------> < type -> V G 0 0
235  *   E is the exclusive marker that is not stored in swap entries.
256  *   6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3
257  *   3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2
258  *   <------------------ zeroes -------------------> E P 0 0 0 0 0 0
261  *   1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
262  *   <------------------- offset --------------------> < type -> V G
264  *   E is the exclusive marker that is not stored in swap entries.
269 #define __swp_offset(x)			 ((x).val >> 7)
270 #define __swp_entry(type, offset)	((swp_entry_t)  { (((type) & 0x1f) << 2) | ((offset) << 7) })
275  * We borrow bit 39 (bit 7 in the low PTE) to store the exclusive marker in swap
278 #define _PAGE_SWP_EXCLUSIVE	(1 << 7)
285  *   1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
286  *   <------------- offset --------------> < type -> 0 0 0 0 0 0 E P
288  *   E is the exclusive marker that is not stored in swap entries.