dts/loongson/ls7a-pch.dtsi

8 		ranges = <0 0x10000000 0 0x10000000 0 0x10000000 /* PIO & CONF & APB */
9 				0 0x20000000 0 0x20000000 0 0x10000000
10 				0 0x40000000 0 0x40000000 0 0x40000000 /* PCI MEM */
11 				0xe00 0x00000000 0xe00 0x00000000 0x100 0x0000000>;
15 			reg = <0 0x10000000 0 0x400>;
18 			loongson,pic-base-vec = <0>;
24 			reg = <0 0x100d0100 0 0x78>;
31 			reg = <0 0x10080000 0 0x100>;
41 			reg = <0 0x10080100 0 0x100>;
51 			reg = <0 0x10080200 0 0x100>;
61 			reg = <0 0x10080300 0 0x100>;
75 			reg = <0 0x1a000000 0 0x02000000>,
76 				<0xefe 0x00000000 0 0x20000000>;
78 			ranges = <0x01000000 0x0 0x00020000 0x0 0x18020000 0x0 0x00020000>,
79 				 <0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>;
81 			ohci@4,0 {
82 				compatible = "pci0014,7a24.0",
87 				reg = <0x2000 0x0 0x0 0x0 0x0>;
93 				compatible = "pci0014,7a14.0",
98 				reg = <0x2100 0x0 0x0 0x0 0x0>;
103 			ohci@5,0 {
104 				compatible = "pci0014,7a24.0",
109 				reg = <0x2800 0x0 0x0 0x0 0x0>;
115 				compatible = "pci0014,7a14.0",
120 				reg = <0x2900 0x0 0x0 0x0 0x0>;
125 			sata@8,0 {
126 				compatible = "pci0014,7a08.0",
131 				reg = <0x4000 0x0 0x0 0x0 0x0>;
137 				compatible = "pci0014,7a08.0",
142 				reg = <0x4100 0x0 0x0 0x0 0x0>;
148 				compatible = "pci0014,7a08.0",
153 				reg = <0x4200 0x0 0x0 0x0 0x0>;
158 			gpu@6,0 {
159 				compatible = "pci0014,7a15.0",
164 				reg = <0x3000 0x0 0x0 0x0 0x0>;
170 				compatible = "pci0014,7a06.0",
175 				reg = <0x3100 0x0 0x0 0x0 0x0>;
180 			hda@7,0 {
181 				compatible = "pci0014,7a07.0",
186 				reg = <0x3800 0x0 0x0 0x0 0x0>;
191 			gmac@3,0 {
192 				compatible = "pci0014,7a03.0",
197 				reg = <0x1800 0x0 0x0 0x0 0x0>;
205 					#size-cells = <0>;
207 					phy0: ethernet-phy@0 {
208 						reg = <0>;
214 				compatible = "pci0014,7a03.0",
220 				reg = <0x1900 0x0 0x0 0x0 0x0>;
228 					#size-cells = <0>;
231 						reg = <0>;
236 			pcie@9,0 {
242 				reg = <0x4800 0x0 0x0 0x0 0x0>;
250 				interrupt-map-mask = <0 0 0 0>;
251 				interrupt-map = <0 0 0 0 &pic 32 IRQ_TYPE_LEVEL_HIGH>;
255 			pcie@a,0 {
261 				reg = <0x5000 0x0 0x0 0x0 0x0>;
269 				interrupt-map-mask = <0 0 0 0>;
270 				interrupt-map = <0 0 0 0 &pic 33 IRQ_TYPE_LEVEL_HIGH>;
274 			pcie@b,0 {
280 				reg = <0x5800 0x0 0x0 0x0 0x0>;
288 				interrupt-map-mask = <0 0 0 0>;
289 				interrupt-map = <0 0 0 0 &pic 34 IRQ_TYPE_LEVEL_HIGH>;
293 			pcie@c,0 {
299 				reg = <0x6000 0x0 0x0 0x0 0x0>;
307 				interrupt-map-mask = <0 0 0 0>;
308 				interrupt-map = <0 0 0 0 &pic 35 IRQ_TYPE_LEVEL_HIGH>;
312 			pcie@d,0 {
318 				reg = <0x6800 0x0 0x0 0x0 0x0>;
326 				interrupt-map-mask = <0 0 0 0>;
327 				interrupt-map = <0 0 0 0 &pic 36 IRQ_TYPE_LEVEL_HIGH>;
331 			pcie@e,0 {
337 				reg = <0x7000 0x0 0x0 0x0 0x0>;
345 				interrupt-map-mask = <0 0 0 0>;
346 				interrupt-map = <0 0 0 0 &pic 37 IRQ_TYPE_LEVEL_HIGH>;
350 			pcie@f,0 {
356 				reg = <0x7800 0x0 0x0 0x0 0x0>;
364 				interrupt-map-mask = <0 0 0 0>;
365 				interrupt-map = <0 0 0 0 &pic 40 IRQ_TYPE_LEVEL_HIGH>;
369 			pcie@10,0 {
375 				reg = <0x8000 0x0 0x0 0x0 0x0>;
383 				interrupt-map-mask = <0 0 0 0>;
384 				interrupt-map = <0 0 0 0 &pic 41 IRQ_TYPE_LEVEL_HIGH>;
388 			pcie@11,0 {
394 				reg = <0x8800 0x0 0x0 0x0 0x0>;
402 				interrupt-map-mask = <0 0 0 0>;
403 				interrupt-map = <0 0 0 0 &pic 42 IRQ_TYPE_LEVEL_HIGH>;
407 			pcie@12,0 {
413 				reg = <0x9000 0x0 0x0 0x0 0x0>;
421 				interrupt-map-mask = <0 0 0 0>;
422 				interrupt-map = <0 0 0 0 &pic 43 IRQ_TYPE_LEVEL_HIGH>;
426 			pcie@13,0 {
432 				reg = <0x9800 0x0 0x0 0x0 0x0>;
440 				interrupt-map-mask = <0 0 0 0>;
441 				interrupt-map = <0 0 0 0 &pic 38 IRQ_TYPE_LEVEL_HIGH>;
445 			pcie@14,0 {
451 				reg = <0xa000 0x0 0x0 0x0 0x0>;
459 				interrupt-map-mask = <0 0 0 0>;
460 				interrupt-map = <0 0 0 0 &pic 39 IRQ_TYPE_LEVEL_HIGH>;
469 			ranges = <1 0 0 0x18000000 0x20000>;