dts/ti/k3-am642-evm.dts

1 // SPDX-License-Identifier: GPL-2.0
3  * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
6 /dts-v1/;
8 #include <dt-bindings/phy/phy.h>
9 #include <dt-bindings/leds/common.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/net/ti-dp83867.h>
12 #include "k3-am642.dtsi"
14 #include "k3-serdes.h"
17 	compatible = "ti,am642-evm", "ti,am642";
21 		stdout-path = &main_uart0;
38 		bootph-all;
44 	reserved-memory {
45 		#address-cells = <2>;
46 		#size-cells = <2>;
50 			reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
52 			no-map;
55 		main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
56 			compatible = "shared-dma-pool";
58 			no-map;
61 		main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
62 			compatible = "shared-dma-pool";
64 			no-map;
67 		main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
68 			compatible = "shared-dma-pool";
70 			no-map;
73 		main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
74 			compatible = "shared-dma-pool";
76 			no-map;
79 		main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
80 			compatible = "shared-dma-pool";
82 			no-map;
85 		main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
86 			compatible = "shared-dma-pool";
88 			no-map;
91 		main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
92 			compatible = "shared-dma-pool";
94 			no-map;
97 		main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
98 			compatible = "shared-dma-pool";
100 			no-map;
103 		rtos_ipc_memory_region: ipc-memories@a5000000 {
106 			no-map;
110 	evm_12v0: regulator-0 {
112 		bootph-all;
113 		compatible = "regulator-fixed";
114 		regulator-name = "evm_12v0";
115 		regulator-min-microvolt = <12000000>;
116 		regulator-max-microvolt = <12000000>;
117 		regulator-always-on;
118 		regulator-boot-on;
121 	vsys_5v0: regulator-1 {
123 		compatible = "regulator-fixed";
124 		regulator-name = "vsys_5v0";
125 		regulator-min-microvolt = <5000000>;
126 		regulator-max-microvolt = <5000000>;
127 		vin-supply = <&evm_12v0>;
128 		regulator-always-on;
129 		regulator-boot-on;
132 	vsys_3v3: regulator-2 {
134 		bootph-all;
135 		compatible = "regulator-fixed";
136 		regulator-name = "vsys_3v3";
137 		regulator-min-microvolt = <3300000>;
138 		regulator-max-microvolt = <3300000>;
139 		vin-supply = <&evm_12v0>;
140 		regulator-always-on;
141 		regulator-boot-on;
144 	vdd_mmc1: regulator-3 {
146 		bootph-all;
147 		compatible = "regulator-fixed";
148 		regulator-name = "vdd_mmc1";
149 		regulator-min-microvolt = <3300000>;
150 		regulator-max-microvolt = <3300000>;
151 		regulator-boot-on;
152 		enable-active-high;
153 		vin-supply = <&vsys_3v3>;
157 	vddb: regulator-4 {
158 		compatible = "regulator-fixed";
159 		regulator-name = "vddb_3v3_display";
160 		regulator-min-microvolt = <3300000>;
161 		regulator-max-microvolt = <3300000>;
162 		vin-supply = <&vsys_3v3>;
163 		regulator-always-on;
164 		regulator-boot-on;
167 	vtt_supply: regulator-5 {
168 		bootph-all;
169 		compatible = "regulator-fixed";
170 		regulator-name = "vtt";
171 		pinctrl-names = "default";
172 		pinctrl-0 = <&ddr_vtt_pins_default>;
173 		regulator-min-microvolt = <3300000>;
174 		regulator-max-microvolt = <3300000>;
176 		vin-supply = <&vsys_3v3>;
177 		enable-active-high;
178 		regulator-always-on;
179 		regulator-boot-on;
183 		compatible = "gpio-leds";
185 		led-0 {
186 			label = "am64-evm:red:heartbeat";
188 			linux,default-trigger = "heartbeat";
190 			default-state = "off";
194 	mdio_mux: mux-controller {
195 		compatible = "gpio-mux";
196 		#mux-control-cells = <0>;
198 		mux-gpios = <&exp1 12 GPIO_ACTIVE_HIGH>;
201 	mdio-mux-1 {
202 		compatible = "mdio-mux-multiplexer";
203 		mux-controls = <&mdio_mux>;
204 		mdio-parent-bus = <&cpsw3g_mdio>;
205 		#address-cells = <1>;
206 		#size-cells = <0>;
210 			#address-cells = <1>;
211 			#size-cells = <0>;
213 			cpsw3g_phy3: ethernet-phy@3 {
219 	transceiver1: can-phy0 {
221 		#phy-cells = <0>;
222 		max-bitrate = <5000000>;
223 		standby-gpios = <&exp1 8 GPIO_ACTIVE_HIGH>;
226 	transceiver2: can-phy1 {
228 		#phy-cells = <0>;
229 		max-bitrate = <5000000>;
230 		standby-gpios = <&exp1 9 GPIO_ACTIVE_HIGH>;
235 	main_mmc1_pins_default: main-mmc1-default-pins {
236 		pinctrl-single,pins = <
249 	main_uart1_pins_default: main-uart1-default-pins {
250 		pinctrl-single,pins = <
258 	main_uart0_pins_default: main-uart0-default-pins {
259 		bootph-all;
260 		pinctrl-single,pins = <
268 	main_spi0_pins_default: main-spi0-default-pins {
269 		pinctrl-single,pins = <
277 	main_i2c0_pins_default: main-i2c0-default-pins {
278 		bootph-all;
279 		pinctrl-single,pins = <
285 	main_i2c1_pins_default: main-i2c1-default-pins {
286 		bootph-all;
287 		pinctrl-single,pins = <
293 	mdio1_pins_default: mdio1-default-pins {
294 		bootph-all;
295 		pinctrl-single,pins = <
301 	rgmii1_pins_default: rgmii1-default-pins {
302 		bootph-all;
303 		pinctrl-single,pins = <
306 			AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* (V6) PRG0_PRU1_GPO10.RGMII1_RD2 */
319        rgmii2_pins_default: rgmii2-default-pins {
320 		bootph-all;
321 		pinctrl-single,pins = <
337 	main_usb0_pins_default: main-usb0-default-pins {
338 		bootph-all;
339 		pinctrl-single,pins = <
344 	ospi0_pins_default: ospi0-default-pins {
345 		pinctrl-single,pins = <
360 	main_ecap0_pins_default: main-ecap0-default-pins {
361 		pinctrl-single,pins = <
366 	main_mcan0_pins_default: main-mcan0-default-pins {
367 		pinctrl-single,pins = <
373 	main_mcan1_pins_default: main-mcan1-default-pins {
374 		pinctrl-single,pins = <
380 	ddr_vtt_pins_default: ddr-vtt-default-pins {
381 		bootph-all;
382 		pinctrl-single,pins = <
389 	bootph-all;
391 	pinctrl-names = "default";
392 	pinctrl-0 = <&main_uart0_pins_default>;
393 	current-speed = <115200>;
399 	pinctrl-names = "default";
400 	pinctrl-0 = <&main_uart1_pins_default>;
404 	bootph-all;
406 	pinctrl-names = "default";
407 	pinctrl-0 = <&main_i2c0_pins_default>;
408 	clock-frequency = <400000>;
418 	bootph-all;
420 	pinctrl-names = "default";
421 	pinctrl-0 = <&main_i2c1_pins_default>;
422 	clock-frequency = <400000>;
425 		bootph-all;
428 		gpio-controller;
429 		#gpio-cells = <2>;
430 		gpio-line-names = "GPIO_eMMC_RSTn", "CAN_MUX_SEL",
442 	/* osd9616p0899-10 */
444 		compatible = "solomon,ssd1306fb-i2c";
446 		reset-gpios = <&exp1 14 GPIO_ACTIVE_LOW>;
447 		vbat-supply = <&vddb>;
450 		solomon,com-seq;
451 		solomon,com-invdir;
452 		solomon,page-offset = <0>;
459 	bootph-all;
469 	pinctrl-names = "default";
470 	pinctrl-0 = <&main_spi0_pins_default>;
471 	ti,pindir-d0-out-d1-in;
475 		spi-max-frequency = <1000000>;
476 		spi-cs-high;
477 		data-size = <16>;
484 	bus-width = <8>;
485 	non-removable;
486 	ti,driver-strength-ohm = <50>;
487 	disable-wp;
492 	bootph-all;
494 	vmmc-supply = <&vdd_mmc1>;
495 	pinctrl-names = "default";
496 	bus-width = <4>;
497 	pinctrl-0 = <&main_mmc1_pins_default>;
498 	ti,driver-strength-ohm = <50>;
499 	disable-wp;
503 	bootph-all;
504 	ti,vbus-divider;
505 	ti,usb2-only;
509 	bootph-all;
511 	maximum-speed = "high-speed";
512 	pinctrl-names = "default";
513 	pinctrl-0 = <&main_usb0_pins_default>;
517 	bootph-all;
518 	pinctrl-names = "default";
519 	pinctrl-0 = <&rgmii1_pins_default>, <&rgmii2_pins_default>;
523 	bootph-all;
524 	phy-mode = "rgmii-rxid";
525 	phy-handle = <&cpsw3g_phy0>;
529 	phy-mode = "rgmii-rxid";
530 	phy-handle = <&cpsw3g_phy3>;
534 	bootph-all;
536 	pinctrl-names = "default";
537 	pinctrl-0 = <&mdio1_pins_default>;
539 	cpsw3g_phy0: ethernet-phy@0 {
540 		bootph-all;
542 		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
543 		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
554 	pinctrl-names = "default";
555 	pinctrl-0 = <&ospi0_pins_default>;
558 		compatible = "jedec,spi-nor";
560 		spi-tx-bus-width = <8>;
561 		spi-rx-bus-width = <8>;
562 		spi-max-frequency = <25000000>;
563 		cdns,tshsl-ns = <60>;
564 		cdns,tsd2d-ns = <60>;
565 		cdns,tchsh-ns = <60>;
566 		cdns,tslch-ns = <60>;
567 		cdns,read-delay = <4>;
570 			compatible = "fixed-partitions";
571 			#address-cells = <1>;
572 			#size-cells = <1>;
585 				label = "ospi.u-boot";
615 	mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
616 		ti,mbox-rx = <0 0 2>;
617 		ti,mbox-tx = <1 0 2>;
620 	mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
621 		ti,mbox-rx = <2 0 2>;
622 		ti,mbox-tx = <3 0 2>;
629 	mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
630 		ti,mbox-rx = <0 0 2>;
631 		ti,mbox-tx = <1 0 2>;
634 	mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
635 		ti,mbox-rx = <2 0 2>;
636 		ti,mbox-tx = <3 0 2>;
643 	mbox_m4_0: mbox-m4-0 {
644 		ti,mbox-rx = <0 0 2>;
645 		ti,mbox-tx = <1 0 2>;
651 	memory-region = <&main_r5fss0_core0_dma_memory_region>,
657 	memory-region = <&main_r5fss0_core1_dma_memory_region>,
663 	memory-region = <&main_r5fss1_core0_dma_memory_region>,
669 	memory-region = <&main_r5fss1_core1_dma_memory_region>,
674 	idle-states = <AM64_SERDES0_LANE0_PCIE0>;
680 		cdns,num-lanes = <1>;
681 		#phy-cells = <0>;
682 		cdns,phy-type = <PHY_TYPE_PCIE>;
689 	reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>;
691 	phy-names = "pcie-phy";
692 	num-lanes = <1>;
697 	phy-names = "pcie-phy";
698 	num-lanes = <1>;
704 	pinctrl-names = "default";
705 	pinctrl-0 = <&main_ecap0_pins_default>;
710 	pinctrl-names = "default";
711 	pinctrl-0 = <&main_mcan0_pins_default>;
717 	pinctrl-names = "default";
718 	pinctrl-0 = <&main_mcan1_pins_default>;