dts/ti/k3-am62a-main.dtsi

11 		reg = <0x00 0x70000000 0x00 0x10000>;
14 		ranges = <0x0 0x00 0x70000000 0x10000>;
19 		reg = <0x00 0x01800000 0x00 0x10000>,	/* GICD */
20 		      <0x00 0x01880000 0x00 0xc0000>,	/* GICR */
21 		      <0x01 0x00000000 0x00 0x2000>,    /* GICC */
22 		      <0x01 0x00010000 0x00 0x1000>,    /* GICH */
23 		      <0x01 0x00020000 0x00 0x2000>;    /* GICV */
37 			reg = <0x00 0x01820000 0x00 0x10000>;
38 			socionext,synquacer-pre-its = <0x1000000 0x400000>;
46 		reg = <0x00 0x00100000 0x00 0x20000>;
49 		ranges = <0x00 0x00 0x00100000 0x20000>;
53 			reg = <0x4044 0x8>;
59 			reg = <0x4130 0x4>;
69 		ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06000000>;
75 			reg = <0x00 0x4d000000 0x00 0x80000>,
76 			      <0x00 0x4a600000 0x00 0x80000>,
77 			      <0x00 0x4a400000 0x00 0x80000>;
86 			reg = <0x00 0x48000000 0x00 0x100000>;
87 			#interrupt-cells = <0>;
99 			reg = <0x00 0x485c0100 0x00 0x100>,
100 			      <0x00 0x4c000000 0x00 0x20000>,
101 			      <0x00 0x4a820000 0x00 0x20000>,
102 			      <0x00 0x4aa40000 0x00 0x20000>,
103 			      <0x00 0x4bc00000 0x00 0x100000>;
109 			ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
110 			ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
111 			ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
116 			reg = <0x00 0x485c0000 0x00 0x100>,
117 			      <0x00 0x4a800000 0x00 0x20000>,
118 			      <0x00 0x4aa00000 0x00 0x40000>,
119 			      <0x00 0x4b800000 0x00 0x400000>;
125 			ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
126 						<0x24>, /* CPSW_TX_CHAN */
127 						<0x25>, /* SAUL_TX_0_CHAN */
128 						<0x26>; /* SAUL_TX_1_CHAN */
129 			ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
130 						<0x11>, /* RING_CPSW_TX_CHAN */
131 						<0x12>, /* RING_SAUL_TX_0_CHAN */
132 						<0x13>; /* RING_SAUL_TX_1_CHAN */
133 			ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
134 						<0x2b>, /* CPSW_RX_CHAN */
135 						<0x2d>, /* SAUL_RX_0_CHAN */
136 						<0x2f>, /* SAUL_RX_1_CHAN */
137 						<0x31>, /* SAUL_RX_2_CHAN */
138 						<0x33>; /* SAUL_RX_3_CHAN */
139 			ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
140 						<0x2c>, /* FLOW_CPSW_RX_CHAN */
141 						<0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
142 						<0x32>; /* FLOW_SAUL_RX_2/3_CHAN */
148 		reg = <0x00 0x44043000 0x00 0xfe0>;
175 		reg = <0x00 0x43600000 0x00 0x10000>,
176 		      <0x00 0x44880000 0x00 0x20000>,
177 		      <0x00 0x44860000 0x00 0x20000>;
188 		reg = <0x00 0xf4000 0x00 0x2ac>;
191 		pinctrl-single,function-mask = <0xffffffff>;
196 		reg = <0x00 0x2400000 0x00 0x400>;
208 		reg = <0x00 0x2410000 0x00 0x400>;
220 		reg = <0x00 0x2420000 0x00 0x400>;
232 		reg = <0x00 0x2430000 0x00 0x400>;
244 		reg = <0x00 0x2440000 0x00 0x400>;
256 		reg = <0x00 0x2450000 0x00 0x400>;
268 		reg = <0x00 0x2460000 0x00 0x400>;
280 		reg = <0x00 0x2470000 0x00 0x400>;
292 		reg = <0x00 0x02800000 0x00 0x100>;
295 		clocks = <&k3_clks 146 0>;
302 		reg = <0x00 0x02810000 0x00 0x100>;
305 		clocks = <&k3_clks 152 0>;
312 		reg = <0x00 0x02820000 0x00 0x100>;
315 		clocks = <&k3_clks 153 0>;
322 		reg = <0x00 0x02830000 0x00 0x100>;
325 		clocks = <&k3_clks 154 0>;
332 		reg = <0x00 0x02840000 0x00 0x100>;
335 		clocks = <&k3_clks 155 0>;
342 		reg = <0x00 0x02850000 0x00 0x100>;
345 		clocks = <&k3_clks 156 0>;
352 		reg = <0x00 0x02860000 0x00 0x100>;
355 		clocks = <&k3_clks 158 0>;
362 		reg = <0x00 0x20000000 0x00 0x100>;
365 		#size-cells = <0>;
374 		reg = <0x00 0x20010000 0x00 0x100>;
377 		#size-cells = <0>;
386 		reg = <0x00 0x20020000 0x00 0x100>;
389 		#size-cells = <0>;
398 		reg = <0x00 0x20030000 0x00 0x100>;
401 		#size-cells = <0>;
410 		reg = <0x00 0x20100000 0x00 0x400>;
413 		#size-cells = <0>;
415 		clocks = <&k3_clks 141 0>;
421 		reg = <0x00 0x20110000 0x00 0x400>;
424 		#size-cells = <0>;
426 		clocks = <&k3_clks 142 0>;
432 		reg = <0x00 0x20120000 0x00 0x400>;
435 		#size-cells = <0>;
437 		clocks = <&k3_clks 143 0>;
443 		reg = <0x00 0x00a00000 0x00 0x800>;
450 		ti,interrupt-ranges = <0 32 16>;
456 		reg = <0x00 0x00600000 0x0 0x100>;
465 		ti,davinci-gpio-unbanked = <0>;
467 		clocks = <&k3_clks 77 0>;
474 		reg = <0x00 0x00601000 0x0 0x100>;
483 		ti,davinci-gpio-unbanked = <0>;
485 		clocks = <&k3_clks 78 0>;
492 		reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>;
497 		ti,trm-icp = <0x2>;
498 		ti,otap-del-sel-legacy = <0x0>;
499 		ti,otap-del-sel-sd-hs = <0x0>;
500 		ti,otap-del-sel-sdr12 = <0xf>;
501 		ti,otap-del-sel-sdr25 = <0xf>;
502 		ti,otap-del-sel-sdr50 = <0xc>;
503 		ti,otap-del-sel-sdr104 = <0x6>;
504 		ti,otap-del-sel-ddr50 = <0x9>;
505 		ti,itap-del-sel-legacy = <0x0>;
506 		ti,itap-del-sel-sd-hs = <0x0>;
507 		ti,itap-del-sel-sdr12 = <0x0>;
508 		ti,itap-del-sel-sdr25 = <0x0>;
509 		ti,clkbuf-sel = <0x7>;
517 		reg = <0x00 0x0f900000 0x00 0x800>;
520 		ti,syscon-phy-pll-refclk = <&wkup_conf 0x4008>;
529 			reg = <0x00 0x31000000 0x00 0x50000>;
530 			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
531 				     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
540 		reg = <0x00 0x0f910000 0x00 0x800>;
543 		ti,syscon-phy-pll-refclk = <&wkup_conf 0x4018>;
552 			reg = <0x00 0x31100000 0x00 0x50000>;
553 			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
554 				     <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
563 		reg = <0x00 0x0fc00000 0x00 0x70000>;
571 			reg = <0x00 0x0fc40000 0x00 0x100>,
572 			      <0x05 0x00000000 0x01 0x00000000>;
576 			cdns,trigger-address = <0x0>;
583 			#size-cells = <0>;
591 		reg = <0x0 0x8000000 0x0 0x200000>;
593 		ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>;
594 		clocks = <&k3_clks 13 0>;
601 		dmas = <&main_pktdma 0xc600 15>,
602 		       <&main_pktdma 0xc601 15>,
603 		       <&main_pktdma 0xc602 15>,
604 		       <&main_pktdma 0xc603 15>,
605 		       <&main_pktdma 0xc604 15>,
606 		       <&main_pktdma 0xc605 15>,
607 		       <&main_pktdma 0xc606 15>,
608 		       <&main_pktdma 0xc607 15>,
609 		       <&main_pktdma 0x4600 15>;
615 			#size-cells = <0>;
623 				ti,syscon-efuse = <&wkup_conf 0x200>;
637 			reg = <0x0 0xf00 0x0 0x100>;
639 			#size-cells = <0>;
640 			clocks = <&k3_clks 13 0>;
647 			reg = <0x0 0x3d000 0x0 0x400>;
659 		reg = <0x00 0x2a000000 0x00 0x1000>;
665 		reg = <0x00 0x29000000 0x00 0x200>;
674 		reg = <0x00 0x29010000 0x00 0x200>;
683 		reg = <0x00 0x29020000 0x00 0x200>;
692 		reg = <0x00 0x29030000 0x00 0x200>;
701 		reg = <0x00 0x20701000 0x00 0x200>,
702 		      <0x00 0x20708000 0x00 0x8000>;
710 		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
716 		reg = <0x00 0x0e000000 0x00 0x100>;
717 		clocks = <&k3_clks 125 0>;
719 		assigned-clocks = <&k3_clks 125 0>;
725 		reg = <0x00 0x0e010000 0x00 0x100>;
726 		clocks = <&k3_clks 126 0>;
728 		assigned-clocks = <&k3_clks 126 0>;
734 		reg = <0x00 0x0e020000 0x00 0x100>;
735 		clocks = <&k3_clks 127 0>;
737 		assigned-clocks = <&k3_clks 127 0>;
743 		reg = <0x00 0x0e030000 0x00 0x100>;
744 		clocks = <&k3_clks 128 0>;
746 		assigned-clocks = <&k3_clks 128 0>;
752 		reg = <0x00 0x0e040000 0x00 0x100>;
753 		clocks = <&k3_clks 205 0>;
755 		assigned-clocks = <&k3_clks 205 0>;
762 		reg = <0x00 0x23000000 0x00 0x100>;
764 		clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>;
772 		reg = <0x00 0x23010000 0x00 0x100>;
774 		clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>;
782 		reg = <0x00 0x23020000 0x00 0x100>;
784 		clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>;
792 		reg = <0x00 0x23100000 0x00 0x100>;
794 		clocks = <&k3_clks 51 0>;
802 		reg = <0x00 0x23110000 0x00 0x100>;
804 		clocks = <&k3_clks 52 0>;
812 		reg = <0x00 0x23120000 0x00 0x100>;
814 		clocks = <&k3_clks 53 0>;