Lines Matching +full:uniphier +full:- +full:ld11 +full:- +full:sysctrl
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier LD11 SoC
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 compatible = "socionext,uniphier-ld11";
14 #address-cells = <2>;
15 #size-cells = <2>;
16 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <0>;
22 cpu-map {
35 compatible = "arm,cortex-a53";
38 enable-method = "psci";
39 next-level-cache = <&l2>;
40 operating-points-v2 = <&cluster0_opp>;
45 compatible = "arm,cortex-a53";
48 enable-method = "psci";
49 next-level-cache = <&l2>;
50 operating-points-v2 = <&cluster0_opp>;
53 l2: l2-cache {
58 cluster0_opp: opp-table {
59 compatible = "operating-points-v2";
60 opp-shared;
62 opp-245000000 {
63 opp-hz = /bits/ 64 <245000000>;
64 clock-latency-ns = <300>;
66 opp-250000000 {
67 opp-hz = /bits/ 64 <250000000>;
68 clock-latency-ns = <300>;
70 opp-490000000 {
71 opp-hz = /bits/ 64 <490000000>;
72 clock-latency-ns = <300>;
74 opp-500000000 {
75 opp-hz = /bits/ 64 <500000000>;
76 clock-latency-ns = <300>;
78 opp-653334000 {
79 opp-hz = /bits/ 64 <653334000>;
80 clock-latency-ns = <300>;
82 opp-666667000 {
83 opp-hz = /bits/ 64 <666667000>;
84 clock-latency-ns = <300>;
86 opp-980000000 {
87 opp-hz = /bits/ 64 <980000000>;
88 clock-latency-ns = <300>;
93 compatible = "arm,psci-1.0";
99 compatible = "fixed-clock";
100 #clock-cells = <0>;
101 clock-frequency = <25000000>;
105 emmc_pwrseq: emmc-pwrseq {
106 compatible = "mmc-pwrseq-emmc";
107 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>;
111 compatible = "arm,armv8-timer";
118 reserved-memory {
119 #address-cells = <2>;
120 #size-cells = <2>;
123 secure-memory@81000000 {
125 no-map;
130 compatible = "simple-bus";
131 #address-cells = <1>;
132 #size-cells = <1>;
136 compatible = "socionext,uniphier-scssi";
139 #address-cells = <1>;
140 #size-cells = <0>;
142 pinctrl-names = "default";
143 pinctrl-0 = <&pinctrl_spi0>;
149 compatible = "socionext,uniphier-scssi";
152 #address-cells = <1>;
153 #size-cells = <0>;
155 pinctrl-names = "default";
156 pinctrl-0 = <&pinctrl_spi1>;
162 compatible = "socionext,uniphier-uart";
166 pinctrl-names = "default";
167 pinctrl-0 = <&pinctrl_uart0>;
173 compatible = "socionext,uniphier-uart";
177 pinctrl-names = "default";
178 pinctrl-0 = <&pinctrl_uart1>;
184 compatible = "socionext,uniphier-uart";
188 pinctrl-names = "default";
189 pinctrl-0 = <&pinctrl_uart2>;
195 compatible = "socionext,uniphier-uart";
199 pinctrl-names = "default";
200 pinctrl-0 = <&pinctrl_uart3>;
206 compatible = "socionext,uniphier-gpio";
208 interrupt-parent = <&aidet>;
209 interrupt-controller;
210 #interrupt-cells = <2>;
211 gpio-controller;
212 #gpio-cells = <2>;
213 gpio-ranges = <&pinctrl 0 0 0>,
219 gpio-ranges-group-names = "gpio_range0",
226 socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
231 compatible = "socionext,uniphier-ld11-aio";
234 pinctrl-names = "default";
235 pinctrl-0 = <&pinctrl_aout1>,
237 clock-names = "aio";
239 reset-names = "aio";
241 #sound-dai-cells = <1>;
256 dai-format = "i2s";
257 remote-endpoint = <&evea_line>;
268 dai-format = "i2s";
269 remote-endpoint = <&evea_hp>;
295 compatible = "socionext,uniphier-evea";
297 clock-names = "evea", "exiv";
299 reset-names = "evea", "exiv", "adamv";
301 #sound-dai-cells = <1>;
305 remote-endpoint = <&i2s_line>;
311 remote-endpoint = <&i2s_hp>;
317 compatible = "socionext,uniphier-ld11-adamv",
318 "simple-mfd", "syscon";
321 adamv_rst: reset-controller {
322 compatible = "socionext,uniphier-ld11-adamv-reset";
323 #reset-cells = <1>;
328 compatible = "socionext,uniphier-fi2c";
331 #address-cells = <1>;
332 #size-cells = <0>;
334 pinctrl-names = "default";
335 pinctrl-0 = <&pinctrl_i2c0>;
338 clock-frequency = <100000>;
342 compatible = "socionext,uniphier-fi2c";
345 #address-cells = <1>;
346 #size-cells = <0>;
348 pinctrl-names = "default";
349 pinctrl-0 = <&pinctrl_i2c1>;
352 clock-frequency = <100000>;
356 compatible = "socionext,uniphier-fi2c";
358 #address-cells = <1>;
359 #size-cells = <0>;
363 clock-frequency = <400000>;
367 compatible = "socionext,uniphier-fi2c";
370 #address-cells = <1>;
371 #size-cells = <0>;
373 pinctrl-names = "default";
374 pinctrl-0 = <&pinctrl_i2c3>;
377 clock-frequency = <100000>;
381 compatible = "socionext,uniphier-fi2c";
384 #address-cells = <1>;
385 #size-cells = <0>;
387 pinctrl-names = "default";
388 pinctrl-0 = <&pinctrl_i2c4>;
391 clock-frequency = <100000>;
395 compatible = "socionext,uniphier-fi2c";
397 #address-cells = <1>;
398 #size-cells = <0>;
402 clock-frequency = <400000>;
405 system_bus: system-bus@58c00000 {
406 compatible = "socionext,uniphier-system-bus";
409 #address-cells = <2>;
410 #size-cells = <1>;
411 pinctrl-names = "default";
412 pinctrl-0 = <&pinctrl_system_bus>;
416 compatible = "socionext,uniphier-smpctrl";
421 compatible = "socionext,uniphier-ld11-sdctrl",
422 "simple-mfd", "syscon";
425 sd_rst: reset-controller {
426 compatible = "socionext,uniphier-ld11-sd-reset";
427 #reset-cells = <1>;
432 compatible = "socionext,uniphier-ld11-perictrl",
433 "simple-mfd", "syscon";
436 peri_clk: clock-controller {
437 compatible = "socionext,uniphier-ld11-peri-clock";
438 #clock-cells = <1>;
441 peri_rst: reset-controller {
442 compatible = "socionext,uniphier-ld11-peri-reset";
443 #reset-cells = <1>;
448 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
451 pinctrl-names = "default";
452 pinctrl-0 = <&pinctrl_emmc>;
455 bus-width = <8>;
456 mmc-ddr-1_8v;
457 mmc-hs200-1_8v;
458 mmc-pwrseq = <&emmc_pwrseq>;
459 cdns,phy-input-delay-legacy = <9>;
460 cdns,phy-input-delay-mmc-highspeed = <2>;
461 cdns,phy-input-delay-mmc-ddr = <3>;
462 cdns,phy-dll-delay-sdclk = <21>;
463 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
467 compatible = "socionext,uniphier-ehci", "generic-ehci";
471 pinctrl-names = "default";
472 pinctrl-0 = <&pinctrl_usb0>;
477 phy-names = "usb";
479 has-transaction-translator;
483 compatible = "socionext,uniphier-ehci", "generic-ehci";
487 pinctrl-names = "default";
488 pinctrl-0 = <&pinctrl_usb1>;
493 phy-names = "usb";
495 has-transaction-translator;
499 compatible = "socionext,uniphier-ehci", "generic-ehci";
503 pinctrl-names = "default";
504 pinctrl-0 = <&pinctrl_usb2>;
509 phy-names = "usb";
511 has-transaction-translator;
515 compatible = "socionext,uniphier-ld11-mioctrl",
516 "simple-mfd", "syscon";
519 mio_clk: clock-controller {
520 compatible = "socionext,uniphier-ld11-mio-clock";
521 #clock-cells = <1>;
524 mio_rst: reset-controller {
525 compatible = "socionext,uniphier-ld11-mio-reset";
526 #reset-cells = <1>;
532 compatible = "socionext,uniphier-ld11-soc-glue",
533 "simple-mfd", "syscon";
537 compatible = "socionext,uniphier-ld11-pinctrl";
540 usb-hub {
541 compatible = "socionext,uniphier-ld11-usb2-phy";
542 #address-cells = <1>;
543 #size-cells = <0>;
547 #phy-cells = <0>;
552 #phy-cells = <0>;
557 #phy-cells = <0>;
563 compatible = "socionext,uniphier-ld11-soc-glue-debug",
564 "simple-mfd", "syscon";
566 #address-cells = <1>;
567 #size-cells = <1>;
571 compatible = "socionext,uniphier-efuse";
576 compatible = "socionext,uniphier-efuse";
581 xdmac: dma-controller@5fc10000 {
582 compatible = "socionext,uniphier-xdmac";
585 dma-channels = <16>;
586 #dma-cells = <2>;
589 aidet: interrupt-controller@5fc20000 {
590 compatible = "socionext,uniphier-ld11-aidet";
592 interrupt-controller;
593 #interrupt-cells = <2>;
596 gic: interrupt-controller@5fe00000 {
597 compatible = "arm,gic-v3";
600 interrupt-controller;
601 #interrupt-cells = <3>;
606 compatible = "socionext,uniphier-ld11-sysctrl",
607 "simple-mfd", "syscon";
610 sys_clk: clock-controller {
611 compatible = "socionext,uniphier-ld11-clock";
612 #clock-cells = <1>;
615 sys_rst: reset-controller {
616 compatible = "socionext,uniphier-ld11-reset";
617 #reset-cells = <1>;
621 compatible = "socionext,uniphier-wdt";
626 compatible = "socionext,uniphier-ld11-ave4";
630 clock-names = "ether";
632 reset-names = "ether";
634 phy-mode = "internal";
635 local-mac-address = [00 00 00 00 00 00];
636 socionext,syscon-phy-mode = <&soc_glue 0>;
639 #address-cells = <1>;
640 #size-cells = <0>;
644 nand: nand-controller@68000000 {
645 compatible = "socionext,uniphier-denali-nand-v5b";
647 reg-names = "nand_data", "denali_reg";
649 #address-cells = <1>;
650 #size-cells = <0>;
652 pinctrl-names = "default";
653 pinctrl-0 = <&pinctrl_nand>;
654 clock-names = "nand", "nand_x", "ecc";
656 reset-names = "nand", "reg";
662 #include "uniphier-pinctrl.dtsi"
665 drive-strength = <4>; /* default: 4mA */
669 drive-strength = <8>; /* 8mA */