Lines Matching +full:interconnect +full:- +full:names
1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/dma/qcom-gpi.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interconnect/qcom,osm-l3.h>
14 #include <dt-bindings/interconnect/qcom,sdm670-rpmh.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/phy/phy-qcom-qusb2.h>
17 #include <dt-bindings/power/qcom-rpmpd.h>
18 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
21 interrupt-parent = <&intc>;
23 #address-cells = <2>;
24 #size-cells = <2>;
31 #address-cells = <2>;
32 #size-cells = <0>;
38 enable-method = "psci";
39 capacity-dmips-mhz = <610>;
40 dynamic-power-coefficient = <203>;
41 qcom,freq-domain = <&cpufreq_hw 0>;
42 operating-points-v2 = <&cpu0_opp_table>;
45 power-domains = <&CPU_PD0>;
46 power-domain-names = "psci";
47 next-level-cache = <&L2_0>;
48 L2_0: l2-cache {
50 next-level-cache = <&L3_0>;
51 cache-level = <2>;
52 cache-unified;
53 L3_0: l3-cache {
55 cache-level = <3>;
56 cache-unified;
65 enable-method = "psci";
66 capacity-dmips-mhz = <610>;
67 dynamic-power-coefficient = <203>;
68 qcom,freq-domain = <&cpufreq_hw 0>;
69 operating-points-v2 = <&cpu0_opp_table>;
72 power-domains = <&CPU_PD1>;
73 power-domain-names = "psci";
74 next-level-cache = <&L2_100>;
75 L2_100: l2-cache {
77 cache-level = <2>;
78 cache-unified;
79 next-level-cache = <&L3_0>;
87 enable-method = "psci";
88 capacity-dmips-mhz = <610>;
89 dynamic-power-coefficient = <203>;
90 qcom,freq-domain = <&cpufreq_hw 0>;
91 operating-points-v2 = <&cpu0_opp_table>;
94 power-domains = <&CPU_PD2>;
95 power-domain-names = "psci";
96 next-level-cache = <&L2_200>;
97 L2_200: l2-cache {
99 cache-level = <2>;
100 cache-unified;
101 next-level-cache = <&L3_0>;
109 enable-method = "psci";
110 capacity-dmips-mhz = <610>;
111 dynamic-power-coefficient = <203>;
112 qcom,freq-domain = <&cpufreq_hw 0>;
113 operating-points-v2 = <&cpu0_opp_table>;
116 power-domains = <&CPU_PD3>;
117 power-domain-names = "psci";
118 next-level-cache = <&L2_300>;
119 L2_300: l2-cache {
121 cache-level = <2>;
122 cache-unified;
123 next-level-cache = <&L3_0>;
131 enable-method = "psci";
132 capacity-dmips-mhz = <610>;
133 dynamic-power-coefficient = <203>;
134 qcom,freq-domain = <&cpufreq_hw 0>;
135 operating-points-v2 = <&cpu0_opp_table>;
138 power-domains = <&CPU_PD4>;
139 power-domain-names = "psci";
140 next-level-cache = <&L2_400>;
141 L2_400: l2-cache {
143 cache-level = <2>;
144 cache-unified;
145 next-level-cache = <&L3_0>;
153 enable-method = "psci";
154 capacity-dmips-mhz = <610>;
155 dynamic-power-coefficient = <203>;
156 qcom,freq-domain = <&cpufreq_hw 0>;
157 operating-points-v2 = <&cpu0_opp_table>;
160 power-domains = <&CPU_PD5>;
161 power-domain-names = "psci";
162 next-level-cache = <&L2_500>;
163 L2_500: l2-cache {
165 cache-level = <2>;
166 cache-unified;
167 next-level-cache = <&L3_0>;
175 enable-method = "psci";
176 capacity-dmips-mhz = <1024>;
177 dynamic-power-coefficient = <393>;
178 qcom,freq-domain = <&cpufreq_hw 1>;
179 operating-points-v2 = <&cpu6_opp_table>;
182 power-domains = <&CPU_PD6>;
183 power-domain-names = "psci";
184 next-level-cache = <&L2_600>;
185 L2_600: l2-cache {
187 cache-level = <2>;
188 cache-unified;
189 next-level-cache = <&L3_0>;
197 enable-method = "psci";
198 capacity-dmips-mhz = <1024>;
199 dynamic-power-coefficient = <393>;
200 qcom,freq-domain = <&cpufreq_hw 1>;
201 operating-points-v2 = <&cpu6_opp_table>;
204 power-domains = <&CPU_PD7>;
205 power-domain-names = "psci";
206 next-level-cache = <&L2_700>;
207 L2_700: l2-cache {
209 cache-level = <2>;
210 cache-unified;
211 next-level-cache = <&L3_0>;
215 cpu-map {
251 idle-states {
252 entry-method = "psci";
254 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
255 compatible = "arm,idle-state";
256 idle-state-name = "little-rail-power-collapse";
257 arm,psci-suspend-param = <0x40000004>;
258 entry-latency-us = <702>;
259 exit-latency-us = <915>;
260 min-residency-us = <1617>;
261 local-timer-stop;
264 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
265 compatible = "arm,idle-state";
266 idle-state-name = "big-rail-power-collapse";
267 arm,psci-suspend-param = <0x40000004>;
268 entry-latency-us = <526>;
269 exit-latency-us = <1854>;
270 min-residency-us = <2380>;
271 local-timer-stop;
275 domain-idle-states {
276 CLUSTER_SLEEP_0: cluster-sleep-0 {
277 compatible = "domain-idle-state";
278 arm,psci-suspend-param = <0x4100c244>;
279 entry-latency-us = <3263>;
280 exit-latency-us = <6562>;
281 min-residency-us = <9825>;
288 compatible = "qcom,scm-sdm670", "qcom,scm";
298 cpu0_opp_table: opp-table-cpu0 {
299 compatible = "operating-points-v2";
300 opp-shared;
302 cpu0_opp1: opp-300000000 {
303 opp-hz = /bits/ 64 <300000000>;
304 opp-peak-kBps = <400000 4800000>;
307 cpu0_opp2: opp-576000000 {
308 opp-hz = /bits/ 64 <576000000>;
309 opp-peak-kBps = <400000 4800000>;
312 cpu0_opp3: opp-748800000 {
313 opp-hz = /bits/ 64 <748800000>;
314 opp-peak-kBps = <1200000 4800000>;
317 cpu0_opp4: opp-998400000 {
318 opp-hz = /bits/ 64 <998400000>;
319 opp-peak-kBps = <1804000 8908800>;
322 cpu0_opp5: opp-1209600000 {
323 opp-hz = /bits/ 64 <1209600000>;
324 opp-peak-kBps = <2188000 8908800>;
327 cpu0_opp6: opp-1324800000 {
328 opp-hz = /bits/ 64 <1324800000>;
329 opp-peak-kBps = <2188000 13516800>;
332 cpu0_opp7: opp-1516800000 {
333 opp-hz = /bits/ 64 <1516800000>;
334 opp-peak-kBps = <3072000 15052800>;
337 cpu0_opp8: opp-1612800000 {
338 opp-hz = /bits/ 64 <1612800000>;
339 opp-peak-kBps = <3072000 22118400>;
342 cpu0_opp9: opp-1708800000 {
343 opp-hz = /bits/ 64 <1708800000>;
344 opp-peak-kBps = <4068000 23040000>;
348 cpu6_opp_table: opp-table-cpu6 {
349 compatible = "operating-points-v2";
350 opp-shared;
352 cpu6_opp1: opp-300000000 {
353 opp-hz = /bits/ 64 <300000000>;
354 opp-peak-kBps = <400000 4800000>;
357 cpu6_opp2: opp-652800000 {
358 opp-hz = /bits/ 64 <652800000>;
359 opp-peak-kBps = <400000 4800000>;
362 cpu6_opp3: opp-825600000 {
363 opp-hz = /bits/ 64 <825600000>;
364 opp-peak-kBps = <1200000 4800000>;
367 cpu6_opp4: opp-979200000 {
368 opp-hz = /bits/ 64 <979200000>;
369 opp-peak-kBps = <1200000 4800000>;
372 cpu6_opp5: opp-1132800000 {
373 opp-hz = /bits/ 64 <1132800000>;
374 opp-peak-kBps = <2188000 8908800>;
377 cpu6_opp6: opp-1363200000 {
378 opp-hz = /bits/ 64 <1363200000>;
379 opp-peak-kBps = <4068000 12902400>;
382 cpu6_opp7: opp-1536000000 {
383 opp-hz = /bits/ 64 <1536000000>;
384 opp-peak-kBps = <4068000 12902400>;
387 cpu6_opp8: opp-1747200000 {
388 opp-hz = /bits/ 64 <1747200000>;
389 opp-peak-kBps = <4068000 15052800>;
392 cpu6_opp9: opp-1843200000 {
393 opp-hz = /bits/ 64 <1843200000>;
394 opp-peak-kBps = <4068000 15052800>;
397 cpu6_opp10: opp-1996800000 {
398 opp-hz = /bits/ 64 <1996800000>;
399 opp-peak-kBps = <6220000 19046400>;
404 compatible = "arm,psci-1.0";
407 CPU_PD0: power-domain-cpu0 {
408 #power-domain-cells = <0>;
409 power-domains = <&CLUSTER_PD>;
410 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
413 CPU_PD1: power-domain-cpu1 {
414 #power-domain-cells = <0>;
415 power-domains = <&CLUSTER_PD>;
416 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
419 CPU_PD2: power-domain-cpu2 {
420 #power-domain-cells = <0>;
421 power-domains = <&CLUSTER_PD>;
422 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
425 CPU_PD3: power-domain-cpu3 {
426 #power-domain-cells = <0>;
427 power-domains = <&CLUSTER_PD>;
428 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
431 CPU_PD4: power-domain-cpu4 {
432 #power-domain-cells = <0>;
433 power-domains = <&CLUSTER_PD>;
434 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
437 CPU_PD5: power-domain-cpu5 {
438 #power-domain-cells = <0>;
439 power-domains = <&CLUSTER_PD>;
440 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
443 CPU_PD6: power-domain-cpu6 {
444 #power-domain-cells = <0>;
445 power-domains = <&CLUSTER_PD>;
446 domain-idle-states = <&BIG_CPU_SLEEP_0>;
449 CPU_PD7: power-domain-cpu7 {
450 #power-domain-cells = <0>;
451 power-domains = <&CLUSTER_PD>;
452 domain-idle-states = <&BIG_CPU_SLEEP_0>;
455 CLUSTER_PD: power-domain-cluster {
456 #power-domain-cells = <0>;
457 domain-idle-states = <&CLUSTER_SLEEP_0>;
461 reserved-memory {
462 #address-cells = <2>;
463 #size-cells = <2>;
466 hyp_mem: hyp-mem@85700000 {
468 no-map;
471 xbl_mem: xbl-mem@85e00000 {
473 no-map;
476 aop_mem: aop-mem@85fc0000 {
478 no-map;
481 aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 {
482 compatible = "qcom,cmd-db";
484 no-map;
487 camera_mem: camera-mem@8ab00000 {
489 no-map;
494 no-map;
499 no-map;
502 wlan_msa_mem: wlan-msa@93300000 {
504 no-map;
509 no-map;
514 no-map;
519 no-map;
522 ipa_fw_mem: ipa-fw@95c00000 {
524 no-map;
527 ipa_gsi_mem: ipa-gsi@95c10000 {
529 no-map;
534 no-map;
539 no-map;
544 no-map;
549 compatible = "arm,armv8-timer";
557 #address-cells = <2>;
558 #size-cells = <2>;
560 dma-ranges = <0 0 0 0 0x10 0>;
561 compatible = "simple-bus";
563 gcc: clock-controller@100000 {
564 compatible = "qcom,gcc-sdm670";
569 clock-names = "bi_tcxo",
572 #clock-cells = <1>;
573 #reset-cells = <1>;
574 #power-domain-cells = <1>;
578 compatible = "qcom,sdm670-qfprom", "qcom,qfprom";
580 #address-cells = <1>;
581 #size-cells = <1>;
583 qusb2_hstx_trim: hstx-trim@1eb {
590 compatible = "qcom,sdm670-sdhci", "qcom,sdhci-msm-v5";
594 reg-names = "hc", "cqhci", "ice";
598 interrupt-names = "hc_irq", "pwr_irq";
605 clock-names = "iface", "core", "xo", "ice", "bus";
608 interconnect-names = "sdhc-ddr", "cpu-sdhc";
609 operating-points-v2 = <&sdhc1_opp_table>;
613 pinctrl-names = "default", "sleep";
614 pinctrl-0 = <&sdc1_state_on>;
615 pinctrl-1 = <&sdc1_state_off>;
616 power-domains = <&rpmhpd SDM670_CX>;
618 bus-width = <8>;
619 non-removable;
623 sdhc1_opp_table: opp-table {
624 compatible = "operating-points-v2";
626 opp-20000000 {
627 opp-hz = /bits/ 64 <20000000>;
628 required-opps = <&rpmhpd_opp_min_svs>;
629 opp-peak-kBps = <80000 80000>;
630 opp-avg-kBps = <52286 80000>;
633 opp-50000000 {
634 opp-hz = /bits/ 64 <50000000>;
635 required-opps = <&rpmhpd_opp_low_svs>;
636 opp-peak-kBps = <200000 100000>;
637 opp-avg-kBps = <130718 100000>;
640 opp-100000000 {
641 opp-hz = /bits/ 64 <100000000>;
642 required-opps = <&rpmhpd_opp_svs>;
643 opp-peak-kBps = <200000 130000>;
644 opp-avg-kBps = <130718 130000>;
647 opp-384000000 {
648 opp-hz = /bits/ 64 <384000000>;
649 required-opps = <&rpmhpd_opp_nom>;
650 opp-peak-kBps = <4096000 4096000>;
651 opp-avg-kBps = <1338562 1338562>;
656 gpi_dma0: dma-controller@800000 {
657 #dma-cells = <3>;
658 compatible = "qcom,sdm670-gpi-dma", "qcom,sdm845-gpi-dma";
673 dma-channels = <13>;
674 dma-channel-mask = <0xfa>;
680 compatible = "qcom,geni-se-qup";
682 clock-names = "m-ahb", "s-ahb";
686 #address-cells = <2>;
687 #size-cells = <2>;
690 interconnect-names = "qup-core";
694 compatible = "qcom,geni-i2c";
696 clock-names = "se";
698 pinctrl-names = "default";
699 pinctrl-0 = <&qup_i2c0_default>;
701 #address-cells = <1>;
702 #size-cells = <0>;
703 power-domains = <&rpmhpd SDM670_CX>;
707 interconnect-names = "qup-core", "qup-config", "qup-memory";
710 dma-names = "tx", "rx";
715 compatible = "qcom,geni-i2c";
717 clock-names = "se";
719 pinctrl-names = "default";
720 pinctrl-0 = <&qup_i2c1_default>;
722 #address-cells = <1>;
723 #size-cells = <0>;
724 power-domains = <&rpmhpd SDM670_CX>;
728 interconnect-names = "qup-core", "qup-config", "qup-memory";
731 dma-names = "tx", "rx";
736 compatible = "qcom,geni-i2c";
738 clock-names = "se";
740 pinctrl-names = "default";
741 pinctrl-0 = <&qup_i2c2_default>;
743 #address-cells = <1>;
744 #size-cells = <0>;
745 power-domains = <&rpmhpd SDM670_CX>;
749 interconnect-names = "qup-core", "qup-config", "qup-memory";
752 dma-names = "tx", "rx";
757 compatible = "qcom,geni-i2c";
759 clock-names = "se";
761 pinctrl-names = "default";
762 pinctrl-0 = <&qup_i2c3_default>;
764 #address-cells = <1>;
765 #size-cells = <0>;
766 power-domains = <&rpmhpd SDM670_CX>;
770 interconnect-names = "qup-core", "qup-config", "qup-memory";
773 dma-names = "tx", "rx";
778 compatible = "qcom,geni-i2c";
780 clock-names = "se";
782 pinctrl-names = "default";
783 pinctrl-0 = <&qup_i2c4_default>;
785 #address-cells = <1>;
786 #size-cells = <0>;
787 power-domains = <&rpmhpd SDM670_CX>;
791 interconnect-names = "qup-core", "qup-config", "qup-memory";
794 dma-names = "tx", "rx";
799 compatible = "qcom,geni-i2c";
801 clock-names = "se";
803 pinctrl-names = "default";
804 pinctrl-0 = <&qup_i2c5_default>;
806 #address-cells = <1>;
807 #size-cells = <0>;
808 power-domains = <&rpmhpd SDM670_CX>;
812 interconnect-names = "qup-core", "qup-config", "qup-memory";
815 dma-names = "tx", "rx";
820 compatible = "qcom,geni-i2c";
822 clock-names = "se";
824 pinctrl-names = "default";
825 pinctrl-0 = <&qup_i2c6_default>;
827 #address-cells = <1>;
828 #size-cells = <0>;
829 power-domains = <&rpmhpd SDM670_CX>;
833 interconnect-names = "qup-core", "qup-config", "qup-memory";
836 dma-names = "tx", "rx";
841 compatible = "qcom,geni-i2c";
843 clock-names = "se";
845 pinctrl-names = "default";
846 pinctrl-0 = <&qup_i2c7_default>;
848 #address-cells = <1>;
849 #size-cells = <0>;
850 power-domains = <&rpmhpd SDM670_CX>;
854 interconnect-names = "qup-core", "qup-config", "qup-memory";
857 dma-names = "tx", "rx";
862 gpi_dma1: dma-controller@a00000 {
863 #dma-cells = <3>;
864 compatible = "qcom,sdm670-gpi-dma", "qcom,sdm845-gpi-dma";
879 dma-channels = <13>;
880 dma-channel-mask = <0xfa>;
886 compatible = "qcom,geni-se-qup";
888 clock-names = "m-ahb", "s-ahb";
892 #address-cells = <2>;
893 #size-cells = <2>;
896 interconnect-names = "qup-core";
900 compatible = "qcom,geni-i2c";
902 clock-names = "se";
904 pinctrl-names = "default";
905 pinctrl-0 = <&qup_i2c8_default>;
907 #address-cells = <1>;
908 #size-cells = <0>;
909 power-domains = <&rpmhpd SDM670_CX>;
913 interconnect-names = "qup-core", "qup-config", "qup-memory";
916 dma-names = "tx", "rx";
921 compatible = "qcom,geni-i2c";
923 clock-names = "se";
925 pinctrl-names = "default";
926 pinctrl-0 = <&qup_i2c9_default>;
928 #address-cells = <1>;
929 #size-cells = <0>;
930 power-domains = <&rpmhpd SDM670_CX>;
934 interconnect-names = "qup-core", "qup-config", "qup-memory";
937 dma-names = "tx", "rx";
942 compatible = "qcom,geni-i2c";
944 clock-names = "se";
946 pinctrl-names = "default";
947 pinctrl-0 = <&qup_i2c10_default>;
949 #address-cells = <1>;
950 #size-cells = <0>;
951 power-domains = <&rpmhpd SDM670_CX>;
955 interconnect-names = "qup-core", "qup-config", "qup-memory";
958 dma-names = "tx", "rx";
963 compatible = "qcom,geni-i2c";
965 clock-names = "se";
967 pinctrl-names = "default";
968 pinctrl-0 = <&qup_i2c11_default>;
970 #address-cells = <1>;
971 #size-cells = <0>;
972 power-domains = <&rpmhpd SDM670_CX>;
976 interconnect-names = "qup-core", "qup-config", "qup-memory";
979 dma-names = "tx", "rx";
984 compatible = "qcom,geni-i2c";
986 clock-names = "se";
988 pinctrl-names = "default";
989 pinctrl-0 = <&qup_i2c12_default>;
991 #address-cells = <1>;
992 #size-cells = <0>;
993 power-domains = <&rpmhpd SDM670_CX>;
997 interconnect-names = "qup-core", "qup-config", "qup-memory";
1000 dma-names = "tx", "rx";
1005 compatible = "qcom,geni-i2c";
1007 clock-names = "se";
1009 pinctrl-names = "default";
1010 pinctrl-0 = <&qup_i2c13_default>;
1012 #address-cells = <1>;
1013 #size-cells = <0>;
1014 power-domains = <&rpmhpd SDM670_CX>;
1018 interconnect-names = "qup-core", "qup-config", "qup-memory";
1021 dma-names = "tx", "rx";
1026 compatible = "qcom,geni-i2c";
1028 clock-names = "se";
1030 pinctrl-names = "default";
1031 pinctrl-0 = <&qup_i2c14_default>;
1033 #address-cells = <1>;
1034 #size-cells = <0>;
1035 power-domains = <&rpmhpd SDM670_CX>;
1039 interconnect-names = "qup-core", "qup-config", "qup-memory";
1042 dma-names = "tx", "rx";
1047 compatible = "qcom,geni-i2c";
1049 clock-names = "se";
1051 pinctrl-names = "default";
1052 pinctrl-0 = <&qup_i2c15_default>;
1054 #address-cells = <1>;
1055 #size-cells = <0>;
1056 power-domains = <&rpmhpd SDM670_CX>;
1060 interconnect-names = "qup-core", "qup-config", "qup-memory";
1063 dma-names = "tx", "rx";
1068 mem_noc: interconnect@1380000 {
1069 compatible = "qcom,sdm670-mem-noc";
1071 #interconnect-cells = <2>;
1072 qcom,bcm-voters = <&apps_bcm_voter>;
1075 dc_noc: interconnect@14e0000 {
1076 compatible = "qcom,sdm670-dc-noc";
1078 #interconnect-cells = <2>;
1079 qcom,bcm-voters = <&apps_bcm_voter>;
1082 config_noc: interconnect@1500000 {
1083 compatible = "qcom,sdm670-config-noc";
1085 #interconnect-cells = <2>;
1086 qcom,bcm-voters = <&apps_bcm_voter>;
1089 system_noc: interconnect@1620000 {
1090 compatible = "qcom,sdm670-system-noc";
1092 #interconnect-cells = <2>;
1093 qcom,bcm-voters = <&apps_bcm_voter>;
1096 aggre1_noc: interconnect@16e0000 {
1097 compatible = "qcom,sdm670-aggre1-noc";
1099 #interconnect-cells = <2>;
1100 qcom,bcm-voters = <&apps_bcm_voter>;
1103 aggre2_noc: interconnect@1700000 {
1104 compatible = "qcom,sdm670-aggre2-noc";
1106 #interconnect-cells = <2>;
1107 qcom,bcm-voters = <&apps_bcm_voter>;
1110 mmss_noc: interconnect@1740000 {
1111 compatible = "qcom,sdm670-mmss-noc";
1113 #interconnect-cells = <2>;
1114 qcom,bcm-voters = <&apps_bcm_voter>;
1118 compatible = "qcom,sdm670-tlmm";
1121 gpio-controller;
1122 #gpio-cells = <2>;
1123 interrupt-controller;
1124 #interrupt-cells = <2>;
1125 gpio-ranges = <&tlmm 0 0 151>;
1126 wakeup-parent = <&pdc>;
1128 qup_i2c0_default: qup-i2c0-default-state {
1133 qup_i2c1_default: qup-i2c1-default-state {
1138 qup_i2c2_default: qup-i2c2-default-state {
1143 qup_i2c3_default: qup-i2c3-default-state {
1148 qup_i2c4_default: qup-i2c4-default-state {
1153 qup_i2c5_default: qup-i2c5-default-state {
1158 qup_i2c6_default: qup-i2c6-default-state {
1163 qup_i2c7_default: qup-i2c7-default-state {
1168 qup_i2c8_default: qup-i2c8-default-state {
1173 qup_i2c9_default: qup-i2c9-default-state {
1178 qup_i2c10_default: qup-i2c10-default-state {
1183 qup_i2c11_default: qup-i2c11-default-state {
1188 qup_i2c12_default: qup-i2c12-default-state {
1193 qup_i2c13_default: qup-i2c13-default-state {
1198 qup_i2c14_default: qup-i2c14-default-state {
1203 qup_i2c15_default: qup-i2c15-default-state {
1208 sdc1_state_on: sdc1-on-state {
1209 clk-pins {
1211 bias-disable;
1212 drive-strength = <16>;
1215 cmd-pins {
1217 bias-pull-up;
1218 drive-strength = <10>;
1221 data-pins {
1223 bias-pull-up;
1224 drive-strength = <10>;
1227 rclk-pins {
1229 bias-pull-down;
1233 sdc1_state_off: sdc1-off-state {
1234 clk-pins {
1236 bias-disable;
1237 drive-strength = <2>;
1240 cmd-pins {
1242 bias-pull-up;
1243 drive-strength = <2>;
1246 data-pins {
1248 bias-pull-up;
1249 drive-strength = <2>;
1252 rclk-pins {
1254 bias-pull-down;
1260 compatible = "qcom,sdm670-qusb2-phy", "qcom,qusb2-v2-phy";
1262 #phy-cells = <0>;
1266 clock-names = "cfg_ahb", "ref";
1270 nvmem-cells = <&qusb2_hstx_trim>;
1276 compatible = "qcom,sdm670-dwc3", "qcom,dwc3";
1278 #address-cells = <2>;
1279 #size-cells = <2>;
1281 dma-ranges;
1288 clock-names = "cfg_noc",
1294 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1296 assigned-clock-rates = <19200000>, <150000000>;
1298 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
1302 interrupt-names = "hs_phy_irq", "ss_phy_irq",
1305 power-domains = <&gcc USB30_PRIM_GDSC>;
1311 interconnect-names = "usb-ddr", "apps-usb";
1323 phy-names = "usb2-phy";
1327 pdc: interrupt-controller@b220000 {
1328 compatible = "qcom,sdm670-pdc", "qcom,pdc";
1330 qcom,pdc-ranges = <0 480 40>, <41 521 7>, <49 529 4>,
1333 #interrupt-cells = <2>;
1334 interrupt-parent = <&intc>;
1335 interrupt-controller;
1339 compatible = "qcom,spmi-pmic-arb";
1345 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1346 interrupt-names = "periph_irq";
1350 #address-cells = <2>;
1351 #size-cells = <0>;
1352 interrupt-controller;
1353 #interrupt-cells = <4>;
1357 compatible = "qcom,sdm670-smmu-500", "qcom,smmu-500", "arm,mmu-500";
1359 #iommu-cells = <2>;
1360 #global-interrupts = <1>;
1428 gladiator_noc: interconnect@17900000 {
1429 compatible = "qcom,sdm670-gladiator-noc";
1431 #interconnect-cells = <2>;
1432 qcom,bcm-voters = <&apps_bcm_voter>;
1436 compatible = "qcom,rpmh-rsc";
1440 reg-names = "drv-0", "drv-1", "drv-2";
1445 qcom,tcs-offset = <0xd00>;
1446 qcom,drv-id = <2>;
1447 qcom,tcs-config = <ACTIVE_TCS 2>,
1451 power-domains = <&CLUSTER_PD>;
1453 apps_bcm_voter: bcm-voter {
1454 compatible = "qcom,bcm-voter";
1457 rpmhcc: clock-controller {
1458 compatible = "qcom,sdm670-rpmh-clk";
1459 #clock-cells = <1>;
1460 clock-names = "xo";
1464 rpmhpd: power-controller {
1465 compatible = "qcom,sdm670-rpmhpd";
1466 #power-domain-cells = <1>;
1467 operating-points-v2 = <&rpmhpd_opp_table>;
1469 rpmhpd_opp_table: opp-table {
1470 compatible = "operating-points-v2";
1473 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
1477 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1481 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1485 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1489 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1493 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1497 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1501 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
1505 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1509 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1515 intc: interrupt-controller@17a00000 {
1516 compatible = "arm,gic-v3";
1519 interrupt-controller;
1521 #interrupt-cells = <3>;
1524 osm_l3: interconnect@17d41000 {
1525 compatible = "qcom,sdm670-osm-l3", "qcom,osm-l3";
1529 clock-names = "xo", "alternate";
1531 #interconnect-cells = <1>;
1535 compatible = "qcom,cpufreq-hw";
1537 reg-names = "freq-domain0", "freq-domain1";
1540 clock-names = "xo", "alternate";
1542 #freq-domain-cells = <1>;